opcodes/ChangeLog

   1 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
   2
   3         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
   4         instructions.
   5
   6 2019-07-30  Mel Chen <mel.chen@sifive.com>
   7
   8         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
   9         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
  10
  11         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
  12         fscsr.
  13
  14 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
  15
  16         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
  17         and MPY class instructions.
  18         (parse_option): Add nps400 option.
  19         (print_arc_disassembler_options): Add nps400 info.
  20
  21 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
  22
  23         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
  24         (bspop): Likewise.
  25         (modapp): Likewise.
  26         * arc-opc.c (RAD_CHK): Add.
  27         * arc-tbl.h: Regenerate.
  28
  29 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  30
  31         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
  32         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
  33
  34 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
  35
  36         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
  37         instructions as UNPREDICTABLE.
  38
  39 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
  40
  41         * bpf-desc.c: Regenerated.
  42
  43 2019-07-17  Jan Beulich  <jbeulich@suse.com>
  44
  45         * i386-gen.c (static_assert): Define.
  46         (main): Use it.
  47         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
  48         (Opcode_Modifier_Num): ... this.
  49         (Mem): Delete.
  50
  51 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-gen.c (operand_types): Move RegMem ...
  54         (opcode_modifiers): ... here.
  55         * i386-opc.h (RegMem): Move to opcode modifer enum.
  56         (union i386_operand_type): Move regmem field ...
  57         (struct i386_opcode_modifier): ... here.
  58         * i386-opc.tbl (RegMem): Define.
  59         (mov, movq): Move RegMem on segment, control, debug, and test
  60         register flavors.
  61         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
  62         to non-SSE2AVX flavor.
  63         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
  64         Move RegMem on register only flavors. Drop IgnoreSize from
  65         legacy encoding flavors.
  66         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
  67         flavors.
  68         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
  69         register only flavors.
  70         (vmovd): Move RegMem and drop IgnoreSize on register only
  71         flavor. Change opcode and operand order to store form.
  72         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  73
  74 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  75
  76         * i386-gen.c (operand_type_init, operand_types): Replace SReg
  77         entries.
  78         * i386-opc.h (SReg2, SReg3): Replace by ...
  79         (SReg): ... this.
  80         (union i386_operand_type): Replace sreg fields.
  81         * i386-opc.tbl (mov, ): Use SReg.
  82         (push, pop): Likewies. Drop i386 and x86-64 specific segment
  83         register flavors.
  84         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
  85         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  86
  87 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
  88
  89         * bpf-desc.c: Regenerate.
  90         * bpf-opc.c: Likewise.
  91         * bpf-opc.h: Likewise.
  92
  93 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
  94
  95         * bpf-desc.c: Regenerate.
  96         * bpf-opc.c: Likewise.
  97
  98 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
  99
 100         * arm-dis.c (print_insn_coprocessor): Rename index to
 101         index_operand.
 102
 103 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 104
 105         * riscv-opc.c (riscv_insn_types): Add r4 type.
 106
 107         * riscv-opc.c (riscv_insn_types): Add b and j type.
 108
 109         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 110         format for sb type and correct s type.
 111
 112 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 113
 114         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 115         SVE FMOV alias of FCPY.
 116
 117 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 118
 119         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 120         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 121
 122 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 123
 124         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 125         registers in an instruction prefixed by MOVPRFX.
 126
 127 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 128
 129         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 130         sve_size_13 icode to account for variant behaviour of
 131         pmull{t,b}.
 132         * aarch64-dis-2.c: Regenerate.
 133         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 134         sve_size_13 icode to account for variant behaviour of
 135         pmull{t,b}.
 136         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 137         (OP_SVE_VVV_Q_D): Add new qualifier.
 138         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 139         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 140         AES and those not.
 141
 142 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 143
 144         * opcodes/i386-gen.c (operand_type_init): Remove
 145         OPERAND_TYPE_VEC_IMM4 entry.
 146         (operand_types): Remove Vec_Imm4.
 147         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 148         (union i386_operand_type): Remove vec_imm4.
 149         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 150         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 151
 152 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 153
 154         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 155         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 156         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 157         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 158         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 159         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 160         * i386-tbl.h: Re-generate.
 161
 162 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 163
 164         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 165         register operands.
 166         * i386-tbl.h: Re-generate.
 167
 168 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-opc.tbl (C): New.
 171         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 172         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 173         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 174         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 175         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 176         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 177         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 178         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 179         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 180         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 181         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 182         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 183         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 184         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 185         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 186         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 187         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 188         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 189         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 190         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 191         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 192         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 193         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 194         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 195         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 196         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 197         flavors.
 198         * i386-tbl.h: Re-generate.
 199
 200 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 201
 202         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 203         register operands.
 204         * i386-tbl.h: Re-generate.
 205
 206 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 207
 208         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 209         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 210         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 211         * i386-tbl.h: Re-generate.
 212
 213 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 214
 215         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 216         Disp8MemShift from register only templates.
 217         * i386-tbl.h: Re-generate.
 218
 219 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 220
 221         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 222         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 223         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 224         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 225         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 226         EVEX_W_0F11_P_3_M_1): Delete.
 227         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 228         EVEX_W_0F11_P_3): New.
 229         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 230         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 231         MOD_EVEX_0F11_PREFIX_3 table entries.
 232         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 233         PREFIX_EVEX_0F11 table entries.
 234         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 235         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 236         EVEX_W_0F11_P_3_M_{0,1} table entries.
 237
 238 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 239
 240         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 241         Delete.
 242
 243 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 244
 245         PR binutils/24719
 246         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 247         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 248         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 249         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 250         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 251         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 252         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 253         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 254         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 255         PREFIX_EVEX_0F38C6_REG_6 entries.
 256         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 257         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 258         EVEX_W_0F38C7_R_6_P_2 entries.
 259         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 260         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 261         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 262         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 263         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 264         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 265         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 266
 267 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 268
 269         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 270         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 271         VEX_LEN_0F2D_P_3): Delete.
 272         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 273         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 274         (prefix_table): ... here.
 275
 276 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 277
 278         * i386-dis.c (Iq): Delete.
 279         (Id): New.
 280         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 281         TBM insns.
 282         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 283         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 284         (OP_E_memory): Also honor needindex when deciding whether an
 285         address size prefix needs printing.
 286         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 287
 288 2019-06-26  Jim Wilson  <jimw@sifive.com>
 289
 290         PR binutils/24739
 291         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 292         Set info->display_endian to info->endian_code.
 293
 294 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 295
 296         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 297         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 298         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 299         OPERAND_TYPE_ACC64 entries.
 300         * i386-init.h: Re-generate.
 301
 302 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 303
 304         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 305         Delete.
 306         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 307         of dqa_mode.
 308         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 309         entries here.
 310         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 311         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 312
 313 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 314
 315         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 316         variables.
 317
 318 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 319
 320         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 321         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 322         movnti.
 323         * i386-opc.tbl (movnti): Add IgnoreSize.
 324         * i386-tbl.h: Re-generate.
 325
 326 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 327
 328         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 329         * i386-tbl.h: Re-generate.
 330
 331 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 332
 333         * i386-dis-evex.h: Break into ...
 334         * i386-dis-evex-len.h: New file.
 335         * i386-dis-evex-mod.h: Likewise.
 336         * i386-dis-evex-prefix.h: Likewise.
 337         * i386-dis-evex-reg.h: Likewise.
 338         * i386-dis-evex-w.h: Likewise.
 339         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 340         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 341         i386-dis-evex-mod.h.
 342
 343 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 344
 345         PR binutils/24700
 346         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 347         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 348         EVEX_W_0F385B_P_2.
 349         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 350         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 351         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 352         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 353         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 354         EVEX_LEN_0F385B_P_2_W_1.
 355         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 356         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 357         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 358         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 359         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 360         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 361         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 362         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 363         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 364         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 365
 366 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 367
 368         PR binutils/24691
 369         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 370         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 371         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 372         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 373         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 374         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 375         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 376         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 377         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 378         EVEX_LEN_0F3A43_P_2_W_1.
 379         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 380         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 381         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 382         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 383         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 384         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 385         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 386         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 387         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 388         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 389         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 390         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 391
 392 2019-06-14  Nick Clifton  <nickc@redhat.com>
 393
 394         * po/fr.po; Updated French translation.
 395
 396 2019-06-13  Stafford Horne  <shorne@gmail.com>
 397
 398         * or1k-asm.c: Regenerated.
 399         * or1k-desc.c: Regenerated.
 400         * or1k-desc.h: Regenerated.
 401         * or1k-dis.c: Regenerated.
 402         * or1k-ibld.c: Regenerated.
 403         * or1k-opc.c: Regenerated.
 404         * or1k-opc.h: Regenerated.
 405         * or1k-opinst.c: Regenerated.
 406
 407 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 408
 409         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 410
 411 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 412
 413         PR binutils/24633
 414         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 415         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 416         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 417         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 418         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 419         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 420         EVEX_LEN_0F3A1B_P_2_W_1.
 421         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 422         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 423         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 424         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 425         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 426         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 427         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 428         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 429
 430 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 431
 432         PR binutils/24626
 433         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 434         EVEX.vvvv when disassembling VEX and EVEX instructions.
 435         (OP_VEX): Set vex.register_specifier to 0 after readding
 436         vex.register_specifier.
 437         (OP_Vex_2src_1): Likewise.
 438         (OP_Vex_2src_2): Likewise.
 439         (OP_LWP_E): Likewise.
 440         (OP_EX_Vex): Don't check vex.register_specifier.
 441         (OP_XMM_Vex): Likewise.
 442
 443 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 444             Lili Cui  <lili.cui@intel.com>
 445
 446         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 447         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 448         instructions.
 449         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 450         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 451         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 452         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 453         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 454         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 455         * i386-init.h: Regenerated.
 456         * i386-tbl.h: Likewise.
 457
 458 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 459             Lili Cui  <lili.cui@intel.com>
 460
 461         * doc/c-i386.texi: Document enqcmd.
 462         * testsuite/gas/i386/enqcmd-intel.d: New file.
 463         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 464         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 465         * testsuite/gas/i386/enqcmd.d: Likewise.
 466         * testsuite/gas/i386/enqcmd.s: Likewise.
 467         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 468         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 469         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 470         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 471         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 472         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 473         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 474         and x86-64-enqcmd.
 475
 476 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 477
 478         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 479
 480 2019-06-03  Alan Modra  <amodra@gmail.com>
 481
 482         * ppc-dis.c (prefix_opcd_indices): Correct size.
 483
 484 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 485
 486         PR gas/24625
 487         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 488         Disp8ShiftVL.
 489         * i386-tbl.h: Regenerated.
 490
 491 2019-05-24  Alan Modra  <amodra@gmail.com>
 492
 493         * po/POTFILES.in: Regenerate.
 494
 495 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 496             Alan Modra  <amodra@gmail.com>
 497
 498         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 499         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 500         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 501         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 502         XTOP>): Define and add entries.
 503         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 504         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 505         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 506         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 507
 508 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 509             Alan Modra  <amodra@gmail.com>
 510
 511         * ppc-dis.c (ppc_opts): Add "future" entry.
 512         (PREFIX_OPCD_SEGS): Define.
 513         (prefix_opcd_indices): New array.
 514         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 515         (lookup_prefix): New function.
 516         (print_insn_powerpc): Handle 64-bit prefix instructions.
 517         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 518         (PMRR, POWERXX): Define.
 519         (prefix_opcodes): New instruction table.
 520         (prefix_num_opcodes): New constant.
 521
 522 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 523
 524         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 525         * configure: Regenerated.
 526         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 527         and cpu/bpf.opc.
 528         (HFILES): Add bpf-desc.h and bpf-opc.h.
 529         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 530         bpf-ibld.c and bpf-opc.c.
 531         (BPF_DEPS): Define.
 532         * Makefile.in: Regenerated.
 533         * disassemble.c (ARCH_bpf): Define.
 534         (disassembler): Add case for bfd_arch_bpf.
 535         (disassemble_init_for_target): Likewise.
 536         (enum epbf_isa_attr): Define.
 537         * disassemble.h: extern print_insn_bpf.
 538         * bpf-asm.c: Generated.
 539         * bpf-opc.h: Likewise.
 540         * bpf-opc.c: Likewise.
 541         * bpf-ibld.c: Likewise.
 542         * bpf-dis.c: Likewise.
 543         * bpf-desc.h: Likewise.
 544         * bpf-desc.c: Likewise.
 545
 546 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 547
 548         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 549         and VMSR with the new operands.
 550
 551 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 552
 553         * arm-dis.c (enum mve_instructions): New enum
 554         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 555         and cneg.
 556         (mve_opcodes): New instructions as above.
 557         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 558         csneg and csel.
 559         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 560
 561 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 562
 563         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 564         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 565         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 566         uqshl, urshrl and urshr.
 567         (is_mve_okay_in_it): Add new instructions to TRUE list.
 568         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 569         (print_insn_mve): Updated to accept new %j,
 570         %<bitfield>m and %<bitfield>n patterns.
 571
 572 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 573
 574         * mips-opc.c (mips_builtin_opcodes): Change source register
 575         constraint for DAUI.
 576
 577 2019-05-20  Nick Clifton  <nickc@redhat.com>
 578
 579         * po/fr.po: Updated French translation.
 580
 581 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 582             Michael Collison <michael.collison@arm.com>
 583
 584         * arm-dis.c (thumb32_opcodes): Add new instructions.
 585         (enum mve_instructions): Likewise.
 586         (enum mve_undefined): Add new reasons.
 587         (is_mve_encoding_conflict): Handle new instructions.
 588         (is_mve_undefined): Likewise.
 589         (is_mve_unpredictable): Likewise.
 590         (print_mve_undefined): Likewise.
 591         (print_mve_size): Likewise.
 592
 593 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 594             Michael Collison <michael.collison@arm.com>
 595
 596         * arm-dis.c (thumb32_opcodes): Add new instructions.
 597         (enum mve_instructions): Likewise.
 598         (is_mve_encoding_conflict): Handle new instructions.
 599         (is_mve_undefined): Likewise.
 600         (is_mve_unpredictable): Likewise.
 601         (print_mve_size): Likewise.
 602
 603 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 604             Michael Collison <michael.collison@arm.com>
 605
 606         * arm-dis.c (thumb32_opcodes): Add new instructions.
 607         (enum mve_instructions): Likewise.
 608         (is_mve_encoding_conflict): Likewise.
 609         (is_mve_unpredictable): Likewise.
 610         (print_mve_size): Likewise.
 611
 612 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 613             Michael Collison <michael.collison@arm.com>
 614
 615         * arm-dis.c (thumb32_opcodes): Add new instructions.
 616         (enum mve_instructions): Likewise.
 617         (is_mve_encoding_conflict): Handle new instructions.
 618         (is_mve_undefined): Likewise.
 619         (is_mve_unpredictable): Likewise.
 620         (print_mve_size): Likewise.
 621
 622 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 623             Michael Collison <michael.collison@arm.com>
 624
 625         * arm-dis.c (thumb32_opcodes): Add new instructions.
 626         (enum mve_instructions): Likewise.
 627         (is_mve_encoding_conflict): Handle new instructions.
 628         (is_mve_undefined): Likewise.
 629         (is_mve_unpredictable): Likewise.
 630         (print_mve_size): Likewise.
 631         (print_insn_mve): Likewise.
 632
 633 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 634             Michael Collison <michael.collison@arm.com>
 635
 636         * arm-dis.c (thumb32_opcodes): Add new instructions.
 637         (print_insn_thumb32): Handle new instructions.
 638
 639 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 640             Michael Collison <michael.collison@arm.com>
 641
 642         * arm-dis.c (enum mve_instructions): Add new instructions.
 643         (enum mve_undefined): Add new reasons.
 644         (is_mve_encoding_conflict): Handle new instructions.
 645         (is_mve_undefined): Likewise.
 646         (is_mve_unpredictable): Likewise.
 647         (print_mve_undefined): Likewise.
 648         (print_mve_size): Likewise.
 649         (print_mve_shift_n): Likewise.
 650         (print_insn_mve): Likewise.
 651
 652 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 653             Michael Collison <michael.collison@arm.com>
 654
 655         * arm-dis.c (enum mve_instructions): Add new instructions.
 656         (is_mve_encoding_conflict): Handle new instructions.
 657         (is_mve_unpredictable): Likewise.
 658         (print_mve_rotate): Likewise.
 659         (print_mve_size): Likewise.
 660         (print_insn_mve): Likewise.
 661
 662 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 663             Michael Collison <michael.collison@arm.com>
 664
 665         * arm-dis.c (enum mve_instructions): Add new instructions.
 666         (is_mve_encoding_conflict): Handle new instructions.
 667         (is_mve_unpredictable): Likewise.
 668         (print_mve_size): Likewise.
 669         (print_insn_mve): Likewise.
 670
 671 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 672             Michael Collison <michael.collison@arm.com>
 673
 674         * arm-dis.c (enum mve_instructions): Add new instructions.
 675         (enum mve_undefined): Add new reasons.
 676         (is_mve_encoding_conflict): Handle new instructions.
 677         (is_mve_undefined): Likewise.
 678         (is_mve_unpredictable): Likewise.
 679         (print_mve_undefined): Likewise.
 680         (print_mve_size): Likewise.
 681         (print_insn_mve): Likewise.
 682
 683 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 684             Michael Collison <michael.collison@arm.com>
 685
 686         * arm-dis.c (enum mve_instructions): Add new instructions.
 687         (is_mve_encoding_conflict): Handle new instructions.
 688         (is_mve_undefined): Likewise.
 689         (is_mve_unpredictable): Likewise.
 690         (print_mve_size): Likewise.
 691         (print_insn_mve): Likewise.
 692
 693 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 694             Michael Collison <michael.collison@arm.com>
 695
 696         * arm-dis.c (enum mve_instructions): Add new instructions.
 697         (enum mve_unpredictable): Add new reasons.
 698         (enum mve_undefined): Likewise.
 699         (is_mve_okay_in_it): Handle new isntructions.
 700         (is_mve_encoding_conflict): Likewise.
 701         (is_mve_undefined): Likewise.
 702         (is_mve_unpredictable): Likewise.
 703         (print_mve_vmov_index): Likewise.
 704         (print_simd_imm8): Likewise.
 705         (print_mve_undefined): Likewise.
 706         (print_mve_unpredictable): Likewise.
 707         (print_mve_size): Likewise.
 708         (print_insn_mve): Likewise.
 709
 710 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 711             Michael Collison <michael.collison@arm.com>
 712
 713         * arm-dis.c (enum mve_instructions): Add new instructions.
 714         (enum mve_unpredictable): Add new reasons.
 715         (enum mve_undefined): Likewise.
 716         (is_mve_encoding_conflict): Handle new instructions.
 717         (is_mve_undefined): Likewise.
 718         (is_mve_unpredictable): Likewise.
 719         (print_mve_undefined): Likewise.
 720         (print_mve_unpredictable): Likewise.
 721         (print_mve_rounding_mode): Likewise.
 722         (print_mve_vcvt_size): Likewise.
 723         (print_mve_size): Likewise.
 724         (print_insn_mve): Likewise.
 725
 726 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 727             Michael Collison <michael.collison@arm.com>
 728
 729         * arm-dis.c (enum mve_instructions): Add new instructions.
 730         (enum mve_unpredictable): Add new reasons.
 731         (enum mve_undefined): Likewise.
 732         (is_mve_undefined): Handle new instructions.
 733         (is_mve_unpredictable): Likewise.
 734         (print_mve_undefined): Likewise.
 735         (print_mve_unpredictable): Likewise.
 736         (print_mve_size): Likewise.
 737         (print_insn_mve): Likewise.
 738
 739 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 740             Michael Collison <michael.collison@arm.com>
 741
 742         * arm-dis.c (enum mve_instructions): Add new instructions.
 743         (enum mve_undefined): Add new reasons.
 744         (insns): Add new instructions.
 745         (is_mve_encoding_conflict):
 746         (print_mve_vld_str_addr): New print function.
 747         (is_mve_undefined): Handle new instructions.
 748         (is_mve_unpredictable): Likewise.
 749         (print_mve_undefined): Likewise.
 750         (print_mve_size): Likewise.
 751         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 752         (print_insn_mve):  Handle new operands.
 753
 754 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 755             Michael Collison <michael.collison@arm.com>
 756
 757         * arm-dis.c (enum mve_instructions): Add new instructions.
 758         (enum mve_unpredictable): Add new reasons.
 759         (is_mve_encoding_conflict): Handle new instructions.
 760         (is_mve_unpredictable): Likewise.
 761         (mve_opcodes): Add new instructions.
 762         (print_mve_unpredictable): Handle new reasons.
 763         (print_mve_register_blocks): New print function.
 764         (print_mve_size): Handle new instructions.
 765         (print_insn_mve): Likewise.
 766
 767 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 768             Michael Collison <michael.collison@arm.com>
 769
 770         * arm-dis.c (enum mve_instructions): Add new instructions.
 771         (enum mve_unpredictable): Add new reasons.
 772         (enum mve_undefined): Likewise.
 773         (is_mve_encoding_conflict): Handle new instructions.
 774         (is_mve_undefined): Likewise.
 775         (is_mve_unpredictable): Likewise.
 776         (coprocessor_opcodes): Move NEON VDUP from here...
 777         (neon_opcodes): ... to here.
 778         (mve_opcodes): Add new instructions.
 779         (print_mve_undefined):  Handle new reasons.
 780         (print_mve_unpredictable): Likewise.
 781         (print_mve_size): Handle new instructions.
 782         (print_insn_neon): Handle vdup.
 783         (print_insn_mve): Handle new operands.
 784
 785 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 786             Michael Collison <michael.collison@arm.com>
 787
 788         * arm-dis.c (enum mve_instructions): Add new instructions.
 789         (enum mve_unpredictable): Add new values.
 790         (mve_opcodes): Add new instructions.
 791         (vec_condnames): New array with vector conditions.
 792         (mve_predicatenames): New array with predicate suffixes.
 793         (mve_vec_sizename): New array with vector sizes.
 794         (enum vpt_pred_state): New enum with vector predication states.
 795         (struct vpt_block): New struct type for vpt blocks.
 796         (vpt_block_state): Global struct to keep track of state.
 797         (mve_extract_pred_mask): New helper function.
 798         (num_instructions_vpt_block): Likewise.
 799         (mark_outside_vpt_block): Likewise.
 800         (mark_inside_vpt_block): Likewise.
 801         (invert_next_predicate_state): Likewise.
 802         (update_next_predicate_state): Likewise.
 803         (update_vpt_block_state): Likewise.
 804         (is_vpt_instruction): Likewise.
 805         (is_mve_encoding_conflict): Add entries for new instructions.
 806         (is_mve_unpredictable): Likewise.
 807         (print_mve_unpredictable): Handle new cases.
 808         (print_instruction_predicate): Likewise.
 809         (print_mve_size): New function.
 810         (print_vec_condition): New function.
 811         (print_insn_mve): Handle vpt blocks and new print operands.
 812
 813 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 814
 815         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 816         8, 14 and 15 for Armv8.1-M Mainline.
 817
 818 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 819             Michael Collison <michael.collison@arm.com>
 820
 821         * arm-dis.c (enum mve_instructions): New enum.
 822         (enum mve_unpredictable): Likewise.
 823         (enum mve_undefined): Likewise.
 824         (struct mopcode32): New struct.
 825         (is_mve_okay_in_it): New function.
 826         (is_mve_architecture): Likewise.
 827         (arm_decode_field): Likewise.
 828         (arm_decode_field_multiple): Likewise.
 829         (is_mve_encoding_conflict): Likewise.
 830         (is_mve_undefined): Likewise.
 831         (is_mve_unpredictable): Likewise.
 832         (print_mve_undefined): Likewise.
 833         (print_mve_unpredictable): Likewise.
 834         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 835         (print_insn_mve): New function.
 836         (print_insn_thumb32): Handle MVE architecture.
 837         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 838
 839 2019-05-10  Nick Clifton  <nickc@redhat.com>
 840
 841         PR 24538
 842         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 843         end of the table prematurely.
 844
 845 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 846
 847         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 848         macros for R6.
 849
 850 2019-05-11  Alan Modra  <amodra@gmail.com>
 851
 852         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 853         when -Mraw is in effect.
 854
 855 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 856
 857         * aarch64-dis-2.c: Regenerate.
 858         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 859         (OP_SVE_BBB): New variant set.
 860         (OP_SVE_DDDD): New variant set.
 861         (OP_SVE_HHH): New variant set.
 862         (OP_SVE_HHHU): New variant set.
 863         (OP_SVE_SSS): New variant set.
 864         (OP_SVE_SSSU): New variant set.
 865         (OP_SVE_SHH): New variant set.
 866         (OP_SVE_SBBU): New variant set.
 867         (OP_SVE_DSS): New variant set.
 868         (OP_SVE_DHHU): New variant set.
 869         (OP_SVE_VMV_HSD_BHS): New variant set.
 870         (OP_SVE_VVU_HSD_BHS): New variant set.
 871         (OP_SVE_VVVU_SD_BH): New variant set.
 872         (OP_SVE_VVVU_BHSD): New variant set.
 873         (OP_SVE_VVV_QHD_DBS): New variant set.
 874         (OP_SVE_VVV_HSD_BHS): New variant set.
 875         (OP_SVE_VVV_HSD_BHS2): New variant set.
 876         (OP_SVE_VVV_BHS_HSD): New variant set.
 877         (OP_SVE_VV_BHS_HSD): New variant set.
 878         (OP_SVE_VVV_SD): New variant set.
 879         (OP_SVE_VVU_BHS_HSD): New variant set.
 880         (OP_SVE_VZVV_SD): New variant set.
 881         (OP_SVE_VZVV_BH): New variant set.
 882         (OP_SVE_VZV_SD): New variant set.
 883         (aarch64_opcode_table): Add sve2 instructions.
 884
 885 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 886
 887         * aarch64-asm-2.c: Regenerated.
 888         * aarch64-dis-2.c: Regenerated.
 889         * aarch64-opc-2.c: Regenerated.
 890         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 891         for SVE_SHLIMM_UNPRED_22.
 892         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 893         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 894         operand.
 895
 896 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 897
 898         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 899         sve_size_tsz_bhs iclass encode.
 900         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 901         sve_size_tsz_bhs iclass decode.
 902
 903 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 904
 905         * aarch64-asm-2.c: Regenerated.
 906         * aarch64-dis-2.c: Regenerated.
 907         * aarch64-opc-2.c: Regenerated.
 908         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 909         for SVE_Zm4_11_INDEX.
 910         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 911         (fields): Handle SVE_i2h field.
 912         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 913         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 914
 915 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 916
 917         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 918         sve_shift_tsz_bhsd iclass encode.
 919         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 920         sve_shift_tsz_bhsd iclass decode.
 921
 922 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 923
 924         * aarch64-asm-2.c: Regenerated.
 925         * aarch64-dis-2.c: Regenerated.
 926         * aarch64-opc-2.c: Regenerated.
 927         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 928         (aarch64_encode_variant_using_iclass): Handle
 929         sve_shift_tsz_hsd iclass encode.
 930         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 931         sve_shift_tsz_hsd iclass decode.
 932         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 933         for SVE_SHRIMM_UNPRED_22.
 934         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 935         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 936         operand.
 937
 938 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 939
 940         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 941         sve_size_013 iclass encode.
 942         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 943         sve_size_013 iclass decode.
 944
 945 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 946
 947         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 948         sve_size_bh iclass encode.
 949         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 950         sve_size_bh iclass decode.
 951
 952 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 953
 954         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 955         sve_size_sd2 iclass encode.
 956         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 957         sve_size_sd2 iclass decode.
 958         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 959         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 960
 961 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 962
 963         * aarch64-asm-2.c: Regenerated.
 964         * aarch64-dis-2.c: Regenerated.
 965         * aarch64-opc-2.c: Regenerated.
 966         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 967         for SVE_ADDR_ZX.
 968         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 969         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 970
 971 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 972
 973         * aarch64-asm-2.c: Regenerated.
 974         * aarch64-dis-2.c: Regenerated.
 975         * aarch64-opc-2.c: Regenerated.
 976         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 977         for SVE_Zm3_11_INDEX.
 978         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 979         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 980         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 981         fields.
 982         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 983
 984 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 985
 986         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 987         sve_size_hsd2 iclass encode.
 988         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 989         sve_size_hsd2 iclass decode.
 990         * aarch64-opc.c (fields): Handle SVE_size field.
 991         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 992
 993 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 994
 995         * aarch64-asm-2.c: Regenerated.
 996         * aarch64-dis-2.c: Regenerated.
 997         * aarch64-opc-2.c: Regenerated.
 998         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 999         for SVE_IMM_ROT3.
1000         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1001         (fields): Handle SVE_rot3 field.
1002         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1003         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1004
1005 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1006
1007         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1008         instructions.
1009
1010 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1011
1012         * aarch64-tbl.h
1013         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1014         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1015         aarch64_feature_sve2bitperm): New feature sets.
1016         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1017         for feature set addresses.
1018         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1019         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1020
1021 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1022             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1023
1024         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1025         argument and set ASE_EVA_R6 appropriately.
1026         (set_default_mips_dis_options): Pass ISA to above.
1027         (parse_mips_dis_option): Likewise.
1028         * mips-opc.c (EVAR6): New macro.
1029         (mips_builtin_opcodes): Add llwpe, scwpe.
1030
1031 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1032
1033         * aarch64-asm-2.c: Regenerated.
1034         * aarch64-dis-2.c: Regenerated.
1035         * aarch64-opc-2.c: Regenerated.
1036         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1037         AARCH64_OPND_TME_UIMM16.
1038         (aarch64_print_operand): Likewise.
1039         * aarch64-tbl.h (QL_IMM_NIL): New.
1040         (TME): New.
1041         (_TME_INSN): New.
1042         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1043
1044 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1045
1046         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1047
1048 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1049             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1050
1051         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1052
1053 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1054
1055         * s12z-opc.h: Add extern "C" bracketing to help
1056         users who wish to use this interface in c++ code.
1057
1058 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1059
1060         * s12z-opc.c (bm_decode): Handle bit map operations with the
1061         "reserved0" mode.
1062
1063 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1064
1065         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1066         specifier.  Add entries for VLDR and VSTR of system registers.
1067         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1068         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1069         of %J and %K format specifier.
1070
1071 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1072
1073         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1074         Add new entries for VSCCLRM instruction.
1075         (print_insn_coprocessor): Handle new %C format control code.
1076
1077 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1078
1079         * arm-dis.c (enum isa): New enum.
1080         (struct sopcode32): New structure.
1081         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1082         set isa field of all current entries to ANY.
1083         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1084         Only match an entry if its isa field allows the current mode.
1085
1086 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1087
1088         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1089         CLRM.
1090         (print_insn_thumb32): Add logic to print %n CLRM register list.
1091
1092 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1093
1094         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1095         and %Q patterns.
1096
1097 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1098
1099         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1100         (print_insn_thumb32): Edit the switch case for %Z.
1101
1102 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1103
1104         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1105
1106 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1107
1108         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1109
1110 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1111
1112         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1113
1114 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1115
1116         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1117         Arm register with r13 and r15 unpredictable.
1118         (thumb32_opcodes): New instructions for bfx and bflx.
1119
1120 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1121
1122         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1123
1124 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1125
1126         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1127
1128 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1129
1130         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1131
1132 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1133
1134         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1135
1136 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1137
1138         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1139         "optr". ("operator" is a reserved word in c++).
1140
1141 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1142
1143         * aarch64-opc.c (aarch64_print_operand): Add case for
1144         AARCH64_OPND_Rt_SP.
1145         (verify_constraints): Likewise.
1146         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1147         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1148         to accept Rt|SP as first operand.
1149         (AARCH64_OPERANDS): Add new Rt_SP.
1150         * aarch64-asm-2.c: Regenerated.
1151         * aarch64-dis-2.c: Regenerated.
1152         * aarch64-opc-2.c: Regenerated.
1153
1154 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1155
1156         * aarch64-asm-2.c: Regenerated.
1157         * aarch64-dis-2.c: Likewise.
1158         * aarch64-opc-2.c: Likewise.
1159         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1160
1161 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1162
1163         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1164
1165 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1166
1167         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1168         * i386-init.h: Regenerated.
1169
1170 2019-04-07  Alan Modra  <amodra@gmail.com>
1171
1172         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1173         op_separator to control printing of spaces, comma and parens
1174         rather than need_comma, need_paren and spaces vars.
1175
1176 2019-04-07  Alan Modra  <amodra@gmail.com>
1177
1178         PR 24421
1179         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1180         (print_insn_neon, print_insn_arm): Likewise.
1181
1182 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1183
1184         * i386-dis-evex.h (evex_table): Updated to support BF16
1185         instructions.
1186         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1187         and EVEX_W_0F3872_P_3.
1188         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1189         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1190         * i386-opc.h (enum): Add CpuAVX512_BF16.
1191         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1192         * i386-opc.tbl: Add AVX512 BF16 instructions.
1193         * i386-init.h: Regenerated.
1194         * i386-tbl.h: Likewise.
1195
1196 2019-04-05  Alan Modra  <amodra@gmail.com>
1197
1198         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1199         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1200         to favour printing of "-" branch hint when using the "y" bit.
1201         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1202
1203 2019-04-05  Alan Modra  <amodra@gmail.com>
1204
1205         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1206         opcode until first operand is output.
1207
1208 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1209
1210         PR gas/24349
1211         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1212         (valid_bo_post_v2): Add support for 'at' branch hints.
1213         (insert_bo): Only error on branch on ctr.
1214         (get_bo_hint_mask): New function.
1215         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1216         for inserting 'at' branch hints.
1217         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1218         for extracting 'at' branch hints.
1219         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1220         (BOE): Delete operand.
1221         (BOM, BOP): New operands.
1222         (RM): Update value.
1223         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1224         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1225         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1226         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1227         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1228         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1229         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1230         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1231         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1232         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1233         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1234         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1235         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1236         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1237         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1238         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1239         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1240         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1241         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1242         bttarl+>: New extended mnemonics.
1243
1244 2019-03-28  Alan Modra  <amodra@gmail.com>
1245
1246         PR 24390
1247         * ppc-opc.c (BTF): Define.
1248         (powerpc_opcodes): Use for mtfsb*.
1249         * ppc-dis.c (print_insn_powerpc): Print fields with both
1250         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1251
1252 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1253
1254         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1255         (mapping_symbol_for_insn): Implement new algorithm.
1256         (print_insn): Remove duplicate code.
1257
1258 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1259
1260         * aarch64-dis.c (print_insn_aarch64):
1261         Implement override.
1262
1263 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1264
1265         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1266         order.
1267
1268 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1269
1270         * aarch64-dis.c (last_stop_offset): New.
1271         (print_insn_aarch64): Use stop_offset.
1272
1273 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1274
1275         PR gas/24359
1276         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1277         CPU_ANY_AVX2_FLAGS.
1278         * i386-init.h: Regenerated.
1279
1280 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1281
1282         PR gas/24348
1283         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1284         vmovdqu16, vmovdqu32 and vmovdqu64.
1285         * i386-tbl.h: Regenerated.
1286
1287 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1288
1289         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1290         from vstrszb, vstrszh, and vstrszf.
1291
1292 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1293
1294         * s390-opc.txt: Add instruction descriptions.
1295
1296 2019-02-08  Jim Wilson  <jimw@sifive.com>
1297
1298         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1299         <bne>: Likewise.
1300
1301 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1302
1303         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1304
1305 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1306
1307         PR binutils/23212
1308         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1309         * aarch64-opc.c (verify_elem_sd): New.
1310         (fields): Add FLD_sz entr.
1311         * aarch64-tbl.h (_SIMD_INSN): New.
1312         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1313         fmulx scalar and vector by element isns.
1314
1315 2019-02-07  Nick Clifton  <nickc@redhat.com>
1316
1317         * po/sv.po: Updated Swedish translation.
1318
1319 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1320
1321         * s390-mkopc.c (main): Accept arch13 as cpu string.
1322         * s390-opc.c: Add new instruction formats and instruction opcode
1323         masks.
1324         * s390-opc.txt: Add new arch13 instructions.
1325
1326 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1327
1328         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1329         (aarch64_opcode): Change encoding for stg, stzg
1330         st2g and st2zg.
1331         * aarch64-asm-2.c: Regenerated.
1332         * aarch64-dis-2.c: Regenerated.
1333         * aarch64-opc-2.c: Regenerated.
1334
1335 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1336
1337         * aarch64-asm-2.c: Regenerated.
1338         * aarch64-dis-2.c: Likewise.
1339         * aarch64-opc-2.c: Likewise.
1340         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1341
1342 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1343             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1344
1345         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1346         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1347         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1348         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1349         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1350         case for ldstgv_indexed.
1351         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1352         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1353         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1354         * aarch64-asm-2.c: Regenerated.
1355         * aarch64-dis-2.c: Regenerated.
1356         * aarch64-opc-2.c: Regenerated.
1357
1358 2019-01-23  Nick Clifton  <nickc@redhat.com>
1359
1360         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1361
1362 2019-01-21  Nick Clifton  <nickc@redhat.com>
1363
1364         * po/de.po: Updated German translation.
1365         * po/uk.po: Updated Ukranian translation.
1366
1367 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1368         * mips-dis.c (mips_arch_choices): Fix typo in
1369         gs464, gs464e and gs264e descriptors.
1370
1371 2019-01-19  Nick Clifton  <nickc@redhat.com>
1372
1373         * configure: Regenerate.
1374         * po/opcodes.pot: Regenerate.
1375
1376 2018-06-24  Nick Clifton  <nickc@redhat.com>
1377
1378         2.32 branch created.
1379
1380 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1381
1382         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1383         if it is null.
1384         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1385         zero.
1386
1387 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1388
1389         * configure: Regenerate.
1390
1391 2019-01-07  Alan Modra  <amodra@gmail.com>
1392
1393         * configure: Regenerate.
1394         * po/POTFILES.in: Regenerate.
1395
1396 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1397
1398         * s12z-opc.c: New file.
1399         * s12z-opc.h: New file.
1400         * s12z-dis.c: Removed all code not directly related to display
1401         of instructions.  Used the interface provided by the new files
1402         instead.
1403         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1404         * Makefile.in: Regenerate.
1405         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1406         * configure: Regenerate.
1407
1408 2019-01-01  Alan Modra  <amodra@gmail.com>
1409
1410         Update year range in copyright notice of all files.
1411
1412 For older changes see ChangeLog-2018
1413 \f
1414 Copyright (C) 2019 Free Software Foundation, Inc.
1415
1416 Copying and distribution of this file, with or without modification,
1417 are permitted in any medium without royalty provided the copyright
1418 notice and this notice are preserved.
1419
1420 Local Variables:
1421 mode: change-log
1422 left-margin: 8
1423 fill-column: 74
1424 version-control: never
1425 End: