opcodes/ChangeLog

   1 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
   2
   3         * arc-dis.c (enforced_isa_mask): Declare.
   4         (cpu_types): Likewise.
   5         (parse_cpu_option): New function.
   6         (parse_disassembler_options): Use it.
   7         (print_insn_arc): Use enforced_isa_mask.
   8         (print_arc_disassembler_options): Document new options.
   9
  10 2017-05-24  Yao Qi  <yao.qi@linaro.org>
  11
  12         * alpha-dis.c: Include disassemble.h, don't include
  13         dis-asm.h.
  14         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
  15         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
  16         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
  17         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
  18         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
  19         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
  20         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
  21         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
  22         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
  23         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
  24         * moxie-dis.c, msp430-dis.c, mt-dis.c:
  25         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
  26         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
  27         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
  28         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
  29         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
  30         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
  31         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
  32         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
  33         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
  34         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
  35         * z80-dis.c, z8k-dis.c: Likewise.
  36         * disassemble.h: New file.
  37
  38 2017-05-24  Yao Qi  <yao.qi@linaro.org>
  39
  40         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
  41         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
  42
  43 2017-05-24  Yao Qi  <yao.qi@linaro.org>
  44
  45         * disassemble.c (disassembler): Add arguments a, big and mach.
  46         Use them.
  47
  48 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
  49
  50         * i386-dis.c (NOTRACK_Fixup): New.
  51         (NOTRACK): Likewise.
  52         (NOTRACK_PREFIX): Likewise.
  53         (last_active_prefix): Likewise.
  54         (reg_table): Use NOTRACK on indirect call and jmp.
  55         (ckprefix): Set last_active_prefix.
  56         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
  57         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
  58         * i386-opc.h (NoTrackPrefixOk): New.
  59         (i386_opcode_modifier): Add notrackprefixok.
  60         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
  61         Add notrack.
  62         * i386-tbl.h: Regenerated.
  63
  64 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
  65
  66         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
  67         (X_IMM2): Define.
  68         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
  69         bfd_mach_sparc_v9m8.
  70         (print_insn_sparc): Handle new operand types.
  71         * sparc-opc.c (MASK_M8): Define.
  72         (v6): Add MASK_M8.
  73         (v6notlet): Likewise.
  74         (v7): Likewise.
  75         (v8): Likewise.
  76         (v9): Likewise.
  77         (v9a): Likewise.
  78         (v9b): Likewise.
  79         (v9c): Likewise.
  80         (v9d): Likewise.
  81         (v9e): Likewise.
  82         (v9v): Likewise.
  83         (v9m): Likewise.
  84         (v9andleon): Likewise.
  85         (m8): Define.
  86         (HWS_VM8): Define.
  87         (HWS2_VM8): Likewise.
  88         (sparc_opcode_archs): Add entry for "m8".
  89         (sparc_opcodes): Add OSA2017 and M8 instructions
  90         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
  91         fpx{ll,ra,rl}64x,
  92         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
  93         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
  94         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
  95         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
  96         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
  97         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
  98         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
  99         ASI_CORE_SELECT_COMMIT_NHT.
 100
 101 2017-05-18  Alan Modra  <amodra@gmail.com>
 102
 103         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 104         * aarch64-dis.c: Likewise.
 105         * aarch64-gen.c: Likewise.
 106         * aarch64-opc.c: Likewise.
 107
 108 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 109             Matthew Fortune  <matthew.fortune@imgtec.com>
 110
 111         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 112         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 113         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 114         (print_insn_arg) <OP_REG28>: Add handler.
 115         (validate_insn_args) <OP_REG28>: Handle.
 116         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 117         32-bit encoding and 9-bit immediates.
 118         (print_insn_mips16): Handle MIPS16 instructions that require
 119         32-bit encoding and MFC0/MTC0 operand decoding.
 120         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 121         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 122         (RD_C0, WR_C0, E2, E2MT): New macros.
 123         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 124         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 125         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 126         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 127         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 128         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 129         instructions, "swl", "swr", "sync" and its "sync_acquire",
 130         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 131         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 132         regular/extended entries for original MIPS16 ISA revision
 133         instructions whose extended forms are subdecoded in the MIPS16e2
 134         ISA revision: "li", "sll" and "srl".
 135
 136 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 137
 138         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 139         reference in CP0 move operand decoding.
 140
 141 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 142
 143         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 144         type to hexadecimal.
 145         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 146
 147 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 148
 149         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 150         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 151         "sync_rmb" and "sync_wmb" as aliases.
 152         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 153         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 154
 155 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 156
 157         * arc-dis.c (parse_option): Update quarkse_em option..
 158         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 159         QUARKSE1.
 160         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 161
 162 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 163
 164         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 165
 166 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 167
 168         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 169         register.
 170
 171 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 172
 173         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 174         and branches and not synthetic data instructions.
 175
 176 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 177
 178         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 179
 180 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 181
 182         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 183         * arc-opc.c (insert_r13el): New function.
 184         (R13_EL): Define.
 185         * arc-tbl.h: Add new enter/leave variants.
 186
 187 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 188
 189         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 190
 191 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 192
 193         * mips-dis.c (print_mips_disassembler_options): Add
 194         `no-aliases'.
 195
 196 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 197
 198         * mips16-opc.c (AL): New macro.
 199         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 200         of "ld" and "lw" as aliases.
 201
 202 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 203
 204         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 205         arguments.
 206
 207 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 208             Alan Modra  <amodra@gmail.com>
 209
 210         * ppc-opc.c (ELEV): Define.
 211         (vle_opcodes): Add se_rfgi and e_sc.
 212         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 213         for E200Z4.
 214
 215 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 216
 217         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 218
 219 2017-04-21  Nick Clifton  <nickc@redhat.com>
 220
 221         PR binutils/21380
 222         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 223         LD3R and LD4R.
 224
 225 2017-04-13  Alan Modra  <amodra@gmail.com>
 226
 227         * epiphany-desc.c: Regenerate.
 228         * fr30-desc.c: Regenerate.
 229         * frv-desc.c: Regenerate.
 230         * ip2k-desc.c: Regenerate.
 231         * iq2000-desc.c: Regenerate.
 232         * lm32-desc.c: Regenerate.
 233         * m32c-desc.c: Regenerate.
 234         * m32r-desc.c: Regenerate.
 235         * mep-desc.c: Regenerate.
 236         * mt-desc.c: Regenerate.
 237         * or1k-desc.c: Regenerate.
 238         * xc16x-desc.c: Regenerate.
 239         * xstormy16-desc.c: Regenerate.
 240
 241 2017-04-11  Alan Modra  <amodra@gmail.com>
 242
 243         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 244         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 245         PPC_OPCODE_TMR for e6500.
 246         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 247         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 248         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 249         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 250         (PPCHTM): Define as PPC_OPCODE_POWER8.
 251         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 252
 253 2017-04-10  Alan Modra  <amodra@gmail.com>
 254
 255         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 256         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 257         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 258         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 259
 260 2017-04-09  Pip Cet  <pipcet@gmail.com>
 261
 262         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 263         appropriate floating-point precision directly.
 264
 265 2017-04-07  Alan Modra  <amodra@gmail.com>
 266
 267         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 268         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 269         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 270         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 271         vector instructions with E6500 not PPCVEC2.
 272
 273 2017-04-06  Pip Cet  <pipcet@gmail.com>
 274
 275         * Makefile.am: Add wasm32-dis.c.
 276         * configure.ac: Add wasm32-dis.c to wasm32 target.
 277         * disassemble.c: Add wasm32 disassembler code.
 278         * wasm32-dis.c: New file.
 279         * Makefile.in: Regenerate.
 280         * configure: Regenerate.
 281         * po/POTFILES.in: Regenerate.
 282         * po/opcodes.pot: Regenerate.
 283
 284 2017-04-05  Pedro Alves  <palves@redhat.com>
 285
 286         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 287         * arm-dis.c (parse_arm_disassembler_options): Constify.
 288         * ppc-dis.c (powerpc_init_dialect): Constify local.
 289         * vax-dis.c (parse_disassembler_options): Constify.
 290
 291 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 292
 293         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 294         RISCV_GP_SYMBOL.
 295
 296 2017-03-30  Pip Cet  <pipcet@gmail.com>
 297
 298         * configure.ac: Add (empty) bfd_wasm32_arch target.
 299         * configure: Regenerate
 300         * po/opcodes.pot: Regenerate.
 301
 302 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 303
 304         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 305         OSA2015.
 306         * opcodes/sparc-opc.c (asi_table): New ASIs.
 307
 308 2017-03-29  Alan Modra  <amodra@gmail.com>
 309
 310         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 311         "raw" option.
 312         (lookup_powerpc): Don't special case -1 dialect.  Handle
 313         PPC_OPCODE_RAW.
 314         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 315         lookup_powerpc call, pass it on second.
 316
 317 2017-03-27  Alan Modra  <amodra@gmail.com>
 318
 319         PR 21303
 320         * ppc-dis.c (struct ppc_mopt): Comment.
 321         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 322
 323 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 324
 325         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 326         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 327         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 328         (insert_nps_misc_imm_offset): New function.
 329         (extract_nps_misc imm_offset): New function.
 330         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 331         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 332
 333 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 334
 335         * s390-mkopc.c (main): Remove vx2 check.
 336         * s390-opc.txt: Remove vx2 instruction flags.
 337
 338 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 339
 340         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 341         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 342         (insert_nps_imm_offset): New function.
 343         (extract_nps_imm_offset): New function.
 344         (insert_nps_imm_entry): New function.
 345         (extract_nps_imm_entry): New function.
 346
 347 2017-03-17  Alan Modra  <amodra@gmail.com>
 348
 349         PR 21248
 350         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 351         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 352         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 353
 354 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 355
 356         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 357         <c.andi>: Likewise.
 358         <c.addiw> Likewise.
 359
 360 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 361
 362         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 363
 364 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 365
 366         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 367         <srl> Likewise.
 368         <srai> Likewise.
 369         <sra> Likewise.
 370
 371 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 372
 373         * i386-gen.c (opcode_modifiers): Replace S with Load.
 374         * i386-opc.h (S): Removed.
 375         (Load): New.
 376         (i386_opcode_modifier): Replace s with load.
 377         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 378         and {evex}.  Replace S with Load.
 379         * i386-tbl.h: Regenerated.
 380
 381 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 382
 383         * i386-opc.tbl: Use CpuCET on rdsspq.
 384         * i386-tbl.h: Regenerated.
 385
 386 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 387
 388         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 389         <vsx>: Do not use PPC_OPCODE_VSX3;
 390
 391 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 392
 393         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 394
 395 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 396
 397         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 398         (MOD_0F1E_PREFIX_1): Likewise.
 399         (MOD_0F38F5_PREFIX_2): Likewise.
 400         (MOD_0F38F6_PREFIX_0): Likewise.
 401         (RM_0F1E_MOD_3_REG_7): Likewise.
 402         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 403         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 404         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 405         (PREFIX_0F1E): Likewise.
 406         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 407         (PREFIX_0F38F5): Likewise.
 408         (dis386_twobyte): Use PREFIX_0F1E.
 409         (reg_table): Add REG_0F1E_MOD_3.
 410         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 411         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 412         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 413         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 414         (three_byte_table): Use PREFIX_0F38F5.
 415         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 416         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 417         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 418         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 419         PREFIX_MOD_3_0F01_REG_5_RM_2.
 420         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 421         (cpu_flags): Add CpuCET.
 422         * i386-opc.h (CpuCET): New enum.
 423         (CpuUnused): Commented out.
 424         (i386_cpu_flags): Add cpucet.
 425         * i386-opc.tbl: Add Intel CET instructions.
 426         * i386-init.h: Regenerated.
 427         * i386-tbl.h: Likewise.
 428
 429 2017-03-06  Alan Modra  <amodra@gmail.com>
 430
 431         PR 21124
 432         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 433         (extract_raq, extract_ras, extract_rbx): New functions.
 434         (powerpc_operands): Use opposite corresponding insert function.
 435         (Q_MASK): Define.
 436         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 437         register restriction.
 438
 439 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 440
 441         * disassemble.c Include "safe-ctype.h".
 442         (disassemble_init_for_target): Handle s390 init.
 443         (remove_whitespace_and_extra_commas): New function.
 444         (disassembler_options_cmp): Likewise.
 445         * arm-dis.c: Include "libiberty.h".
 446         (NUM_ELEM): Delete.
 447         (regnames): Use long disassembler style names.
 448         Add force-thumb and no-force-thumb options.
 449         (NUM_ARM_REGNAMES): Rename from this...
 450         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 451         (get_arm_regname_num_options): Delete.
 452         (set_arm_regname_option): Likewise.
 453         (get_arm_regnames): Likewise.
 454         (parse_disassembler_options): Likewise.
 455         (parse_arm_disassembler_option): Rename from this...
 456         (parse_arm_disassembler_options): ...to this.  Make static.
 457         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 458         (print_insn): Use parse_arm_disassembler_options.
 459         (disassembler_options_arm): New function.
 460         (print_arm_disassembler_options): Handle updated regnames.
 461         * ppc-dis.c: Include "libiberty.h".
 462         (ppc_opts): Add "32" and "64" entries.
 463         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 464         (powerpc_init_dialect): Add break to switch statement.
 465         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 466         (disassembler_options_powerpc): New function.
 467         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 468         Remove printing of "32" and "64".
 469         * s390-dis.c: Include "libiberty.h".
 470         (init_flag): Remove unneeded variable.
 471         (struct s390_options_t): New structure type.
 472         (options): New structure.
 473         (init_disasm): Rename from this...
 474         (disassemble_init_s390): ...to this.  Add initializations for
 475         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 476         (print_insn_s390): Delete call to init_disasm.
 477         (disassembler_options_s390): New function.
 478         (print_s390_disassembler_options): Print using information from
 479         struct 'options'.
 480         * po/opcodes.pot: Regenerate.
 481
 482 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 483
 484         * i386-dis.c (PCMPESTR_Fixup): New.
 485         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 486         (prefix_table): Use PCMPESTR_Fixup.
 487         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 488         PCMPESTR_Fixup.
 489         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 490         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 491         Split 64-bit and non-64-bit variants.
 492         * opcodes/i386-tbl.h: Re-generate.
 493
 494 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 495
 496         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 497         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 498         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 499         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 500         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 501         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 502         (OP_SVE_V_HSD): New macros.
 503         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 504         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 505         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 506         (aarch64_opcode_table): Add new SVE instructions.
 507         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 508         for rotation operands.  Add new SVE operands.
 509         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 510         (ins_sve_quad_index): Likewise.
 511         (ins_imm_rotate): Split into...
 512         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 513         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 514         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 515         functions.
 516         (aarch64_ins_sve_addr_ri_s4): New function.
 517         (aarch64_ins_sve_quad_index): Likewise.
 518         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 519         * aarch64-asm-2.c: Regenerate.
 520         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 521         (ext_sve_quad_index): Likewise.
 522         (ext_imm_rotate): Split into...
 523         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 524         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 525         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 526         functions.
 527         (aarch64_ext_sve_addr_ri_s4): New function.
 528         (aarch64_ext_sve_quad_index): Likewise.
 529         (aarch64_ext_sve_index): Allow quad indices.
 530         (do_misc_decoding): Likewise.
 531         * aarch64-dis-2.c: Regenerate.
 532         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 533         aarch64_field_kinds.
 534         (OPD_F_OD_MASK): Widen by one bit.
 535         (OPD_F_NO_ZR): Bump accordingly.
 536         (get_operand_field_width): New function.
 537         * aarch64-opc.c (fields): Add new SVE fields.
 538         (operand_general_constraint_met_p): Handle new SVE operands.
 539         (aarch64_print_operand): Likewise.
 540         * aarch64-opc-2.c: Regenerate.
 541
 542 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 543
 544         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 545         (aarch64_feature_compnum): ...this.
 546         (SIMD_V8_3): Replace with...
 547         (COMPNUM): ...this.
 548         (CNUM_INSN): New macro.
 549         (aarch64_opcode_table): Use it for the complex number instructions.
 550
 551 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 552
 553         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 554
 555 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 556
 557         Add support for associating SPARC ASIs with an architecture level.
 558         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 559         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 560         decoding of SPARC ASIs.
 561
 562 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 563
 564         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 565         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 566
 567 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 568
 569         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 570         1 (instead of to itself). Correct typo.
 571
 572 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 573
 574         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 575         pseudoinstructions.
 576
 577 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 578
 579         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 580         (aarch64_sys_reg_supported_p): Handle them.
 581
 582 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 583
 584         * arc-opc.c (UIMM6_20R): Define.
 585         (SIMM12_20): Use above.
 586         (SIMM12_20R): Define.
 587         (SIMM3_5_S): Use above.
 588         (UIMM7_A32_11R_S): Define.
 589         (UIMM7_9_S): Use above.
 590         (UIMM3_13R_S): Define.
 591         (SIMM11_A32_7_S): Use above.
 592         (SIMM9_8R): Define.
 593         (UIMM10_A32_8_S): Use above.
 594         (UIMM8_8R_S): Define.
 595         (W6): Use above.
 596         (arc_relax_opcodes): Use all above defines.
 597
 598 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 599
 600         * arc-regs.h: Distinguish some of the registers different on
 601         ARC700 and HS38 cpus.
 602
 603 2017-02-14  Alan Modra  <amodra@gmail.com>
 604
 605         PR 21118
 606         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 607         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 608
 609 2017-02-11  Stafford Horne  <shorne@gmail.com>
 610             Alan Modra  <amodra@gmail.com>
 611
 612         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 613         Use insn_bytes_value and insn_int_value directly instead.  Don't
 614         free allocated memory until function exit.
 615
 616 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 617
 618         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 619
 620 2017-02-03  Nick Clifton  <nickc@redhat.com>
 621
 622         PR 21096
 623         * aarch64-opc.c (print_register_list): Ensure that the register
 624         list index will fir into the tb buffer.
 625         (print_register_offset_address): Likewise.
 626         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 627
 628 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 629
 630         PR 21056
 631         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 632         instructions when the previous fetch packet ends with a 32-bit
 633         instruction.
 634
 635 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 636
 637         * pru-opc.c: Remove vague reference to a future GDB port.
 638
 639 2017-01-20  Nick Clifton  <nickc@redhat.com>
 640
 641         * po/ga.po: Updated Irish translation.
 642
 643 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 644
 645         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 646
 647 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 648
 649         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 650         if FETCH_DATA returns 0.
 651         (m68k_scan_mask): Likewise.
 652         (print_insn_m68k): Update code to handle -1 return value.
 653
 654 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 655
 656         * m68k-dis.c (enum print_insn_arg_error): New.
 657         (NEXTBYTE): Replace -3 with
 658         PRINT_INSN_ARG_MEMORY_ERROR.
 659         (NEXTULONG): Likewise.
 660         (NEXTSINGLE): Likewise.
 661         (NEXTDOUBLE): Likewise.
 662         (NEXTDOUBLE): Likewise.
 663         (NEXTPACKED): Likewise.
 664         (FETCH_ARG): Likewise.
 665         (FETCH_DATA): Update comments.
 666         (print_insn_arg): Update comments. Replace magic numbers with
 667         enum.
 668         (match_insn_m68k): Likewise.
 669
 670 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 671
 672         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 673         * i386-dis-evex.h (evex_table): Updated.
 674         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 675         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 676         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 677         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 678         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 679         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 680         * i386-init.h: Regenerate.
 681         * i386-tbl.h: Ditto.
 682
 683 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 684
 685         * msp430-dis.c (msp430_singleoperand): Return -1 if
 686         msp430dis_opcode_signed returns false.
 687         (msp430_doubleoperand): Likewise.
 688         (msp430_branchinstr): Return -1 if
 689         msp430dis_opcode_unsigned returns false.
 690         (msp430x_calla_instr): Likewise.
 691         (print_insn_msp430): Likewise.
 692
 693 2017-01-05  Nick Clifton  <nickc@redhat.com>
 694
 695         PR 20946
 696         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 697         could not be matched.
 698         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 699         NULL.
 700
 701 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 702
 703         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 704         (aarch64_opcode_table): Use RCPC_INSN.
 705
 706 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 707
 708         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 709         extension.
 710         * riscv-opcodes/all-opcodes: Likewise.
 711
 712 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 713
 714         * riscv-dis.c (print_insn_args): Add fall through comment.
 715
 716 2017-01-03  Nick Clifton  <nickc@redhat.com>
 717
 718         * po/sr.po: New Serbian translation.
 719         * configure.ac (ALL_LINGUAS): Add sr.
 720         * configure: Regenerate.
 721
 722 2017-01-02  Alan Modra  <amodra@gmail.com>
 723
 724         * epiphany-desc.h: Regenerate.
 725         * epiphany-opc.h: Regenerate.
 726         * fr30-desc.h: Regenerate.
 727         * fr30-opc.h: Regenerate.
 728         * frv-desc.h: Regenerate.
 729         * frv-opc.h: Regenerate.
 730         * ip2k-desc.h: Regenerate.
 731         * ip2k-opc.h: Regenerate.
 732         * iq2000-desc.h: Regenerate.
 733         * iq2000-opc.h: Regenerate.
 734         * lm32-desc.h: Regenerate.
 735         * lm32-opc.h: Regenerate.
 736         * m32c-desc.h: Regenerate.
 737         * m32c-opc.h: Regenerate.
 738         * m32r-desc.h: Regenerate.
 739         * m32r-opc.h: Regenerate.
 740         * mep-desc.h: Regenerate.
 741         * mep-opc.h: Regenerate.
 742         * mt-desc.h: Regenerate.
 743         * mt-opc.h: Regenerate.
 744         * or1k-desc.h: Regenerate.
 745         * or1k-opc.h: Regenerate.
 746         * xc16x-desc.h: Regenerate.
 747         * xc16x-opc.h: Regenerate.
 748         * xstormy16-desc.h: Regenerate.
 749         * xstormy16-opc.h: Regenerate.
 750
 751 2017-01-02  Alan Modra  <amodra@gmail.com>
 752
 753         Update year range in copyright notice of all files.
 754
 755 For older changes see ChangeLog-2016
 756 \f
 757 Copyright (C) 2017 Free Software Foundation, Inc.
 758
 759 Copying and distribution of this file, with or without modification,
 760 are permitted in any medium without royalty provided the copyright
 761 notice and this notice are preserved.
 762
 763 Local Variables:
 764 mode: change-log
 765 left-margin: 8
 766 fill-column: 74
 767 version-control: never
 768 End: