opcodes/ChangeLog

   1 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
   2
   3         * arc-regs.h: Update auxiliary registers.
   4
   5 2018-08-06  Jan Beulich  <jbeulich@suse.com>
   6
   7         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
   8         (RegIP, RegIZ): Define.
   9         * i386-reg.tbl: Adjust comments.
  10         (rip): Use Qword instead of BaseIndex. Use RegIP.
  11         (eip): Use Dword instead of BaseIndex. Use RegIP.
  12         (riz): Add Qword. Use RegIZ.
  13         (eiz): Add Dword. Use RegIZ.
  14         * i386-tbl.h: Re-generate.
  15
  16 2018-08-03  Jan Beulich  <jbeulich@suse.com>
  17
  18         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
  19         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
  20         vpmovzxdq, vpmovzxwd): Remove NoRex64.
  21         * i386-tbl.h: Re-generate.
  22
  23 2018-08-03  Jan Beulich  <jbeulich@suse.com>
  24
  25         * i386-gen.c (operand_types): Remove Mem field.
  26         * i386-opc.h (union i386_operand_type): Remove mem field.
  27         * i386-init.h, i386-tbl.h: Re-generate.
  28
  29 2018-08-01  Alan Modra  <amodra@gmail.com>
  30
  31         * po/POTFILES.in: Regenerate.
  32
  33 2018-07-31  Nick Clifton  <nickc@redhat.com>
  34
  35         * po/sv.po: Updated Swedish translation.
  36
  37 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  38
  39         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
  40         * i386-init.h, i386-tbl.h: Re-generate.
  41
  42 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  43
  44         * i386-opc.h (ZEROING_MASKING) Rename to ...
  45         (DYNAMIC_MASKING): ... this. Adjust comment.
  46         * i386-opc.tbl (MaskingMorZ): Define.
  47         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
  48         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
  49         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
  50         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
  51         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
  52         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
  53         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
  54         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
  55         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
  56
  57 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  58
  59         * i386-opc.tbl: Use element rather than vector size for AVX512*
  60         scatter/gather insns.
  61         * i386-tbl.h: Re-generate.
  62
  63 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  64
  65         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
  66         (cpu_flags): Drop CpuVREX.
  67         * i386-opc.h (CpuVREX): Delete.
  68         (union i386_cpu_flags): Remove cpuvrex.
  69         * i386-init.h, i386-tbl.h: Re-generate.
  70
  71 2018-07-30  Jim Wilson  <jimw@sifive.com>
  72
  73         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
  74         fields.
  75         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
  76
  77 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
  78
  79         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
  80         * Makefile.in: Regenerated.
  81         * configure.ac: Add C-SKY.
  82         * configure: Regenerated.
  83         * csky-dis.c: New file.
  84         * csky-opc.h: New file.
  85         * disassemble.c (ARCH_csky): Define.
  86         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
  87         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
  88
  89 2018-07-27  Alan Modra  <amodra@gmail.com>
  90
  91         * ppc-opc.c (insert_sprbat): Correct function parameter and
  92         return type.
  93         (extract_sprbat): Likewise, variable too.
  94
  95 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
  96             Alan Modra  <amodra@gmail.com>
  97
  98         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
  99         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 100         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 101         support disjointed BAT.
 102         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 103         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 104         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 105
 106 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 107             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 108
 109         * i386-gen.c (adjust_broadcast_modifier): New function.
 110         (process_i386_opcode_modifier): Add an argument for operands.
 111         Adjust the Broadcast value based on operands.
 112         (output_i386_opcode): Pass operand_types to
 113         process_i386_opcode_modifier.
 114         (process_i386_opcodes): Pass NULL as operands to
 115         process_i386_opcode_modifier.
 116         * i386-opc.h (BYTE_BROADCAST): New.
 117         (WORD_BROADCAST): Likewise.
 118         (DWORD_BROADCAST): Likewise.
 119         (QWORD_BROADCAST): Likewise.
 120         (i386_opcode_modifier): Expand broadcast to 3 bits.
 121         * i386-tbl.h: Regenerated.
 122
 123 2018-07-24  Alan Modra  <amodra@gmail.com>
 124
 125         PR 23430
 126         * or1k-desc.h: Regenerate.
 127
 128 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 129
 130         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 131         vcvtusi2ss, and vcvtusi2sd.
 132         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 133         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 134         * i386-tbl.h: Re-generate.
 135
 136 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 137
 138         * arc-opc.c (extract_w6): Fix extending the sign.
 139
 140 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 141
 142         * arc-tbl.h (vewt): Allow it for ARC EM family.
 143
 144 2018-07-23  Alan Modra  <amodra@gmail.com>
 145
 146         PR 23419
 147         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 148         opcode variants for mtspr/mfspr encodings.
 149
 150 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 151             Maciej W. Rozycki  <macro@mips.com>
 152
 153         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 154         loongson3a descriptors.
 155         (parse_mips_ase_option): Handle -M loongson-mmi option.
 156         (print_mips_disassembler_options): Document -M loongson-mmi.
 157         * mips-opc.c (LMMI): New macro.
 158         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 159         instructions.
 160
 161 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 162
 163         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 164         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 165         IgnoreSize and [XYZ]MMword where applicable.
 166         * i386-tbl.h: Re-generate.
 167
 168 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 171         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 172         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 173         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 174         * i386-tbl.h: Re-generate.
 175
 176 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 177
 178         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 179         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 180         VPCLMULQDQ templates into their respective AVX512VL counterparts
 181         where possible, using Disp8ShiftVL and CheckRegSize instead of
 182         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 183         * i386-tbl.h: Re-generate.
 184
 185 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 186
 187         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 188         AVX512VL counterparts where possible, using Disp8ShiftVL and
 189         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 190         IgnoreSize) as appropriate.
 191         * i386-tbl.h: Re-generate.
 192
 193 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 194
 195         * i386-opc.tbl: Fold AVX512BW templates into their respective
 196         AVX512VL counterparts where possible, using Disp8ShiftVL and
 197         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 198         IgnoreSize) as appropriate.
 199         * i386-tbl.h: Re-generate.
 200
 201 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 202
 203         * i386-opc.tbl: Fold AVX512CD templates into their respective
 204         AVX512VL counterparts where possible, using Disp8ShiftVL and
 205         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 206         IgnoreSize) as appropriate.
 207         * i386-tbl.h: Re-generate.
 208
 209 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 210
 211         * i386-opc.h (DISP8_SHIFT_VL): New.
 212         * i386-opc.tbl (Disp8ShiftVL):  Define.
 213         (various): Fold AVX512VL templates into their respective
 214         AVX512F counterparts where possible, using Disp8ShiftVL and
 215         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 216         IgnoreSize) as appropriate.
 217         * i386-tbl.h: Re-generate.
 218
 219 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 220
 221         * Makefile.am: Change dependencies and rule for
 222         $(srcdir)/i386-init.h.
 223         * Makefile.in: Re-generate.
 224         * i386-gen.c (process_i386_opcodes): New local variable
 225         "marker". Drop opening of input file. Recognize marker and line
 226         number directives.
 227         * i386-opc.tbl (OPCODE_I386_H): Define.
 228         (i386-opc.h): Include it.
 229         (None): Undefine.
 230
 231 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 232
 233         PR gas/23418
 234         * i386-opc.h (Byte): Update comments.
 235         (Word): Likewise.
 236         (Dword): Likewise.
 237         (Fword): Likewise.
 238         (Qword): Likewise.
 239         (Tbyte): Likewise.
 240         (Xmmword): Likewise.
 241         (Ymmword): Likewise.
 242         (Zmmword): Likewise.
 243         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 244         vcvttps2uqq.
 245         * i386-tbl.h: Regenerated.
 246
 247 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 248
 249         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 250         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 251         * aarch64-asm-2.c: Regenerate.
 252         * aarch64-dis-2.c: Regenerate.
 253         * aarch64-opc-2.c: Regenerate.
 254
 255 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 256
 257         PR binutils/23192
 258         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 259         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 260         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 261         sqdmulh, sqrdmulh): Use Em16.
 262
 263 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 264
 265         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 266         csdb together with them.
 267         (thumb32_opcodes): Likewise.
 268
 269 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 270
 271         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 272         requiring 32-bit registers as operands 2 and 3. Improve
 273         comments.
 274         (mwait, mwaitx): Fold templates. Improve comments.
 275         OPERAND_TYPE_INOUTPORTREG.
 276         * i386-tbl.h: Re-generate.
 277
 278 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 279
 280         * i386-gen.c (operand_type_init): Remove
 281         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 282         OPERAND_TYPE_INOUTPORTREG.
 283         * i386-init.h: Re-generate.
 284
 285 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 286
 287         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 288         (wrssq, wrussq): Add Qword.
 289         * i386-tbl.h: Re-generate.
 290
 291 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 292
 293         * i386-opc.h: Rename OTMax to OTNum.
 294         (OTNumOfUints): Adjust calculation.
 295         (OTUnused): Directly alias to OTNum.
 296
 297 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 298
 299         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 300         `reg_xys'.
 301         (lea_reg_xys): Likewise.
 302         (print_insn_loop_primitive): Rename `reg' local variable to
 303         `reg_dxy'.
 304
 305 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 306
 307         PR binutils/23242
 308         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 309
 310 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 311
 312         PR binutils/23369
 313         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 314         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 315
 316 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 317
 318         PR tdep/8282
 319         * mips-dis.c (mips_option_arg_t): New enumeration.
 320         (mips_options): New variable.
 321         (disassembler_options_mips): New function.
 322         (print_mips_disassembler_options): Reimplement in terms of
 323         `disassembler_options_mips'.
 324         * arm-dis.c (disassembler_options_arm): Adapt to using the
 325         `disasm_options_and_args_t' structure.
 326         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 327         * s390-dis.c (disassembler_options_s390): Likewise.
 328
 329 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 330
 331         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 332         expected result.
 333         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 334         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 335         * testsuite/ld-arm/tls-longplt.d: Likewise.
 336
 337 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 338
 339         PR binutils/23192
 340         * aarch64-asm-2.c: Regenerate.
 341         * aarch64-dis-2.c: Likewise.
 342         * aarch64-opc-2.c: Likewise.
 343         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 344         * aarch64-opc.c (operand_general_constraint_met_p,
 345         aarch64_print_operand): Likewise.
 346         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 347         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 348         fmlal2, fmlsl2.
 349         (AARCH64_OPERANDS): Add Em2.
 350
 351 2018-06-26  Nick Clifton  <nickc@redhat.com>
 352
 353         * po/uk.po: Updated Ukranian translation.
 354         * po/de.po: Updated German translation.
 355         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 356
 357 2018-06-26  Nick Clifton  <nickc@redhat.com>
 358
 359         * nfp-dis.c: Fix spelling mistake.
 360
 361 2018-06-24  Nick Clifton  <nickc@redhat.com>
 362
 363         * configure: Regenerate.
 364         * po/opcodes.pot: Regenerate.
 365
 366 2018-06-24  Nick Clifton  <nickc@redhat.com>
 367
 368         2.31 branch created.
 369
 370 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 371
 372         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 373         * aarch64-asm-2.c: Regenerate.
 374         * aarch64-dis-2.c: Likewise.
 375
 376 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 377
 378         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 379         `-M ginv' option description.
 380
 381 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 382
 383         PR gas/23305
 384         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 385         la and lla.
 386
 387 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 388
 389         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 390         * configure.ac: Remove AC_PREREQ.
 391         * Makefile.in: Re-generate.
 392         * aclocal.m4: Re-generate.
 393         * configure: Re-generate.
 394
 395 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 396
 397         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 398         mips64r6 descriptors.
 399         (parse_mips_ase_option): Handle -Mginv option.
 400         (print_mips_disassembler_options): Document -Mginv.
 401         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 402         (GINV): New macro.
 403         (mips_opcodes): Define ginvi and ginvt.
 404
 405 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 406             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 407
 408         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 409         * mips-opc.c (CRC, CRC64): New macros.
 410         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 411         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 412         crc32cd for CRC64.
 413
 414 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 415
 416         PR 20319
 417         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 418         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 419
 420 2018-06-06  Alan Modra  <amodra@gmail.com>
 421
 422         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 423         setjmp.  Move init for some other vars later too.
 424
 425 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 426
 427         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 428         (dis_private): Add new fields for property section tracking.
 429         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 430         (xtensa_instruction_fits): New functions.
 431         (fetch_data): Bump minimal fetch size to 4.
 432         (print_insn_xtensa): Make struct dis_private static.
 433         Load and prepare property table on section change.
 434         Don't disassemble literals. Don't disassemble instructions that
 435         cross property table boundaries.
 436
 437 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 438
 439         * configure: Regenerated.
 440
 441 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 442
 443         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 444         * i386-tbl.h: Re-generate.
 445
 446 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 447
 448         * i386-opc.tbl (sldt, str): Add NoRex64.
 449         * i386-tbl.h: Re-generate.
 450
 451 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 452
 453         * i386-opc.tbl (invpcid): Add Oword.
 454         * i386-tbl.h: Re-generate.
 455
 456 2018-06-01  Alan Modra  <amodra@gmail.com>
 457
 458         * sysdep.h (_bfd_error_handler): Don't declare.
 459         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 460         * rl78-decode.opc: Likewise.
 461         * msp430-decode.c: Regenerate.
 462         * rl78-decode.c: Regenerate.
 463
 464 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 465
 466         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 467         * i386-init.h : Regenerated.
 468
 469 2018-05-25  Alan Modra  <amodra@gmail.com>
 470
 471         * Makefile.in: Regenerate.
 472         * po/POTFILES.in: Regenerate.
 473
 474 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 475
 476         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 477         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 478         (insert_bab, extract_bab, insert_btab, extract_btab,
 479         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 480         (BAT, BBA VBA RBS XB6S): Delete macros.
 481         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 482         (BB, BD, RBX, XC6): Update for new macros.
 483         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 484         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 485         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 486         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 487
 488 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 489
 490         * Makefile.am: Add support for s12z architecture.
 491         * configure.ac: Likewise.
 492         * disassemble.c: Likewise.
 493         * disassemble.h: Likewise.
 494         * Makefile.in: Regenerate.
 495         * configure: Regenerate.
 496         * s12z-dis.c: New file.
 497         * s12z.h: New file.
 498
 499 2018-05-18  Alan Modra  <amodra@gmail.com>
 500
 501         * nfp-dis.c: Don't #include libbfd.h.
 502         (init_nfp3200_priv): Use bfd_get_section_contents.
 503         (nit_nfp6000_mecsr_sec): Likewise.
 504
 505 2018-05-17  Nick Clifton  <nickc@redhat.com>
 506
 507         * po/zh_CN.po: Updated simplified Chinese translation.
 508
 509 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 510
 511         PR binutils/23109
 512         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 513         * aarch64-dis-2.c: Regenerate.
 514
 515 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 516
 517         PR binutils/21446
 518         * aarch64-asm.c (opintl.h): Include.
 519         (aarch64_ins_sysreg): Enforce read/write constraints.
 520         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 521         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 522         (F_REG_READ, F_REG_WRITE): New.
 523         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 524         AARCH64_OPND_SYSREG.
 525         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 526         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 527         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 528         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 529         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 530         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 531         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 532         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 533         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 534         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 535         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 536         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 537         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 538         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 539         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 540         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 541         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 542
 543 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 544
 545         PR binutils/21446
 546         * aarch64-dis.c (no_notes: New.
 547         (parse_aarch64_dis_option): Support notes.
 548         (aarch64_decode_insn, print_operands): Likewise.
 549         (print_aarch64_disassembler_options): Document notes.
 550         * aarch64-opc.c (aarch64_print_operand): Support notes.
 551
 552 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 553
 554         PR binutils/21446
 555         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 556         and take error struct.
 557         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 558         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 559         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 560         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 561         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 562         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 563         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 564         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 565         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 566         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 567         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 568         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 569         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 570         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 571         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 572         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 573         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 574         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 575         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 576         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 577         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 578         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 579         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 580         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 581         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 582         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 583         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 584         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 585         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 586         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 587         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 588         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 589         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 590         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 591         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 592         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 593         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 594         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 595         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 596         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 597         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 598         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 599         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 600         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 601         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 602         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 603         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 604         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 605         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 606         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 607         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 608         (determine_disassembling_preference, aarch64_decode_insn,
 609         print_insn_aarch64_word, print_insn_data): Take errors struct.
 610         (print_insn_aarch64): Use errors.
 611         * aarch64-asm-2.c: Regenerate.
 612         * aarch64-dis-2.c: Regenerate.
 613         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 614         boolean in aarch64_insert_operan.
 615         (print_operand_extractor): Likewise.
 616         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 617
 618 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 619
 620         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 621
 622 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 623
 624         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 625
 626 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 627
 628         * cr16-opc.c (cr16_instruction): Comment typo fix.
 629         * hppa-dis.c (print_insn_hppa): Likewise.
 630
 631 2018-05-08  Jim Wilson  <jimw@sifive.com>
 632
 633         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 634         (match_c_slli64, match_srxi_as_c_srxi): New.
 635         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 636         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 637         <c.slli, c.srli, c.srai>: Use match_s_slli.
 638         <c.slli64, c.srli64, c.srai64>: New.
 639
 640 2018-05-08  Alan Modra  <amodra@gmail.com>
 641
 642         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 643         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 644         partition opcode space for index lookup.
 645
 646 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 647
 648         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 649         <insn_length>: ...with this.  Update usage.
 650         Remove duplicate call to *info->memory_error_func.
 651
 652 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 653             H.J. Lu  <hongjiu.lu@intel.com>
 654
 655         * i386-dis.c (Gva): New.
 656         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 657         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 658         (prefix_table): New instructions (see prefix above).
 659         (mod_table): New instructions (see prefix above).
 660         (OP_G): Handle va_mode.
 661         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 662         CPU_MOVDIR64B_FLAGS.
 663         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 664         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 665         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 666         * i386-opc.tbl: Add movidir{i,64b}.
 667         * i386-init.h: Regenerated.
 668         * i386-tbl.h: Likewise.
 669
 670 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 671
 672         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 673         AddrPrefixOpReg.
 674         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 675         (AddrPrefixOpReg): This.
 676         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 677         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 678
 679 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 680
 681         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 682         (vle_num_opcodes): Likewise.
 683         (spe2_num_opcodes): Likewise.
 684         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 685         initialization loop.
 686         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 687         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 688         only once.
 689
 690 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 691
 692         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 693
 694 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 695
 696         Makefile.am: Added nfp-dis.c.
 697         configure.ac: Added bfd_nfp_arch.
 698         disassemble.h: Added print_insn_nfp prototype.
 699         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 700         nfp-dis.c: New, for NFP support.
 701         po/POTFILES.in: Added nfp-dis.c to the list.
 702         Makefile.in: Regenerate.
 703         configure: Regenerate.
 704
 705 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 706
 707         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 708         templates into their base ones.
 709         * i386-tlb.h: Re-generate.
 710
 711 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 712
 713         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 714         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 715         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 716         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 717         * i386-init.h: Re-generate.
 718
 719 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 720
 721         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 722         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 723         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 724         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 725         comment.
 726         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 727         and CpuRegMask.
 728         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 729         CpuRegMask: Delete.
 730         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 731         cpuregzmm, and cpuregmask.
 732         * i386-init.h: Re-generate.
 733         * i386-tbl.h: Re-generate.
 734
 735 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 736
 737         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 738         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 739         * i386-init.h: Re-generate.
 740
 741 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 742
 743         * i386-gen.c (VexImmExt): Delete.
 744         * i386-opc.h (VexImmExt, veximmext): Delete.
 745         * i386-opc.tbl: Drop all VexImmExt uses.
 746         * i386-tlb.h: Re-generate.
 747
 748 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 749
 750         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 751         register-only forms.
 752         * i386-tlb.h: Re-generate.
 753
 754 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 755
 756         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 757
 758 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 759
 760         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 761         PREFIX_0F1C.
 762         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 763         (cpu_flags): Add CpuCLDEMOTE.
 764         * i386-init.h: Regenerate.
 765         * i386-opc.h (enum): Add CpuCLDEMOTE,
 766         (i386_cpu_flags): Add cpucldemote.
 767         * i386-opc.tbl: Add cldemote.
 768         * i386-tbl.h: Regenerate.
 769
 770 2018-04-16  Alan Modra  <amodra@gmail.com>
 771
 772         * Makefile.am: Remove sh5 and sh64 support.
 773         * configure.ac: Likewise.
 774         * disassemble.c: Likewise.
 775         * disassemble.h: Likewise.
 776         * sh-dis.c: Likewise.
 777         * sh64-dis.c: Delete.
 778         * sh64-opc.c: Delete.
 779         * sh64-opc.h: Delete.
 780         * Makefile.in: Regenerate.
 781         * configure: Regenerate.
 782         * po/POTFILES.in: Regenerate.
 783
 784 2018-04-16  Alan Modra  <amodra@gmail.com>
 785
 786         * Makefile.am: Remove w65 support.
 787         * configure.ac: Likewise.
 788         * disassemble.c: Likewise.
 789         * disassemble.h: Likewise.
 790         * w65-dis.c: Delete.
 791         * w65-opc.h: Delete.
 792         * Makefile.in: Regenerate.
 793         * configure: Regenerate.
 794         * po/POTFILES.in: Regenerate.
 795
 796 2018-04-16  Alan Modra  <amodra@gmail.com>
 797
 798         * configure.ac: Remove we32k support.
 799         * configure: Regenerate.
 800
 801 2018-04-16  Alan Modra  <amodra@gmail.com>
 802
 803         * Makefile.am: Remove m88k support.
 804         * configure.ac: Likewise.
 805         * disassemble.c: Likewise.
 806         * disassemble.h: Likewise.
 807         * m88k-dis.c: Delete.
 808         * Makefile.in: Regenerate.
 809         * configure: Regenerate.
 810         * po/POTFILES.in: Regenerate.
 811
 812 2018-04-16  Alan Modra  <amodra@gmail.com>
 813
 814         * Makefile.am: Remove i370 support.
 815         * configure.ac: Likewise.
 816         * disassemble.c: Likewise.
 817         * disassemble.h: Likewise.
 818         * i370-dis.c: Delete.
 819         * i370-opc.c: Delete.
 820         * Makefile.in: Regenerate.
 821         * configure: Regenerate.
 822         * po/POTFILES.in: Regenerate.
 823
 824 2018-04-16  Alan Modra  <amodra@gmail.com>
 825
 826         * Makefile.am: Remove h8500 support.
 827         * configure.ac: Likewise.
 828         * disassemble.c: Likewise.
 829         * disassemble.h: Likewise.
 830         * h8500-dis.c: Delete.
 831         * h8500-opc.h: Delete.
 832         * Makefile.in: Regenerate.
 833         * configure: Regenerate.
 834         * po/POTFILES.in: Regenerate.
 835
 836 2018-04-16  Alan Modra  <amodra@gmail.com>
 837
 838         * configure.ac: Remove tahoe support.
 839         * configure: Regenerate.
 840
 841 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 842
 843         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 844         umwait.
 845         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 846         64-bit mode.
 847         * i386-tbl.h: Regenerated.
 848
 849 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 850
 851         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 852         PREFIX_MOD_1_0FAE_REG_6.
 853         (va_mode): New.
 854         (OP_E_register): Use va_mode.
 855         * i386-dis-evex.h (prefix_table):
 856         New instructions (see prefixes above).
 857         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 858         (cpu_flags): Likewise.
 859         * i386-opc.h (enum): Likewise.
 860         (i386_cpu_flags): Likewise.
 861         * i386-opc.tbl: Add umonitor, umwait, tpause.
 862         * i386-init.h: Regenerate.
 863         * i386-tbl.h: Likewise.
 864
 865 2018-04-11  Alan Modra  <amodra@gmail.com>
 866
 867         * opcodes/i860-dis.c: Delete.
 868         * opcodes/i960-dis.c: Delete.
 869         * Makefile.am: Remove i860 and i960 support.
 870         * configure.ac: Likewise.
 871         * disassemble.c: Likewise.
 872         * disassemble.h: Likewise.
 873         * Makefile.in: Regenerate.
 874         * configure: Regenerate.
 875         * po/POTFILES.in: Regenerate.
 876
 877 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 878
 879         PR binutils/23025
 880         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 881         to 0.
 882         (print_insn): Clear vex instead of vex.evex.
 883
 884 2018-04-04  Nick Clifton  <nickc@redhat.com>
 885
 886         * po/es.po: Updated Spanish translation.
 887
 888 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 889
 890         * i386-gen.c (opcode_modifiers): Delete VecESize.
 891         * i386-opc.h (VecESize): Delete.
 892         (struct i386_opcode_modifier): Delete vecesize.
 893         * i386-opc.tbl: Drop VecESize.
 894         * i386-tlb.h: Re-generate.
 895
 896 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 897
 898         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 899         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 900         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 901         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 902         * i386-tlb.h: Re-generate.
 903
 904 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 905
 906         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 907         Fold AVX512 forms
 908         * i386-tlb.h: Re-generate.
 909
 910 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 911
 912         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 913         (vex_len_table): Drop Y for vcvt*2si.
 914         (putop): Replace plain 'Y' handling by abort().
 915
 916 2018-03-28  Nick Clifton  <nickc@redhat.com>
 917
 918         PR 22988
 919         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 920         instructions with only a base address register.
 921         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 922         handle AARHC64_OPND_SVE_ADDR_R.
 923         (aarch64_print_operand): Likewise.
 924         * aarch64-asm-2.c: Regenerate.
 925         * aarch64_dis-2.c: Regenerate.
 926         * aarch64-opc-2.c: Regenerate.
 927
 928 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 929
 930         * i386-opc.tbl: Drop VecESize from register only insn forms and
 931         memory forms not allowing broadcast.
 932         * i386-tlb.h: Re-generate.
 933
 934 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 935
 936         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 937         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 938         sha256*): Drop Disp<N>.
 939
 940 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 941
 942         * i386-dis.c (EbndS, bnd_swap_mode): New.
 943         (prefix_table): Use EbndS.
 944         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 945         * i386-opc.tbl (bndmov): Move misplaced Load.
 946         * i386-tlb.h: Re-generate.
 947
 948 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 949
 950         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 951         templates allowing memory operands and folded ones for register
 952         only flavors.
 953         * i386-tlb.h: Re-generate.
 954
 955 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 956
 957         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 958         256-bit templates. Drop redundant leftover Disp<N>.
 959         * i386-tlb.h: Re-generate.
 960
 961 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 962
 963         * riscv-opc.c (riscv_insn_types): New.
 964
 965 2018-03-13  Nick Clifton  <nickc@redhat.com>
 966
 967         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 968
 969 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 970
 971         * i386-opc.tbl: Add Optimize to clr.
 972         * i386-tbl.h: Regenerated.
 973
 974 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 975
 976         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 977         * i386-opc.h (OldGcc): Removed.
 978         (i386_opcode_modifier): Remove oldgcc.
 979         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 980         instructions for old (<= 2.8.1) versions of gcc.
 981         * i386-tbl.h: Regenerated.
 982
 983 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 984
 985         * i386-opc.h (EVEXDYN): New.
 986         * i386-opc.tbl: Fold various AVX512VL templates.
 987         * i386-tlb.h: Re-generate.
 988
 989 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 990
 991         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 992         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 993         vpexpandd, vpexpandq): Fold AFX512VF templates.
 994         * i386-tlb.h: Re-generate.
 995
 996 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 997
 998         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 999         Fold 128- and 256-bit VEX-encoded templates.
1000         * i386-tlb.h: Re-generate.
1001
1002 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1003
1004         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1005         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1006         vpexpandd, vpexpandq): Fold AVX512F templates.
1007         * i386-tlb.h: Re-generate.
1008
1009 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1010
1011         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1012         64-bit templates. Drop Disp<N>.
1013         * i386-tlb.h: Re-generate.
1014
1015 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1016
1017         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1018         and 256-bit templates.
1019         * i386-tlb.h: Re-generate.
1020
1021 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1022
1023         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1024         * i386-tlb.h: Re-generate.
1025
1026 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1027
1028         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1029         Drop NoAVX.
1030         * i386-tlb.h: Re-generate.
1031
1032 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1033
1034         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1035         * i386-tlb.h: Re-generate.
1036
1037 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1038
1039         * i386-gen.c (opcode_modifiers): Delete FloatD.
1040         * i386-opc.h (FloatD): Delete.
1041         (struct i386_opcode_modifier): Delete floatd.
1042         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1043         FloatD by D.
1044         * i386-tlb.h: Re-generate.
1045
1046 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1047
1048         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1049
1050 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1051
1052         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1053         * i386-tlb.h: Re-generate.
1054
1055 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1056
1057         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1058         forms.
1059         * i386-tlb.h: Re-generate.
1060
1061 2018-03-07  Alan Modra  <amodra@gmail.com>
1062
1063         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1064         bfd_arch_rs6000.
1065         * disassemble.h (print_insn_rs6000): Delete.
1066         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1067         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1068         (print_insn_rs6000): Delete.
1069
1070 2018-03-03  Alan Modra  <amodra@gmail.com>
1071
1072         * sysdep.h (opcodes_error_handler): Define.
1073         (_bfd_error_handler): Declare.
1074         * Makefile.am: Remove stray #.
1075         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1076         EDIT" comment.
1077         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1078         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1079         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1080         opcodes_error_handler to print errors.  Standardize error messages.
1081         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1082         and include opintl.h.
1083         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1084         * i386-gen.c: Standardize error messages.
1085         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1086         * Makefile.in: Regenerate.
1087         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1088         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1089         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1090         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1091         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1092         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1093         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1094         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1095         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1096         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1097         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1098         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1099         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1100
1101 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1102
1103         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1104         vpsub[bwdq] instructions.
1105         * i386-tbl.h: Regenerated.
1106
1107 2018-03-01  Alan Modra  <amodra@gmail.com>
1108
1109         * configure.ac (ALL_LINGUAS): Sort.
1110         * configure: Regenerate.
1111
1112 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1113
1114         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1115         macro by assignements.
1116
1117 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1118
1119         PR gas/22871
1120         * i386-gen.c (opcode_modifiers): Add Optimize.
1121         * i386-opc.h (Optimize): New enum.
1122         (i386_opcode_modifier): Add optimize.
1123         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1124         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1125         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1126         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1127         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1128         vpxord and vpxorq.
1129         * i386-tbl.h: Regenerated.
1130
1131 2018-02-26  Alan Modra  <amodra@gmail.com>
1132
1133         * crx-dis.c (getregliststring): Allocate a large enough buffer
1134         to silence false positive gcc8 warning.
1135
1136 2018-02-22  Shea Levy <shea@shealevy.com>
1137
1138         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1139
1140 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1141
1142         * i386-opc.tbl: Add {rex},
1143         * i386-tbl.h: Regenerated.
1144
1145 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1146
1147         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1148         (mips16_opcodes): Replace `M' with `m' for "restore".
1149
1150 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1151
1152         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1153
1154 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1155
1156         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1157         variable to `function_index'.
1158
1159 2018-02-13  Nick Clifton  <nickc@redhat.com>
1160
1161         PR 22823
1162         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1163         about truncation of printing.
1164
1165 2018-02-12  Henry Wong <henry@stuffedcow.net>
1166
1167         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1168
1169 2018-02-05  Nick Clifton  <nickc@redhat.com>
1170
1171         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1172
1173 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1174
1175         * i386-dis.c (enum): Add pconfig.
1176         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1177         (cpu_flags): Add CpuPCONFIG.
1178         * i386-opc.h (enum): Add CpuPCONFIG.
1179         (i386_cpu_flags): Add cpupconfig.
1180         * i386-opc.tbl: Add PCONFIG instruction.
1181         * i386-init.h: Regenerate.
1182         * i386-tbl.h: Likewise.
1183
1184 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1185
1186         * i386-dis.c (enum): Add PREFIX_0F09.
1187         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1188         (cpu_flags): Add CpuWBNOINVD.
1189         * i386-opc.h (enum): Add CpuWBNOINVD.
1190         (i386_cpu_flags): Add cpuwbnoinvd.
1191         * i386-opc.tbl: Add WBNOINVD instruction.
1192         * i386-init.h: Regenerate.
1193         * i386-tbl.h: Likewise.
1194
1195 2018-01-17  Jim Wilson  <jimw@sifive.com>
1196
1197         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1198
1199 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1200
1201         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1202         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1203         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1204         (cpu_flags): Add CpuIBT, CpuSHSTK.
1205         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1206         (i386_cpu_flags): Add cpuibt, cpushstk.
1207         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1208         * i386-init.h: Regenerate.
1209         * i386-tbl.h: Likewise.
1210
1211 2018-01-16  Nick Clifton  <nickc@redhat.com>
1212
1213         * po/pt_BR.po: Updated Brazilian Portugese translation.
1214         * po/de.po: Updated German translation.
1215
1216 2018-01-15  Jim Wilson  <jimw@sifive.com>
1217
1218         * riscv-opc.c (match_c_nop): New.
1219         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1220
1221 2018-01-15  Nick Clifton  <nickc@redhat.com>
1222
1223         * po/uk.po: Updated Ukranian translation.
1224
1225 2018-01-13  Nick Clifton  <nickc@redhat.com>
1226
1227         * po/opcodes.pot: Regenerated.
1228
1229 2018-01-13  Nick Clifton  <nickc@redhat.com>
1230
1231         * configure: Regenerate.
1232
1233 2018-01-13  Nick Clifton  <nickc@redhat.com>
1234
1235         2.30 branch created.
1236
1237 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1238
1239         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1240         * i386-tbl.h: Regenerate.
1241
1242 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1243
1244         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1245         * i386-tbl.h: Re-generate.
1246
1247 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1248
1249         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1250         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1251         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1252         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1253         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1254         Disp8MemShift of AVX512VL forms.
1255         * i386-tbl.h: Re-generate.
1256
1257 2018-01-09  Jim Wilson  <jimw@sifive.com>
1258
1259         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1260         then the hi_addr value is zero.
1261
1262 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1263
1264         * arm-dis.c (arm_opcodes): Add csdb.
1265         (thumb32_opcodes): Add csdb.
1266
1267 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1268
1269         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1270         * aarch64-asm-2.c: Regenerate.
1271         * aarch64-dis-2.c: Regenerate.
1272         * aarch64-opc-2.c: Regenerate.
1273
1274 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1275
1276         PR gas/22681
1277         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1278         Remove AVX512 vmovd with 64-bit operands.
1279         * i386-tbl.h: Regenerated.
1280
1281 2018-01-05  Jim Wilson  <jimw@sifive.com>
1282
1283         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1284         jalr.
1285
1286 2018-01-03  Alan Modra  <amodra@gmail.com>
1287
1288         Update year range in copyright notice of all files.
1289
1290 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1291
1292         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1293         and OPERAND_TYPE_REGZMM entries.
1294
1295 For older changes see ChangeLog-2017
1296 \f
1297 Copyright (C) 2018 Free Software Foundation, Inc.
1298
1299 Copying and distribution of this file, with or without modification,
1300 are permitted in any medium without royalty provided the copyright
1301 notice and this notice are preserved.
1302
1303 Local Variables:
1304 mode: change-log
1305 left-margin: 8
1306 fill-column: 74
1307 version-control: never
1308 End: