opcodes/ChangeLog

   1 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR gas/24625
   4         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
   5         Disp8ShiftVL.
   6         * i386-tbl.h: Regenerated.
   7
   8 2019-05-24  Alan Modra  <amodra@gmail.com>
   9
  10         * po/POTFILES.in: Regenerate.
  11
  12 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  13             Alan Modra  <amodra@gmail.com>
  14
  15         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
  16         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
  17         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
  18         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
  19         XTOP>): Define and add entries.
  20         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
  21         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
  22         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
  23         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
  24
  25 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  26             Alan Modra  <amodra@gmail.com>
  27
  28         * ppc-dis.c (ppc_opts): Add "future" entry.
  29         (PREFIX_OPCD_SEGS): Define.
  30         (prefix_opcd_indices): New array.
  31         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
  32         (lookup_prefix): New function.
  33         (print_insn_powerpc): Handle 64-bit prefix instructions.
  34         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
  35         (PMRR, POWERXX): Define.
  36         (prefix_opcodes): New instruction table.
  37         (prefix_num_opcodes): New constant.
  38
  39 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
  40
  41         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
  42         * configure: Regenerated.
  43         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
  44         and cpu/bpf.opc.
  45         (HFILES): Add bpf-desc.h and bpf-opc.h.
  46         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
  47         bpf-ibld.c and bpf-opc.c.
  48         (BPF_DEPS): Define.
  49         * Makefile.in: Regenerated.
  50         * disassemble.c (ARCH_bpf): Define.
  51         (disassembler): Add case for bfd_arch_bpf.
  52         (disassemble_init_for_target): Likewise.
  53         (enum epbf_isa_attr): Define.
  54         * disassemble.h: extern print_insn_bpf.
  55         * bpf-asm.c: Generated.
  56         * bpf-opc.h: Likewise.
  57         * bpf-opc.c: Likewise.
  58         * bpf-ibld.c: Likewise.
  59         * bpf-dis.c: Likewise.
  60         * bpf-desc.h: Likewise.
  61         * bpf-desc.c: Likewise.
  62
  63 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  64
  65         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
  66         and VMSR with the new operands.
  67
  68 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  69
  70         * arm-dis.c (enum mve_instructions): New enum
  71         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
  72         and cneg.
  73         (mve_opcodes): New instructions as above.
  74         (is_mve_encoding_conflict): Add cases for csinc, csinv,
  75         csneg and csel.
  76         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
  77
  78 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  79
  80         * arm-dis.c (emun mve_instructions): Updated for new instructions.
  81         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
  82         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
  83         uqshl, urshrl and urshr.
  84         (is_mve_okay_in_it): Add new instructions to TRUE list.
  85         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
  86         (print_insn_mve): Updated to accept new %j,
  87         %<bitfield>m and %<bitfield>n patterns.
  88
  89 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
  90
  91         * mips-opc.c (mips_builtin_opcodes): Change source register
  92         constraint for DAUI.
  93
  94 2019-05-20  Nick Clifton  <nickc@redhat.com>
  95
  96         * po/fr.po: Updated French translation.
  97
  98 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  99             Michael Collison <michael.collison@arm.com>
 100
 101         * arm-dis.c (thumb32_opcodes): Add new instructions.
 102         (enum mve_instructions): Likewise.
 103         (enum mve_undefined): Add new reasons.
 104         (is_mve_encoding_conflict): Handle new instructions.
 105         (is_mve_undefined): Likewise.
 106         (is_mve_unpredictable): Likewise.
 107         (print_mve_undefined): Likewise.
 108         (print_mve_size): Likewise.
 109
 110 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 111             Michael Collison <michael.collison@arm.com>
 112
 113         * arm-dis.c (thumb32_opcodes): Add new instructions.
 114         (enum mve_instructions): Likewise.
 115         (is_mve_encoding_conflict): Handle new instructions.
 116         (is_mve_undefined): Likewise.
 117         (is_mve_unpredictable): Likewise.
 118         (print_mve_size): Likewise.
 119
 120 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 121             Michael Collison <michael.collison@arm.com>
 122
 123         * arm-dis.c (thumb32_opcodes): Add new instructions.
 124         (enum mve_instructions): Likewise.
 125         (is_mve_encoding_conflict): Likewise.
 126         (is_mve_unpredictable): Likewise.
 127         (print_mve_size): Likewise.
 128
 129 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 130             Michael Collison <michael.collison@arm.com>
 131
 132         * arm-dis.c (thumb32_opcodes): Add new instructions.
 133         (enum mve_instructions): Likewise.
 134         (is_mve_encoding_conflict): Handle new instructions.
 135         (is_mve_undefined): Likewise.
 136         (is_mve_unpredictable): Likewise.
 137         (print_mve_size): Likewise.
 138
 139 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 140             Michael Collison <michael.collison@arm.com>
 141
 142         * arm-dis.c (thumb32_opcodes): Add new instructions.
 143         (enum mve_instructions): Likewise.
 144         (is_mve_encoding_conflict): Handle new instructions.
 145         (is_mve_undefined): Likewise.
 146         (is_mve_unpredictable): Likewise.
 147         (print_mve_size): Likewise.
 148         (print_insn_mve): Likewise.
 149
 150 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 151             Michael Collison <michael.collison@arm.com>
 152
 153         * arm-dis.c (thumb32_opcodes): Add new instructions.
 154         (print_insn_thumb32): Handle new instructions.
 155
 156 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 157             Michael Collison <michael.collison@arm.com>
 158
 159         * arm-dis.c (enum mve_instructions): Add new instructions.
 160         (enum mve_undefined): Add new reasons.
 161         (is_mve_encoding_conflict): Handle new instructions.
 162         (is_mve_undefined): Likewise.
 163         (is_mve_unpredictable): Likewise.
 164         (print_mve_undefined): Likewise.
 165         (print_mve_size): Likewise.
 166         (print_mve_shift_n): Likewise.
 167         (print_insn_mve): Likewise.
 168
 169 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 170             Michael Collison <michael.collison@arm.com>
 171
 172         * arm-dis.c (enum mve_instructions): Add new instructions.
 173         (is_mve_encoding_conflict): Handle new instructions.
 174         (is_mve_unpredictable): Likewise.
 175         (print_mve_rotate): Likewise.
 176         (print_mve_size): Likewise.
 177         (print_insn_mve): Likewise.
 178
 179 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 180             Michael Collison <michael.collison@arm.com>
 181
 182         * arm-dis.c (enum mve_instructions): Add new instructions.
 183         (is_mve_encoding_conflict): Handle new instructions.
 184         (is_mve_unpredictable): Likewise.
 185         (print_mve_size): Likewise.
 186         (print_insn_mve): Likewise.
 187
 188 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 189             Michael Collison <michael.collison@arm.com>
 190
 191         * arm-dis.c (enum mve_instructions): Add new instructions.
 192         (enum mve_undefined): Add new reasons.
 193         (is_mve_encoding_conflict): Handle new instructions.
 194         (is_mve_undefined): Likewise.
 195         (is_mve_unpredictable): Likewise.
 196         (print_mve_undefined): Likewise.
 197         (print_mve_size): Likewise.
 198         (print_insn_mve): Likewise.
 199
 200 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 201             Michael Collison <michael.collison@arm.com>
 202
 203         * arm-dis.c (enum mve_instructions): Add new instructions.
 204         (is_mve_encoding_conflict): Handle new instructions.
 205         (is_mve_undefined): Likewise.
 206         (is_mve_unpredictable): Likewise.
 207         (print_mve_size): Likewise.
 208         (print_insn_mve): Likewise.
 209
 210 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 211             Michael Collison <michael.collison@arm.com>
 212
 213         * arm-dis.c (enum mve_instructions): Add new instructions.
 214         (enum mve_unpredictable): Add new reasons.
 215         (enum mve_undefined): Likewise.
 216         (is_mve_okay_in_it): Handle new isntructions.
 217         (is_mve_encoding_conflict): Likewise.
 218         (is_mve_undefined): Likewise.
 219         (is_mve_unpredictable): Likewise.
 220         (print_mve_vmov_index): Likewise.
 221         (print_simd_imm8): Likewise.
 222         (print_mve_undefined): Likewise.
 223         (print_mve_unpredictable): Likewise.
 224         (print_mve_size): Likewise.
 225         (print_insn_mve): Likewise.
 226
 227 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 228             Michael Collison <michael.collison@arm.com>
 229
 230         * arm-dis.c (enum mve_instructions): Add new instructions.
 231         (enum mve_unpredictable): Add new reasons.
 232         (enum mve_undefined): Likewise.
 233         (is_mve_encoding_conflict): Handle new instructions.
 234         (is_mve_undefined): Likewise.
 235         (is_mve_unpredictable): Likewise.
 236         (print_mve_undefined): Likewise.
 237         (print_mve_unpredictable): Likewise.
 238         (print_mve_rounding_mode): Likewise.
 239         (print_mve_vcvt_size): Likewise.
 240         (print_mve_size): Likewise.
 241         (print_insn_mve): Likewise.
 242
 243 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 244             Michael Collison <michael.collison@arm.com>
 245
 246         * arm-dis.c (enum mve_instructions): Add new instructions.
 247         (enum mve_unpredictable): Add new reasons.
 248         (enum mve_undefined): Likewise.
 249         (is_mve_undefined): Handle new instructions.
 250         (is_mve_unpredictable): Likewise.
 251         (print_mve_undefined): Likewise.
 252         (print_mve_unpredictable): Likewise.
 253         (print_mve_size): Likewise.
 254         (print_insn_mve): Likewise.
 255
 256 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 257             Michael Collison <michael.collison@arm.com>
 258
 259         * arm-dis.c (enum mve_instructions): Add new instructions.
 260         (enum mve_undefined): Add new reasons.
 261         (insns): Add new instructions.
 262         (is_mve_encoding_conflict):
 263         (print_mve_vld_str_addr): New print function.
 264         (is_mve_undefined): Handle new instructions.
 265         (is_mve_unpredictable): Likewise.
 266         (print_mve_undefined): Likewise.
 267         (print_mve_size): Likewise.
 268         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 269         (print_insn_mve):  Handle new operands.
 270
 271 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 272             Michael Collison <michael.collison@arm.com>
 273
 274         * arm-dis.c (enum mve_instructions): Add new instructions.
 275         (enum mve_unpredictable): Add new reasons.
 276         (is_mve_encoding_conflict): Handle new instructions.
 277         (is_mve_unpredictable): Likewise.
 278         (mve_opcodes): Add new instructions.
 279         (print_mve_unpredictable): Handle new reasons.
 280         (print_mve_register_blocks): New print function.
 281         (print_mve_size): Handle new instructions.
 282         (print_insn_mve): Likewise.
 283
 284 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 285             Michael Collison <michael.collison@arm.com>
 286
 287         * arm-dis.c (enum mve_instructions): Add new instructions.
 288         (enum mve_unpredictable): Add new reasons.
 289         (enum mve_undefined): Likewise.
 290         (is_mve_encoding_conflict): Handle new instructions.
 291         (is_mve_undefined): Likewise.
 292         (is_mve_unpredictable): Likewise.
 293         (coprocessor_opcodes): Move NEON VDUP from here...
 294         (neon_opcodes): ... to here.
 295         (mve_opcodes): Add new instructions.
 296         (print_mve_undefined):  Handle new reasons.
 297         (print_mve_unpredictable): Likewise.
 298         (print_mve_size): Handle new instructions.
 299         (print_insn_neon): Handle vdup.
 300         (print_insn_mve): Handle new operands.
 301
 302 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 303             Michael Collison <michael.collison@arm.com>
 304
 305         * arm-dis.c (enum mve_instructions): Add new instructions.
 306         (enum mve_unpredictable): Add new values.
 307         (mve_opcodes): Add new instructions.
 308         (vec_condnames): New array with vector conditions.
 309         (mve_predicatenames): New array with predicate suffixes.
 310         (mve_vec_sizename): New array with vector sizes.
 311         (enum vpt_pred_state): New enum with vector predication states.
 312         (struct vpt_block): New struct type for vpt blocks.
 313         (vpt_block_state): Global struct to keep track of state.
 314         (mve_extract_pred_mask): New helper function.
 315         (num_instructions_vpt_block): Likewise.
 316         (mark_outside_vpt_block): Likewise.
 317         (mark_inside_vpt_block): Likewise.
 318         (invert_next_predicate_state): Likewise.
 319         (update_next_predicate_state): Likewise.
 320         (update_vpt_block_state): Likewise.
 321         (is_vpt_instruction): Likewise.
 322         (is_mve_encoding_conflict): Add entries for new instructions.
 323         (is_mve_unpredictable): Likewise.
 324         (print_mve_unpredictable): Handle new cases.
 325         (print_instruction_predicate): Likewise.
 326         (print_mve_size): New function.
 327         (print_vec_condition): New function.
 328         (print_insn_mve): Handle vpt blocks and new print operands.
 329
 330 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 331
 332         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 333         8, 14 and 15 for Armv8.1-M Mainline.
 334
 335 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 336             Michael Collison <michael.collison@arm.com>
 337
 338         * arm-dis.c (enum mve_instructions): New enum.
 339         (enum mve_unpredictable): Likewise.
 340         (enum mve_undefined): Likewise.
 341         (struct mopcode32): New struct.
 342         (is_mve_okay_in_it): New function.
 343         (is_mve_architecture): Likewise.
 344         (arm_decode_field): Likewise.
 345         (arm_decode_field_multiple): Likewise.
 346         (is_mve_encoding_conflict): Likewise.
 347         (is_mve_undefined): Likewise.
 348         (is_mve_unpredictable): Likewise.
 349         (print_mve_undefined): Likewise.
 350         (print_mve_unpredictable): Likewise.
 351         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 352         (print_insn_mve): New function.
 353         (print_insn_thumb32): Handle MVE architecture.
 354         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 355
 356 2019-05-10  Nick Clifton  <nickc@redhat.com>
 357
 358         PR 24538
 359         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 360         end of the table prematurely.
 361
 362 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 363
 364         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 365         macros for R6.
 366
 367 2019-05-11  Alan Modra  <amodra@gmail.com>
 368
 369         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 370         when -Mraw is in effect.
 371
 372 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 373
 374         * aarch64-dis-2.c: Regenerate.
 375         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 376         (OP_SVE_BBB): New variant set.
 377         (OP_SVE_DDDD): New variant set.
 378         (OP_SVE_HHH): New variant set.
 379         (OP_SVE_HHHU): New variant set.
 380         (OP_SVE_SSS): New variant set.
 381         (OP_SVE_SSSU): New variant set.
 382         (OP_SVE_SHH): New variant set.
 383         (OP_SVE_SBBU): New variant set.
 384         (OP_SVE_DSS): New variant set.
 385         (OP_SVE_DHHU): New variant set.
 386         (OP_SVE_VMV_HSD_BHS): New variant set.
 387         (OP_SVE_VVU_HSD_BHS): New variant set.
 388         (OP_SVE_VVVU_SD_BH): New variant set.
 389         (OP_SVE_VVVU_BHSD): New variant set.
 390         (OP_SVE_VVV_QHD_DBS): New variant set.
 391         (OP_SVE_VVV_HSD_BHS): New variant set.
 392         (OP_SVE_VVV_HSD_BHS2): New variant set.
 393         (OP_SVE_VVV_BHS_HSD): New variant set.
 394         (OP_SVE_VV_BHS_HSD): New variant set.
 395         (OP_SVE_VVV_SD): New variant set.
 396         (OP_SVE_VVU_BHS_HSD): New variant set.
 397         (OP_SVE_VZVV_SD): New variant set.
 398         (OP_SVE_VZVV_BH): New variant set.
 399         (OP_SVE_VZV_SD): New variant set.
 400         (aarch64_opcode_table): Add sve2 instructions.
 401
 402 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 403
 404         * aarch64-asm-2.c: Regenerated.
 405         * aarch64-dis-2.c: Regenerated.
 406         * aarch64-opc-2.c: Regenerated.
 407         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 408         for SVE_SHLIMM_UNPRED_22.
 409         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 410         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 411         operand.
 412
 413 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 414
 415         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 416         sve_size_tsz_bhs iclass encode.
 417         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 418         sve_size_tsz_bhs iclass decode.
 419
 420 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 421
 422         * aarch64-asm-2.c: Regenerated.
 423         * aarch64-dis-2.c: Regenerated.
 424         * aarch64-opc-2.c: Regenerated.
 425         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 426         for SVE_Zm4_11_INDEX.
 427         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 428         (fields): Handle SVE_i2h field.
 429         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 430         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 431
 432 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 433
 434         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 435         sve_shift_tsz_bhsd iclass encode.
 436         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 437         sve_shift_tsz_bhsd iclass decode.
 438
 439 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 440
 441         * aarch64-asm-2.c: Regenerated.
 442         * aarch64-dis-2.c: Regenerated.
 443         * aarch64-opc-2.c: Regenerated.
 444         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 445         (aarch64_encode_variant_using_iclass): Handle
 446         sve_shift_tsz_hsd iclass encode.
 447         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 448         sve_shift_tsz_hsd iclass decode.
 449         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 450         for SVE_SHRIMM_UNPRED_22.
 451         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 452         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 453         operand.
 454
 455 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 456
 457         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 458         sve_size_013 iclass encode.
 459         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 460         sve_size_013 iclass decode.
 461
 462 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 463
 464         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 465         sve_size_bh iclass encode.
 466         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 467         sve_size_bh iclass decode.
 468
 469 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 470
 471         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 472         sve_size_sd2 iclass encode.
 473         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 474         sve_size_sd2 iclass decode.
 475         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 476         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 477
 478 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 479
 480         * aarch64-asm-2.c: Regenerated.
 481         * aarch64-dis-2.c: Regenerated.
 482         * aarch64-opc-2.c: Regenerated.
 483         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 484         for SVE_ADDR_ZX.
 485         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 486         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 487
 488 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 489
 490         * aarch64-asm-2.c: Regenerated.
 491         * aarch64-dis-2.c: Regenerated.
 492         * aarch64-opc-2.c: Regenerated.
 493         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 494         for SVE_Zm3_11_INDEX.
 495         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 496         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 497         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 498         fields.
 499         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 500
 501 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 502
 503         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 504         sve_size_hsd2 iclass encode.
 505         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 506         sve_size_hsd2 iclass decode.
 507         * aarch64-opc.c (fields): Handle SVE_size field.
 508         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 509
 510 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 511
 512         * aarch64-asm-2.c: Regenerated.
 513         * aarch64-dis-2.c: Regenerated.
 514         * aarch64-opc-2.c: Regenerated.
 515         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 516         for SVE_IMM_ROT3.
 517         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 518         (fields): Handle SVE_rot3 field.
 519         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 520         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 521
 522 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 523
 524         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 525         instructions.
 526
 527 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 528
 529         * aarch64-tbl.h
 530         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 531         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 532         aarch64_feature_sve2bitperm): New feature sets.
 533         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 534         for feature set addresses.
 535         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 536         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 537
 538 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 539             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 540
 541         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 542         argument and set ASE_EVA_R6 appropriately.
 543         (set_default_mips_dis_options): Pass ISA to above.
 544         (parse_mips_dis_option): Likewise.
 545         * mips-opc.c (EVAR6): New macro.
 546         (mips_builtin_opcodes): Add llwpe, scwpe.
 547
 548 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 549
 550         * aarch64-asm-2.c: Regenerated.
 551         * aarch64-dis-2.c: Regenerated.
 552         * aarch64-opc-2.c: Regenerated.
 553         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 554         AARCH64_OPND_TME_UIMM16.
 555         (aarch64_print_operand): Likewise.
 556         * aarch64-tbl.h (QL_IMM_NIL): New.
 557         (TME): New.
 558         (_TME_INSN): New.
 559         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 560
 561 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 562
 563         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 564
 565 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 566             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 567
 568         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 569
 570 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 571
 572         * s12z-opc.h: Add extern "C" bracketing to help
 573         users who wish to use this interface in c++ code.
 574
 575 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 576
 577         * s12z-opc.c (bm_decode): Handle bit map operations with the
 578         "reserved0" mode.
 579
 580 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 581
 582         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 583         specifier.  Add entries for VLDR and VSTR of system registers.
 584         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 585         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 586         of %J and %K format specifier.
 587
 588 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 589
 590         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 591         Add new entries for VSCCLRM instruction.
 592         (print_insn_coprocessor): Handle new %C format control code.
 593
 594 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 595
 596         * arm-dis.c (enum isa): New enum.
 597         (struct sopcode32): New structure.
 598         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 599         set isa field of all current entries to ANY.
 600         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 601         Only match an entry if its isa field allows the current mode.
 602
 603 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 604
 605         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 606         CLRM.
 607         (print_insn_thumb32): Add logic to print %n CLRM register list.
 608
 609 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 610
 611         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 612         and %Q patterns.
 613
 614 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 615
 616         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 617         (print_insn_thumb32): Edit the switch case for %Z.
 618
 619 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 620
 621         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 622
 623 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 624
 625         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 626
 627 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 628
 629         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 630
 631 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 632
 633         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 634         Arm register with r13 and r15 unpredictable.
 635         (thumb32_opcodes): New instructions for bfx and bflx.
 636
 637 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 638
 639         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 640
 641 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 642
 643         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 644
 645 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 646
 647         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 648
 649 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 650
 651         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 652
 653 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 654
 655         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 656         "optr". ("operator" is a reserved word in c++).
 657
 658 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 659
 660         * aarch64-opc.c (aarch64_print_operand): Add case for
 661         AARCH64_OPND_Rt_SP.
 662         (verify_constraints): Likewise.
 663         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 664         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 665         to accept Rt|SP as first operand.
 666         (AARCH64_OPERANDS): Add new Rt_SP.
 667         * aarch64-asm-2.c: Regenerated.
 668         * aarch64-dis-2.c: Regenerated.
 669         * aarch64-opc-2.c: Regenerated.
 670
 671 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 672
 673         * aarch64-asm-2.c: Regenerated.
 674         * aarch64-dis-2.c: Likewise.
 675         * aarch64-opc-2.c: Likewise.
 676         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 677
 678 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 679
 680         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 681
 682 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 683
 684         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 685         * i386-init.h: Regenerated.
 686
 687 2019-04-07  Alan Modra  <amodra@gmail.com>
 688
 689         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 690         op_separator to control printing of spaces, comma and parens
 691         rather than need_comma, need_paren and spaces vars.
 692
 693 2019-04-07  Alan Modra  <amodra@gmail.com>
 694
 695         PR 24421
 696         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 697         (print_insn_neon, print_insn_arm): Likewise.
 698
 699 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 700
 701         * i386-dis-evex.h (evex_table): Updated to support BF16
 702         instructions.
 703         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 704         and EVEX_W_0F3872_P_3.
 705         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 706         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 707         * i386-opc.h (enum): Add CpuAVX512_BF16.
 708         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 709         * i386-opc.tbl: Add AVX512 BF16 instructions.
 710         * i386-init.h: Regenerated.
 711         * i386-tbl.h: Likewise.
 712
 713 2019-04-05  Alan Modra  <amodra@gmail.com>
 714
 715         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 716         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 717         to favour printing of "-" branch hint when using the "y" bit.
 718         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 719
 720 2019-04-05  Alan Modra  <amodra@gmail.com>
 721
 722         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 723         opcode until first operand is output.
 724
 725 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 726
 727         PR gas/24349
 728         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 729         (valid_bo_post_v2): Add support for 'at' branch hints.
 730         (insert_bo): Only error on branch on ctr.
 731         (get_bo_hint_mask): New function.
 732         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 733         for inserting 'at' branch hints.
 734         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 735         for extracting 'at' branch hints.
 736         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 737         (BOE): Delete operand.
 738         (BOM, BOP): New operands.
 739         (RM): Update value.
 740         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 741         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 742         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 743         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 744         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 745         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 746         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 747         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 748         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 749         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 750         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 751         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 752         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 753         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 754         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 755         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 756         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 757         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 758         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 759         bttarl+>: New extended mnemonics.
 760
 761 2019-03-28  Alan Modra  <amodra@gmail.com>
 762
 763         PR 24390
 764         * ppc-opc.c (BTF): Define.
 765         (powerpc_opcodes): Use for mtfsb*.
 766         * ppc-dis.c (print_insn_powerpc): Print fields with both
 767         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 768
 769 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 770
 771         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 772         (mapping_symbol_for_insn): Implement new algorithm.
 773         (print_insn): Remove duplicate code.
 774
 775 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 776
 777         * aarch64-dis.c (print_insn_aarch64):
 778         Implement override.
 779
 780 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 781
 782         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 783         order.
 784
 785 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 786
 787         * aarch64-dis.c (last_stop_offset): New.
 788         (print_insn_aarch64): Use stop_offset.
 789
 790 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 791
 792         PR gas/24359
 793         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 794         CPU_ANY_AVX2_FLAGS.
 795         * i386-init.h: Regenerated.
 796
 797 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 798
 799         PR gas/24348
 800         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 801         vmovdqu16, vmovdqu32 and vmovdqu64.
 802         * i386-tbl.h: Regenerated.
 803
 804 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 805
 806         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 807         from vstrszb, vstrszh, and vstrszf.
 808
 809 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 810
 811         * s390-opc.txt: Add instruction descriptions.
 812
 813 2019-02-08  Jim Wilson  <jimw@sifive.com>
 814
 815         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 816         <bne>: Likewise.
 817
 818 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 819
 820         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 821
 822 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 823
 824         PR binutils/23212
 825         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 826         * aarch64-opc.c (verify_elem_sd): New.
 827         (fields): Add FLD_sz entr.
 828         * aarch64-tbl.h (_SIMD_INSN): New.
 829         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 830         fmulx scalar and vector by element isns.
 831
 832 2019-02-07  Nick Clifton  <nickc@redhat.com>
 833
 834         * po/sv.po: Updated Swedish translation.
 835
 836 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 837
 838         * s390-mkopc.c (main): Accept arch13 as cpu string.
 839         * s390-opc.c: Add new instruction formats and instruction opcode
 840         masks.
 841         * s390-opc.txt: Add new arch13 instructions.
 842
 843 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 844
 845         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 846         (aarch64_opcode): Change encoding for stg, stzg
 847         st2g and st2zg.
 848         * aarch64-asm-2.c: Regenerated.
 849         * aarch64-dis-2.c: Regenerated.
 850         * aarch64-opc-2.c: Regenerated.
 851
 852 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 853
 854         * aarch64-asm-2.c: Regenerated.
 855         * aarch64-dis-2.c: Likewise.
 856         * aarch64-opc-2.c: Likewise.
 857         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 858
 859 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 860             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 861
 862         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 863         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 864         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 865         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 866         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 867         case for ldstgv_indexed.
 868         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 869         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 870         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 871         * aarch64-asm-2.c: Regenerated.
 872         * aarch64-dis-2.c: Regenerated.
 873         * aarch64-opc-2.c: Regenerated.
 874
 875 2019-01-23  Nick Clifton  <nickc@redhat.com>
 876
 877         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 878
 879 2019-01-21  Nick Clifton  <nickc@redhat.com>
 880
 881         * po/de.po: Updated German translation.
 882         * po/uk.po: Updated Ukranian translation.
 883
 884 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 885         * mips-dis.c (mips_arch_choices): Fix typo in
 886         gs464, gs464e and gs264e descriptors.
 887
 888 2019-01-19  Nick Clifton  <nickc@redhat.com>
 889
 890         * configure: Regenerate.
 891         * po/opcodes.pot: Regenerate.
 892
 893 2018-06-24  Nick Clifton  <nickc@redhat.com>
 894
 895         2.32 branch created.
 896
 897 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 898
 899         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 900         if it is null.
 901         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 902         zero.
 903
 904 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 905
 906         * configure: Regenerate.
 907
 908 2019-01-07  Alan Modra  <amodra@gmail.com>
 909
 910         * configure: Regenerate.
 911         * po/POTFILES.in: Regenerate.
 912
 913 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 914
 915         * s12z-opc.c: New file.
 916         * s12z-opc.h: New file.
 917         * s12z-dis.c: Removed all code not directly related to display
 918         of instructions.  Used the interface provided by the new files
 919         instead.
 920         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 921         * Makefile.in: Regenerate.
 922         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 923         * configure: Regenerate.
 924
 925 2019-01-01  Alan Modra  <amodra@gmail.com>
 926
 927         Update year range in copyright notice of all files.
 928
 929 For older changes see ChangeLog-2018
 930 \f
 931 Copyright (C) 2019 Free Software Foundation, Inc.
 932
 933 Copying and distribution of this file, with or without modification,
 934 are permitted in any medium without royalty provided the copyright
 935 notice and this notice are preserved.
 936
 937 Local Variables:
 938 mode: change-log
 939 left-margin: 8
 940 fill-column: 74
 941 version-control: never
 942 End: