opcodes/ChangeLog

   1 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
   2
   3         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
   4
   5 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
   6             Matthew Fortune  <matthew.fortune@imgtec.com>
   7             Andrew Bennett <andrew.bennett@imgtec.com>
   8
   9         * mips-formats.h (INT_BIAS): New macro.
  10         (INT_ADJ): Redefine in INT_BIAS terms.
  11         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
  12         (mips_print_save_restore): New function.
  13         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
  14         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
  15         call.
  16         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
  17         (print_mips16_insn_arg): Call `mips_print_save_restore' for
  18         OP_SAVE_RESTORE_LIST handling, factored out from here.
  19         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
  20         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
  21         (mips_builtin_opcodes): Add "restore" and "save" entries.
  22         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
  23         (IAMR2): New macro.
  24         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
  25
  26 2017-06-23  Andrew Waterman  <andrew@sifive.com>
  27
  28         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
  29         alias; do not mark SLTI instruction as an alias.
  30
  31 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  32
  33         * i386-dis.c (RM_0FAE_REG_5): Removed.
  34         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
  35         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
  36         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
  37         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
  38         PREFIX_MOD_3_0F01_REG_5_RM_0.
  39         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
  40         PREFIX_MOD_3_0FAE_REG_5.
  41         (mod_table): Update MOD_0FAE_REG_5.
  42         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
  43         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
  44         * i386-tbl.h: Regenerated.
  45
  46 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  47
  48         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
  49         * i386-opc.tbl: Likewise.
  50         * i386-tbl.h: Regenerated.
  51
  52 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  53
  54         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
  55         and "jmp{&|}".
  56         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
  57         prefix.
  58
  59 2017-06-19  Nick Clifton  <nickc@redhat.com>
  60
  61         PR binutils/21614
  62         * score-dis.c (score_opcodes): Add sentinel.
  63
  64 2017-06-16  Alan Modra  <amodra@gmail.com>
  65
  66         * rx-decode.c: Regenerate.
  67
  68 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
  69
  70         PR binutils/21594
  71         * i386-dis.c (OP_E_register): Check valid bnd register.
  72         (OP_G): Likewise.
  73
  74 2017-06-15  Nick Clifton  <nickc@redhat.com>
  75
  76         PR binutils/21595
  77         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
  78         range value.
  79
  80 2017-06-15  Nick Clifton  <nickc@redhat.com>
  81
  82         PR binutils/21588
  83         * rl78-decode.opc (OP_BUF_LEN): Define.
  84         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
  85         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
  86         array.
  87         * rl78-decode.c: Regenerate.
  88
  89 2017-06-15  Nick Clifton  <nickc@redhat.com>
  90
  91         PR binutils/21586
  92         * bfin-dis.c (gregs): Clip index to prevent overflow.
  93         (regs): Likewise.
  94         (regs_lo): Likewise.
  95         (regs_hi): Likewise.
  96
  97 2017-06-14  Nick Clifton  <nickc@redhat.com>
  98
  99         PR binutils/21576
 100         * score7-dis.c (score_opcodes): Add sentinel.
 101
 102 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 103
 104         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 105         * arm-dis.c: Likewise.
 106         * ia64-dis.c: Likewise.
 107         * mips-dis.c: Likewise.
 108         * spu-dis.c: Likewise.
 109         * disassemble.h (print_insn_aarch64): New declaration, moved from
 110         include/dis-asm.h.
 111         (print_insn_big_arm, print_insn_big_mips): Likewise.
 112         (print_insn_i386, print_insn_ia64): Likewise.
 113         (print_insn_little_arm, print_insn_little_mips): Likewise.
 114
 115 2017-06-14  Nick Clifton  <nickc@redhat.com>
 116
 117         PR binutils/21587
 118         * rx-decode.opc: Include libiberty.h
 119         (GET_SCALE): New macro - validates access to SCALE array.
 120         (GET_PSCALE): New macro - validates access to PSCALE array.
 121         (DIs, SIs, S2Is, rx_disp): Use new macros.
 122         * rx-decode.c: Regenerate.
 123
 124 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 125
 126         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 127
 128 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 129
 130         * arc-dis.c (enforced_isa_mask): Declare.
 131         (cpu_types): Likewise.
 132         (parse_cpu_option): New function.
 133         (parse_disassembler_options): Use it.
 134         (print_insn_arc): Use enforced_isa_mask.
 135         (print_arc_disassembler_options): Document new options.
 136
 137 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 138
 139         * alpha-dis.c: Include disassemble.h, don't include
 140         dis-asm.h.
 141         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 142         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 143         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 144         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 145         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 146         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 147         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 148         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 149         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 150         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 151         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 152         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 153         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 154         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 155         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 156         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 157         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 158         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 159         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 160         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 161         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 162         * z80-dis.c, z8k-dis.c: Likewise.
 163         * disassemble.h: New file.
 164
 165 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 166
 167         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 168         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 169
 170 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 171
 172         * disassemble.c (disassembler): Add arguments a, big and mach.
 173         Use them.
 174
 175 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 176
 177         * i386-dis.c (NOTRACK_Fixup): New.
 178         (NOTRACK): Likewise.
 179         (NOTRACK_PREFIX): Likewise.
 180         (last_active_prefix): Likewise.
 181         (reg_table): Use NOTRACK on indirect call and jmp.
 182         (ckprefix): Set last_active_prefix.
 183         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 184         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 185         * i386-opc.h (NoTrackPrefixOk): New.
 186         (i386_opcode_modifier): Add notrackprefixok.
 187         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 188         Add notrack.
 189         * i386-tbl.h: Regenerated.
 190
 191 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 192
 193         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 194         (X_IMM2): Define.
 195         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 196         bfd_mach_sparc_v9m8.
 197         (print_insn_sparc): Handle new operand types.
 198         * sparc-opc.c (MASK_M8): Define.
 199         (v6): Add MASK_M8.
 200         (v6notlet): Likewise.
 201         (v7): Likewise.
 202         (v8): Likewise.
 203         (v9): Likewise.
 204         (v9a): Likewise.
 205         (v9b): Likewise.
 206         (v9c): Likewise.
 207         (v9d): Likewise.
 208         (v9e): Likewise.
 209         (v9v): Likewise.
 210         (v9m): Likewise.
 211         (v9andleon): Likewise.
 212         (m8): Define.
 213         (HWS_VM8): Define.
 214         (HWS2_VM8): Likewise.
 215         (sparc_opcode_archs): Add entry for "m8".
 216         (sparc_opcodes): Add OSA2017 and M8 instructions
 217         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 218         fpx{ll,ra,rl}64x,
 219         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 220         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 221         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 222         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 223         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 224         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 225         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 226         ASI_CORE_SELECT_COMMIT_NHT.
 227
 228 2017-05-18  Alan Modra  <amodra@gmail.com>
 229
 230         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 231         * aarch64-dis.c: Likewise.
 232         * aarch64-gen.c: Likewise.
 233         * aarch64-opc.c: Likewise.
 234
 235 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 236             Matthew Fortune  <matthew.fortune@imgtec.com>
 237
 238         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 239         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 240         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 241         (print_insn_arg) <OP_REG28>: Add handler.
 242         (validate_insn_args) <OP_REG28>: Handle.
 243         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 244         32-bit encoding and 9-bit immediates.
 245         (print_insn_mips16): Handle MIPS16 instructions that require
 246         32-bit encoding and MFC0/MTC0 operand decoding.
 247         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 248         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 249         (RD_C0, WR_C0, E2, E2MT): New macros.
 250         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 251         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 252         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 253         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 254         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 255         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 256         instructions, "swl", "swr", "sync" and its "sync_acquire",
 257         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 258         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 259         regular/extended entries for original MIPS16 ISA revision
 260         instructions whose extended forms are subdecoded in the MIPS16e2
 261         ISA revision: "li", "sll" and "srl".
 262
 263 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 264
 265         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 266         reference in CP0 move operand decoding.
 267
 268 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 269
 270         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 271         type to hexadecimal.
 272         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 273
 274 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 275
 276         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 277         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 278         "sync_rmb" and "sync_wmb" as aliases.
 279         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 280         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 281
 282 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 283
 284         * arc-dis.c (parse_option): Update quarkse_em option..
 285         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 286         QUARKSE1.
 287         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 288
 289 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 290
 291         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 292
 293 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 294
 295         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 296         register.
 297
 298 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 299
 300         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 301         and branches and not synthetic data instructions.
 302
 303 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 304
 305         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 306
 307 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 308
 309         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 310         * arc-opc.c (insert_r13el): New function.
 311         (R13_EL): Define.
 312         * arc-tbl.h: Add new enter/leave variants.
 313
 314 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 315
 316         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 317
 318 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 319
 320         * mips-dis.c (print_mips_disassembler_options): Add
 321         `no-aliases'.
 322
 323 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 324
 325         * mips16-opc.c (AL): New macro.
 326         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 327         of "ld" and "lw" as aliases.
 328
 329 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 330
 331         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 332         arguments.
 333
 334 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 335             Alan Modra  <amodra@gmail.com>
 336
 337         * ppc-opc.c (ELEV): Define.
 338         (vle_opcodes): Add se_rfgi and e_sc.
 339         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 340         for E200Z4.
 341
 342 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 343
 344         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 345
 346 2017-04-21  Nick Clifton  <nickc@redhat.com>
 347
 348         PR binutils/21380
 349         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 350         LD3R and LD4R.
 351
 352 2017-04-13  Alan Modra  <amodra@gmail.com>
 353
 354         * epiphany-desc.c: Regenerate.
 355         * fr30-desc.c: Regenerate.
 356         * frv-desc.c: Regenerate.
 357         * ip2k-desc.c: Regenerate.
 358         * iq2000-desc.c: Regenerate.
 359         * lm32-desc.c: Regenerate.
 360         * m32c-desc.c: Regenerate.
 361         * m32r-desc.c: Regenerate.
 362         * mep-desc.c: Regenerate.
 363         * mt-desc.c: Regenerate.
 364         * or1k-desc.c: Regenerate.
 365         * xc16x-desc.c: Regenerate.
 366         * xstormy16-desc.c: Regenerate.
 367
 368 2017-04-11  Alan Modra  <amodra@gmail.com>
 369
 370         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 371         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 372         PPC_OPCODE_TMR for e6500.
 373         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 374         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 375         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 376         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 377         (PPCHTM): Define as PPC_OPCODE_POWER8.
 378         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 379
 380 2017-04-10  Alan Modra  <amodra@gmail.com>
 381
 382         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 383         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 384         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 385         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 386
 387 2017-04-09  Pip Cet  <pipcet@gmail.com>
 388
 389         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 390         appropriate floating-point precision directly.
 391
 392 2017-04-07  Alan Modra  <amodra@gmail.com>
 393
 394         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 395         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 396         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 397         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 398         vector instructions with E6500 not PPCVEC2.
 399
 400 2017-04-06  Pip Cet  <pipcet@gmail.com>
 401
 402         * Makefile.am: Add wasm32-dis.c.
 403         * configure.ac: Add wasm32-dis.c to wasm32 target.
 404         * disassemble.c: Add wasm32 disassembler code.
 405         * wasm32-dis.c: New file.
 406         * Makefile.in: Regenerate.
 407         * configure: Regenerate.
 408         * po/POTFILES.in: Regenerate.
 409         * po/opcodes.pot: Regenerate.
 410
 411 2017-04-05  Pedro Alves  <palves@redhat.com>
 412
 413         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 414         * arm-dis.c (parse_arm_disassembler_options): Constify.
 415         * ppc-dis.c (powerpc_init_dialect): Constify local.
 416         * vax-dis.c (parse_disassembler_options): Constify.
 417
 418 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 419
 420         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 421         RISCV_GP_SYMBOL.
 422
 423 2017-03-30  Pip Cet  <pipcet@gmail.com>
 424
 425         * configure.ac: Add (empty) bfd_wasm32_arch target.
 426         * configure: Regenerate
 427         * po/opcodes.pot: Regenerate.
 428
 429 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 430
 431         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 432         OSA2015.
 433         * opcodes/sparc-opc.c (asi_table): New ASIs.
 434
 435 2017-03-29  Alan Modra  <amodra@gmail.com>
 436
 437         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 438         "raw" option.
 439         (lookup_powerpc): Don't special case -1 dialect.  Handle
 440         PPC_OPCODE_RAW.
 441         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 442         lookup_powerpc call, pass it on second.
 443
 444 2017-03-27  Alan Modra  <amodra@gmail.com>
 445
 446         PR 21303
 447         * ppc-dis.c (struct ppc_mopt): Comment.
 448         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 449
 450 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 451
 452         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 453         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 454         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 455         (insert_nps_misc_imm_offset): New function.
 456         (extract_nps_misc imm_offset): New function.
 457         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 458         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 459
 460 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 461
 462         * s390-mkopc.c (main): Remove vx2 check.
 463         * s390-opc.txt: Remove vx2 instruction flags.
 464
 465 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 466
 467         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 468         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 469         (insert_nps_imm_offset): New function.
 470         (extract_nps_imm_offset): New function.
 471         (insert_nps_imm_entry): New function.
 472         (extract_nps_imm_entry): New function.
 473
 474 2017-03-17  Alan Modra  <amodra@gmail.com>
 475
 476         PR 21248
 477         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 478         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 479         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 480
 481 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 482
 483         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 484         <c.andi>: Likewise.
 485         <c.addiw> Likewise.
 486
 487 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 488
 489         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 490
 491 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 492
 493         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 494         <srl> Likewise.
 495         <srai> Likewise.
 496         <sra> Likewise.
 497
 498 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 499
 500         * i386-gen.c (opcode_modifiers): Replace S with Load.
 501         * i386-opc.h (S): Removed.
 502         (Load): New.
 503         (i386_opcode_modifier): Replace s with load.
 504         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 505         and {evex}.  Replace S with Load.
 506         * i386-tbl.h: Regenerated.
 507
 508 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 509
 510         * i386-opc.tbl: Use CpuCET on rdsspq.
 511         * i386-tbl.h: Regenerated.
 512
 513 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 514
 515         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 516         <vsx>: Do not use PPC_OPCODE_VSX3;
 517
 518 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 519
 520         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 521
 522 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 523
 524         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 525         (MOD_0F1E_PREFIX_1): Likewise.
 526         (MOD_0F38F5_PREFIX_2): Likewise.
 527         (MOD_0F38F6_PREFIX_0): Likewise.
 528         (RM_0F1E_MOD_3_REG_7): Likewise.
 529         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 530         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 531         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 532         (PREFIX_0F1E): Likewise.
 533         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 534         (PREFIX_0F38F5): Likewise.
 535         (dis386_twobyte): Use PREFIX_0F1E.
 536         (reg_table): Add REG_0F1E_MOD_3.
 537         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 538         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 539         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 540         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 541         (three_byte_table): Use PREFIX_0F38F5.
 542         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 543         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 544         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 545         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 546         PREFIX_MOD_3_0F01_REG_5_RM_2.
 547         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 548         (cpu_flags): Add CpuCET.
 549         * i386-opc.h (CpuCET): New enum.
 550         (CpuUnused): Commented out.
 551         (i386_cpu_flags): Add cpucet.
 552         * i386-opc.tbl: Add Intel CET instructions.
 553         * i386-init.h: Regenerated.
 554         * i386-tbl.h: Likewise.
 555
 556 2017-03-06  Alan Modra  <amodra@gmail.com>
 557
 558         PR 21124
 559         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 560         (extract_raq, extract_ras, extract_rbx): New functions.
 561         (powerpc_operands): Use opposite corresponding insert function.
 562         (Q_MASK): Define.
 563         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 564         register restriction.
 565
 566 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 567
 568         * disassemble.c Include "safe-ctype.h".
 569         (disassemble_init_for_target): Handle s390 init.
 570         (remove_whitespace_and_extra_commas): New function.
 571         (disassembler_options_cmp): Likewise.
 572         * arm-dis.c: Include "libiberty.h".
 573         (NUM_ELEM): Delete.
 574         (regnames): Use long disassembler style names.
 575         Add force-thumb and no-force-thumb options.
 576         (NUM_ARM_REGNAMES): Rename from this...
 577         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 578         (get_arm_regname_num_options): Delete.
 579         (set_arm_regname_option): Likewise.
 580         (get_arm_regnames): Likewise.
 581         (parse_disassembler_options): Likewise.
 582         (parse_arm_disassembler_option): Rename from this...
 583         (parse_arm_disassembler_options): ...to this.  Make static.
 584         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 585         (print_insn): Use parse_arm_disassembler_options.
 586         (disassembler_options_arm): New function.
 587         (print_arm_disassembler_options): Handle updated regnames.
 588         * ppc-dis.c: Include "libiberty.h".
 589         (ppc_opts): Add "32" and "64" entries.
 590         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 591         (powerpc_init_dialect): Add break to switch statement.
 592         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 593         (disassembler_options_powerpc): New function.
 594         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 595         Remove printing of "32" and "64".
 596         * s390-dis.c: Include "libiberty.h".
 597         (init_flag): Remove unneeded variable.
 598         (struct s390_options_t): New structure type.
 599         (options): New structure.
 600         (init_disasm): Rename from this...
 601         (disassemble_init_s390): ...to this.  Add initializations for
 602         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 603         (print_insn_s390): Delete call to init_disasm.
 604         (disassembler_options_s390): New function.
 605         (print_s390_disassembler_options): Print using information from
 606         struct 'options'.
 607         * po/opcodes.pot: Regenerate.
 608
 609 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 610
 611         * i386-dis.c (PCMPESTR_Fixup): New.
 612         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 613         (prefix_table): Use PCMPESTR_Fixup.
 614         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 615         PCMPESTR_Fixup.
 616         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 617         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 618         Split 64-bit and non-64-bit variants.
 619         * opcodes/i386-tbl.h: Re-generate.
 620
 621 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 622
 623         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 624         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 625         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 626         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 627         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 628         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 629         (OP_SVE_V_HSD): New macros.
 630         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 631         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 632         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 633         (aarch64_opcode_table): Add new SVE instructions.
 634         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 635         for rotation operands.  Add new SVE operands.
 636         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 637         (ins_sve_quad_index): Likewise.
 638         (ins_imm_rotate): Split into...
 639         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 640         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 641         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 642         functions.
 643         (aarch64_ins_sve_addr_ri_s4): New function.
 644         (aarch64_ins_sve_quad_index): Likewise.
 645         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 646         * aarch64-asm-2.c: Regenerate.
 647         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 648         (ext_sve_quad_index): Likewise.
 649         (ext_imm_rotate): Split into...
 650         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 651         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 652         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 653         functions.
 654         (aarch64_ext_sve_addr_ri_s4): New function.
 655         (aarch64_ext_sve_quad_index): Likewise.
 656         (aarch64_ext_sve_index): Allow quad indices.
 657         (do_misc_decoding): Likewise.
 658         * aarch64-dis-2.c: Regenerate.
 659         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 660         aarch64_field_kinds.
 661         (OPD_F_OD_MASK): Widen by one bit.
 662         (OPD_F_NO_ZR): Bump accordingly.
 663         (get_operand_field_width): New function.
 664         * aarch64-opc.c (fields): Add new SVE fields.
 665         (operand_general_constraint_met_p): Handle new SVE operands.
 666         (aarch64_print_operand): Likewise.
 667         * aarch64-opc-2.c: Regenerate.
 668
 669 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 670
 671         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 672         (aarch64_feature_compnum): ...this.
 673         (SIMD_V8_3): Replace with...
 674         (COMPNUM): ...this.
 675         (CNUM_INSN): New macro.
 676         (aarch64_opcode_table): Use it for the complex number instructions.
 677
 678 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 679
 680         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 681
 682 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 683
 684         Add support for associating SPARC ASIs with an architecture level.
 685         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 686         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 687         decoding of SPARC ASIs.
 688
 689 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 690
 691         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 692         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 693
 694 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 695
 696         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 697         1 (instead of to itself). Correct typo.
 698
 699 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 700
 701         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 702         pseudoinstructions.
 703
 704 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 705
 706         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 707         (aarch64_sys_reg_supported_p): Handle them.
 708
 709 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 710
 711         * arc-opc.c (UIMM6_20R): Define.
 712         (SIMM12_20): Use above.
 713         (SIMM12_20R): Define.
 714         (SIMM3_5_S): Use above.
 715         (UIMM7_A32_11R_S): Define.
 716         (UIMM7_9_S): Use above.
 717         (UIMM3_13R_S): Define.
 718         (SIMM11_A32_7_S): Use above.
 719         (SIMM9_8R): Define.
 720         (UIMM10_A32_8_S): Use above.
 721         (UIMM8_8R_S): Define.
 722         (W6): Use above.
 723         (arc_relax_opcodes): Use all above defines.
 724
 725 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 726
 727         * arc-regs.h: Distinguish some of the registers different on
 728         ARC700 and HS38 cpus.
 729
 730 2017-02-14  Alan Modra  <amodra@gmail.com>
 731
 732         PR 21118
 733         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 734         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 735
 736 2017-02-11  Stafford Horne  <shorne@gmail.com>
 737             Alan Modra  <amodra@gmail.com>
 738
 739         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 740         Use insn_bytes_value and insn_int_value directly instead.  Don't
 741         free allocated memory until function exit.
 742
 743 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 744
 745         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 746
 747 2017-02-03  Nick Clifton  <nickc@redhat.com>
 748
 749         PR 21096
 750         * aarch64-opc.c (print_register_list): Ensure that the register
 751         list index will fir into the tb buffer.
 752         (print_register_offset_address): Likewise.
 753         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 754
 755 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 756
 757         PR 21056
 758         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 759         instructions when the previous fetch packet ends with a 32-bit
 760         instruction.
 761
 762 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 763
 764         * pru-opc.c: Remove vague reference to a future GDB port.
 765
 766 2017-01-20  Nick Clifton  <nickc@redhat.com>
 767
 768         * po/ga.po: Updated Irish translation.
 769
 770 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 771
 772         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 773
 774 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 775
 776         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 777         if FETCH_DATA returns 0.
 778         (m68k_scan_mask): Likewise.
 779         (print_insn_m68k): Update code to handle -1 return value.
 780
 781 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 782
 783         * m68k-dis.c (enum print_insn_arg_error): New.
 784         (NEXTBYTE): Replace -3 with
 785         PRINT_INSN_ARG_MEMORY_ERROR.
 786         (NEXTULONG): Likewise.
 787         (NEXTSINGLE): Likewise.
 788         (NEXTDOUBLE): Likewise.
 789         (NEXTDOUBLE): Likewise.
 790         (NEXTPACKED): Likewise.
 791         (FETCH_ARG): Likewise.
 792         (FETCH_DATA): Update comments.
 793         (print_insn_arg): Update comments. Replace magic numbers with
 794         enum.
 795         (match_insn_m68k): Likewise.
 796
 797 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 798
 799         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 800         * i386-dis-evex.h (evex_table): Updated.
 801         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 802         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 803         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 804         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 805         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 806         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 807         * i386-init.h: Regenerate.
 808         * i386-tbl.h: Ditto.
 809
 810 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 811
 812         * msp430-dis.c (msp430_singleoperand): Return -1 if
 813         msp430dis_opcode_signed returns false.
 814         (msp430_doubleoperand): Likewise.
 815         (msp430_branchinstr): Return -1 if
 816         msp430dis_opcode_unsigned returns false.
 817         (msp430x_calla_instr): Likewise.
 818         (print_insn_msp430): Likewise.
 819
 820 2017-01-05  Nick Clifton  <nickc@redhat.com>
 821
 822         PR 20946
 823         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 824         could not be matched.
 825         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 826         NULL.
 827
 828 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 829
 830         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 831         (aarch64_opcode_table): Use RCPC_INSN.
 832
 833 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 834
 835         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 836         extension.
 837         * riscv-opcodes/all-opcodes: Likewise.
 838
 839 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 840
 841         * riscv-dis.c (print_insn_args): Add fall through comment.
 842
 843 2017-01-03  Nick Clifton  <nickc@redhat.com>
 844
 845         * po/sr.po: New Serbian translation.
 846         * configure.ac (ALL_LINGUAS): Add sr.
 847         * configure: Regenerate.
 848
 849 2017-01-02  Alan Modra  <amodra@gmail.com>
 850
 851         * epiphany-desc.h: Regenerate.
 852         * epiphany-opc.h: Regenerate.
 853         * fr30-desc.h: Regenerate.
 854         * fr30-opc.h: Regenerate.
 855         * frv-desc.h: Regenerate.
 856         * frv-opc.h: Regenerate.
 857         * ip2k-desc.h: Regenerate.
 858         * ip2k-opc.h: Regenerate.
 859         * iq2000-desc.h: Regenerate.
 860         * iq2000-opc.h: Regenerate.
 861         * lm32-desc.h: Regenerate.
 862         * lm32-opc.h: Regenerate.
 863         * m32c-desc.h: Regenerate.
 864         * m32c-opc.h: Regenerate.
 865         * m32r-desc.h: Regenerate.
 866         * m32r-opc.h: Regenerate.
 867         * mep-desc.h: Regenerate.
 868         * mep-opc.h: Regenerate.
 869         * mt-desc.h: Regenerate.
 870         * mt-opc.h: Regenerate.
 871         * or1k-desc.h: Regenerate.
 872         * or1k-opc.h: Regenerate.
 873         * xc16x-desc.h: Regenerate.
 874         * xc16x-opc.h: Regenerate.
 875         * xstormy16-desc.h: Regenerate.
 876         * xstormy16-opc.h: Regenerate.
 877
 878 2017-01-02  Alan Modra  <amodra@gmail.com>
 879
 880         Update year range in copyright notice of all files.
 881
 882 For older changes see ChangeLog-2016
 883 \f
 884 Copyright (C) 2017 Free Software Foundation, Inc.
 885
 886 Copying and distribution of this file, with or without modification,
 887 are permitted in any medium without royalty provided the copyright
 888 notice and this notice are preserved.
 889
 890 Local Variables:
 891 mode: change-log
 892 left-margin: 8
 893 fill-column: 74
 894 version-control: never
 895 End: