1 2017-05-24 Yao Qi <yao.qi@linaro.org>
3 * alpha-dis.c: Include disassemble.h, don't include
5 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
6 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
7 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
8 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
9 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
10 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
11 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
12 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
13 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
14 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
15 * moxie-dis.c, msp430-dis.c, mt-dis.c:
16 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
17 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
18 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
19 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
20 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
21 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
22 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
23 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
24 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
25 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
26 * z80-dis.c, z8k-dis.c: Likewise.
27 * disassemble.h: New file.
29 2017-05-24 Yao Qi <yao.qi@linaro.org>
31 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
32 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
34 2017-05-24 Yao Qi <yao.qi@linaro.org>
36 * disassemble.c (disassembler): Add arguments a, big and mach.
39 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
41 * i386-dis.c (NOTRACK_Fixup): New.
43 (NOTRACK_PREFIX): Likewise.
44 (last_active_prefix): Likewise.
45 (reg_table): Use NOTRACK on indirect call and jmp.
46 (ckprefix): Set last_active_prefix.
47 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
48 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
49 * i386-opc.h (NoTrackPrefixOk): New.
50 (i386_opcode_modifier): Add notrackprefixok.
51 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
53 * i386-tbl.h: Regenerated.
55 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
57 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
59 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
61 (print_insn_sparc): Handle new operand types.
62 * sparc-opc.c (MASK_M8): Define.
75 (v9andleon): Likewise.
79 (sparc_opcode_archs): Add entry for "m8".
80 (sparc_opcodes): Add OSA2017 and M8 instructions
81 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
83 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
84 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
85 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
86 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
87 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
88 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
89 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
90 ASI_CORE_SELECT_COMMIT_NHT.
92 2017-05-18 Alan Modra <amodra@gmail.com>
94 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
95 * aarch64-dis.c: Likewise.
96 * aarch64-gen.c: Likewise.
97 * aarch64-opc.c: Likewise.
99 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
100 Matthew Fortune <matthew.fortune@imgtec.com>
102 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
103 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
104 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
105 (print_insn_arg) <OP_REG28>: Add handler.
106 (validate_insn_args) <OP_REG28>: Handle.
107 (print_mips16_insn_arg): Handle MIPS16 instructions that require
108 32-bit encoding and 9-bit immediates.
109 (print_insn_mips16): Handle MIPS16 instructions that require
110 32-bit encoding and MFC0/MTC0 operand decoding.
111 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
112 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
113 (RD_C0, WR_C0, E2, E2MT): New macros.
114 (mips16_opcodes): Add entries for MIPS16e2 instructions:
115 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
116 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
117 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
118 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
119 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
120 instructions, "swl", "swr", "sync" and its "sync_acquire",
121 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
122 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
123 regular/extended entries for original MIPS16 ISA revision
124 instructions whose extended forms are subdecoded in the MIPS16e2
125 ISA revision: "li", "sll" and "srl".
127 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
129 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
130 reference in CP0 move operand decoding.
132 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
134 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
136 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
138 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
140 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
141 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
142 "sync_rmb" and "sync_wmb" as aliases.
143 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
144 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
146 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
148 * arc-dis.c (parse_option): Update quarkse_em option..
149 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
151 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
153 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
155 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
157 2017-05-01 Michael Clark <michaeljclark@mac.com>
159 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
162 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
164 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
165 and branches and not synthetic data instructions.
167 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
169 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
171 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
173 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
174 * arc-opc.c (insert_r13el): New function.
176 * arc-tbl.h: Add new enter/leave variants.
178 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
180 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
182 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
184 * mips-dis.c (print_mips_disassembler_options): Add
187 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
189 * mips16-opc.c (AL): New macro.
190 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
191 of "ld" and "lw" as aliases.
193 2017-04-24 Tamar Christina <tamar.christina@arm.com>
195 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
198 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
199 Alan Modra <amodra@gmail.com>
201 * ppc-opc.c (ELEV): Define.
202 (vle_opcodes): Add se_rfgi and e_sc.
203 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
206 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
208 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
210 2017-04-21 Nick Clifton <nickc@redhat.com>
213 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
216 2017-04-13 Alan Modra <amodra@gmail.com>
218 * epiphany-desc.c: Regenerate.
219 * fr30-desc.c: Regenerate.
220 * frv-desc.c: Regenerate.
221 * ip2k-desc.c: Regenerate.
222 * iq2000-desc.c: Regenerate.
223 * lm32-desc.c: Regenerate.
224 * m32c-desc.c: Regenerate.
225 * m32r-desc.c: Regenerate.
226 * mep-desc.c: Regenerate.
227 * mt-desc.c: Regenerate.
228 * or1k-desc.c: Regenerate.
229 * xc16x-desc.c: Regenerate.
230 * xstormy16-desc.c: Regenerate.
232 2017-04-11 Alan Modra <amodra@gmail.com>
234 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
235 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
236 PPC_OPCODE_TMR for e6500.
237 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
238 (PPCVEC3): Define as PPC_OPCODE_POWER9.
239 (PPCVSX2): Define as PPC_OPCODE_POWER8.
240 (PPCVSX3): Define as PPC_OPCODE_POWER9.
241 (PPCHTM): Define as PPC_OPCODE_POWER8.
242 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
244 2017-04-10 Alan Modra <amodra@gmail.com>
246 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
247 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
248 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
249 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
251 2017-04-09 Pip Cet <pipcet@gmail.com>
253 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
254 appropriate floating-point precision directly.
256 2017-04-07 Alan Modra <amodra@gmail.com>
258 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
259 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
260 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
261 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
262 vector instructions with E6500 not PPCVEC2.
264 2017-04-06 Pip Cet <pipcet@gmail.com>
266 * Makefile.am: Add wasm32-dis.c.
267 * configure.ac: Add wasm32-dis.c to wasm32 target.
268 * disassemble.c: Add wasm32 disassembler code.
269 * wasm32-dis.c: New file.
270 * Makefile.in: Regenerate.
271 * configure: Regenerate.
272 * po/POTFILES.in: Regenerate.
273 * po/opcodes.pot: Regenerate.
275 2017-04-05 Pedro Alves <palves@redhat.com>
277 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
278 * arm-dis.c (parse_arm_disassembler_options): Constify.
279 * ppc-dis.c (powerpc_init_dialect): Constify local.
280 * vax-dis.c (parse_disassembler_options): Constify.
282 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
284 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
287 2017-03-30 Pip Cet <pipcet@gmail.com>
289 * configure.ac: Add (empty) bfd_wasm32_arch target.
290 * configure: Regenerate
291 * po/opcodes.pot: Regenerate.
293 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
295 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
297 * opcodes/sparc-opc.c (asi_table): New ASIs.
299 2017-03-29 Alan Modra <amodra@gmail.com>
301 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
303 (lookup_powerpc): Don't special case -1 dialect. Handle
305 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
306 lookup_powerpc call, pass it on second.
308 2017-03-27 Alan Modra <amodra@gmail.com>
311 * ppc-dis.c (struct ppc_mopt): Comment.
312 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
314 2017-03-27 Rinat Zelig <rinat@mellanox.com>
316 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
317 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
318 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
319 (insert_nps_misc_imm_offset): New function.
320 (extract_nps_misc imm_offset): New function.
321 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
322 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
324 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
326 * s390-mkopc.c (main): Remove vx2 check.
327 * s390-opc.txt: Remove vx2 instruction flags.
329 2017-03-21 Rinat Zelig <rinat@mellanox.com>
331 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
332 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
333 (insert_nps_imm_offset): New function.
334 (extract_nps_imm_offset): New function.
335 (insert_nps_imm_entry): New function.
336 (extract_nps_imm_entry): New function.
338 2017-03-17 Alan Modra <amodra@gmail.com>
341 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
342 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
343 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
345 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
347 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
351 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
353 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
355 2017-03-13 Andrew Waterman <andrew@sifive.com>
357 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
362 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
364 * i386-gen.c (opcode_modifiers): Replace S with Load.
365 * i386-opc.h (S): Removed.
367 (i386_opcode_modifier): Replace s with load.
368 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
369 and {evex}. Replace S with Load.
370 * i386-tbl.h: Regenerated.
372 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
374 * i386-opc.tbl: Use CpuCET on rdsspq.
375 * i386-tbl.h: Regenerated.
377 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
379 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
380 <vsx>: Do not use PPC_OPCODE_VSX3;
382 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
384 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
386 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
388 * i386-dis.c (REG_0F1E_MOD_3): New enum.
389 (MOD_0F1E_PREFIX_1): Likewise.
390 (MOD_0F38F5_PREFIX_2): Likewise.
391 (MOD_0F38F6_PREFIX_0): Likewise.
392 (RM_0F1E_MOD_3_REG_7): Likewise.
393 (PREFIX_MOD_0_0F01_REG_5): Likewise.
394 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
395 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
396 (PREFIX_0F1E): Likewise.
397 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
398 (PREFIX_0F38F5): Likewise.
399 (dis386_twobyte): Use PREFIX_0F1E.
400 (reg_table): Add REG_0F1E_MOD_3.
401 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
402 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
403 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
404 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
405 (three_byte_table): Use PREFIX_0F38F5.
406 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
407 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
408 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
409 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
410 PREFIX_MOD_3_0F01_REG_5_RM_2.
411 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
412 (cpu_flags): Add CpuCET.
413 * i386-opc.h (CpuCET): New enum.
414 (CpuUnused): Commented out.
415 (i386_cpu_flags): Add cpucet.
416 * i386-opc.tbl: Add Intel CET instructions.
417 * i386-init.h: Regenerated.
418 * i386-tbl.h: Likewise.
420 2017-03-06 Alan Modra <amodra@gmail.com>
423 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
424 (extract_raq, extract_ras, extract_rbx): New functions.
425 (powerpc_operands): Use opposite corresponding insert function.
427 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
428 register restriction.
430 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
432 * disassemble.c Include "safe-ctype.h".
433 (disassemble_init_for_target): Handle s390 init.
434 (remove_whitespace_and_extra_commas): New function.
435 (disassembler_options_cmp): Likewise.
436 * arm-dis.c: Include "libiberty.h".
438 (regnames): Use long disassembler style names.
439 Add force-thumb and no-force-thumb options.
440 (NUM_ARM_REGNAMES): Rename from this...
441 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
442 (get_arm_regname_num_options): Delete.
443 (set_arm_regname_option): Likewise.
444 (get_arm_regnames): Likewise.
445 (parse_disassembler_options): Likewise.
446 (parse_arm_disassembler_option): Rename from this...
447 (parse_arm_disassembler_options): ...to this. Make static.
448 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
449 (print_insn): Use parse_arm_disassembler_options.
450 (disassembler_options_arm): New function.
451 (print_arm_disassembler_options): Handle updated regnames.
452 * ppc-dis.c: Include "libiberty.h".
453 (ppc_opts): Add "32" and "64" entries.
454 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
455 (powerpc_init_dialect): Add break to switch statement.
456 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
457 (disassembler_options_powerpc): New function.
458 (print_ppc_disassembler_options): Use ARRAY_SIZE.
459 Remove printing of "32" and "64".
460 * s390-dis.c: Include "libiberty.h".
461 (init_flag): Remove unneeded variable.
462 (struct s390_options_t): New structure type.
463 (options): New structure.
464 (init_disasm): Rename from this...
465 (disassemble_init_s390): ...to this. Add initializations for
466 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
467 (print_insn_s390): Delete call to init_disasm.
468 (disassembler_options_s390): New function.
469 (print_s390_disassembler_options): Print using information from
471 * po/opcodes.pot: Regenerate.
473 2017-02-28 Jan Beulich <jbeulich@suse.com>
475 * i386-dis.c (PCMPESTR_Fixup): New.
476 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
477 (prefix_table): Use PCMPESTR_Fixup.
478 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
480 (vex_w_table): Delete VPCMPESTR{I,M} entries.
481 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
482 Split 64-bit and non-64-bit variants.
483 * opcodes/i386-tbl.h: Re-generate.
485 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
487 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
488 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
489 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
490 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
491 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
492 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
493 (OP_SVE_V_HSD): New macros.
494 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
495 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
496 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
497 (aarch64_opcode_table): Add new SVE instructions.
498 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
499 for rotation operands. Add new SVE operands.
500 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
501 (ins_sve_quad_index): Likewise.
502 (ins_imm_rotate): Split into...
503 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
504 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
505 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
507 (aarch64_ins_sve_addr_ri_s4): New function.
508 (aarch64_ins_sve_quad_index): Likewise.
509 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
510 * aarch64-asm-2.c: Regenerate.
511 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
512 (ext_sve_quad_index): Likewise.
513 (ext_imm_rotate): Split into...
514 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
515 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
516 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
518 (aarch64_ext_sve_addr_ri_s4): New function.
519 (aarch64_ext_sve_quad_index): Likewise.
520 (aarch64_ext_sve_index): Allow quad indices.
521 (do_misc_decoding): Likewise.
522 * aarch64-dis-2.c: Regenerate.
523 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
525 (OPD_F_OD_MASK): Widen by one bit.
526 (OPD_F_NO_ZR): Bump accordingly.
527 (get_operand_field_width): New function.
528 * aarch64-opc.c (fields): Add new SVE fields.
529 (operand_general_constraint_met_p): Handle new SVE operands.
530 (aarch64_print_operand): Likewise.
531 * aarch64-opc-2.c: Regenerate.
533 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
535 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
536 (aarch64_feature_compnum): ...this.
537 (SIMD_V8_3): Replace with...
539 (CNUM_INSN): New macro.
540 (aarch64_opcode_table): Use it for the complex number instructions.
542 2017-02-24 Jan Beulich <jbeulich@suse.com>
544 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
546 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
548 Add support for associating SPARC ASIs with an architecture level.
549 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
550 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
551 decoding of SPARC ASIs.
553 2017-02-23 Jan Beulich <jbeulich@suse.com>
555 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
556 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
558 2017-02-21 Jan Beulich <jbeulich@suse.com>
560 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
561 1 (instead of to itself). Correct typo.
563 2017-02-14 Andrew Waterman <andrew@sifive.com>
565 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
568 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
570 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
571 (aarch64_sys_reg_supported_p): Handle them.
573 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
575 * arc-opc.c (UIMM6_20R): Define.
576 (SIMM12_20): Use above.
577 (SIMM12_20R): Define.
578 (SIMM3_5_S): Use above.
579 (UIMM7_A32_11R_S): Define.
580 (UIMM7_9_S): Use above.
581 (UIMM3_13R_S): Define.
582 (SIMM11_A32_7_S): Use above.
584 (UIMM10_A32_8_S): Use above.
585 (UIMM8_8R_S): Define.
587 (arc_relax_opcodes): Use all above defines.
589 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
591 * arc-regs.h: Distinguish some of the registers different on
592 ARC700 and HS38 cpus.
594 2017-02-14 Alan Modra <amodra@gmail.com>
597 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
598 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
600 2017-02-11 Stafford Horne <shorne@gmail.com>
601 Alan Modra <amodra@gmail.com>
603 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
604 Use insn_bytes_value and insn_int_value directly instead. Don't
605 free allocated memory until function exit.
607 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
609 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
611 2017-02-03 Nick Clifton <nickc@redhat.com>
614 * aarch64-opc.c (print_register_list): Ensure that the register
615 list index will fir into the tb buffer.
616 (print_register_offset_address): Likewise.
617 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
619 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
622 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
623 instructions when the previous fetch packet ends with a 32-bit
626 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
628 * pru-opc.c: Remove vague reference to a future GDB port.
630 2017-01-20 Nick Clifton <nickc@redhat.com>
632 * po/ga.po: Updated Irish translation.
634 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
636 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
638 2017-01-13 Yao Qi <yao.qi@linaro.org>
640 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
641 if FETCH_DATA returns 0.
642 (m68k_scan_mask): Likewise.
643 (print_insn_m68k): Update code to handle -1 return value.
645 2017-01-13 Yao Qi <yao.qi@linaro.org>
647 * m68k-dis.c (enum print_insn_arg_error): New.
648 (NEXTBYTE): Replace -3 with
649 PRINT_INSN_ARG_MEMORY_ERROR.
650 (NEXTULONG): Likewise.
651 (NEXTSINGLE): Likewise.
652 (NEXTDOUBLE): Likewise.
653 (NEXTDOUBLE): Likewise.
654 (NEXTPACKED): Likewise.
655 (FETCH_ARG): Likewise.
656 (FETCH_DATA): Update comments.
657 (print_insn_arg): Update comments. Replace magic numbers with
659 (match_insn_m68k): Likewise.
661 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
663 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
664 * i386-dis-evex.h (evex_table): Updated.
665 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
666 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
667 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
668 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
669 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
670 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
671 * i386-init.h: Regenerate.
674 2017-01-12 Yao Qi <yao.qi@linaro.org>
676 * msp430-dis.c (msp430_singleoperand): Return -1 if
677 msp430dis_opcode_signed returns false.
678 (msp430_doubleoperand): Likewise.
679 (msp430_branchinstr): Return -1 if
680 msp430dis_opcode_unsigned returns false.
681 (msp430x_calla_instr): Likewise.
682 (print_insn_msp430): Likewise.
684 2017-01-05 Nick Clifton <nickc@redhat.com>
687 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
688 could not be matched.
689 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
692 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
694 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
695 (aarch64_opcode_table): Use RCPC_INSN.
697 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
699 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
701 * riscv-opcodes/all-opcodes: Likewise.
703 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
705 * riscv-dis.c (print_insn_args): Add fall through comment.
707 2017-01-03 Nick Clifton <nickc@redhat.com>
709 * po/sr.po: New Serbian translation.
710 * configure.ac (ALL_LINGUAS): Add sr.
711 * configure: Regenerate.
713 2017-01-02 Alan Modra <amodra@gmail.com>
715 * epiphany-desc.h: Regenerate.
716 * epiphany-opc.h: Regenerate.
717 * fr30-desc.h: Regenerate.
718 * fr30-opc.h: Regenerate.
719 * frv-desc.h: Regenerate.
720 * frv-opc.h: Regenerate.
721 * ip2k-desc.h: Regenerate.
722 * ip2k-opc.h: Regenerate.
723 * iq2000-desc.h: Regenerate.
724 * iq2000-opc.h: Regenerate.
725 * lm32-desc.h: Regenerate.
726 * lm32-opc.h: Regenerate.
727 * m32c-desc.h: Regenerate.
728 * m32c-opc.h: Regenerate.
729 * m32r-desc.h: Regenerate.
730 * m32r-opc.h: Regenerate.
731 * mep-desc.h: Regenerate.
732 * mep-opc.h: Regenerate.
733 * mt-desc.h: Regenerate.
734 * mt-opc.h: Regenerate.
735 * or1k-desc.h: Regenerate.
736 * or1k-opc.h: Regenerate.
737 * xc16x-desc.h: Regenerate.
738 * xc16x-opc.h: Regenerate.
739 * xstormy16-desc.h: Regenerate.
740 * xstormy16-opc.h: Regenerate.
742 2017-01-02 Alan Modra <amodra@gmail.com>
744 Update year range in copyright notice of all files.
746 For older changes see ChangeLog-2016
748 Copyright (C) 2017 Free Software Foundation, Inc.
750 Copying and distribution of this file, with or without modification,
751 are permitted in any medium without royalty provided the copyright
752 notice and this notice are preserved.
758 version-control: never