opcodes/ChangeLog

   1 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
   2
   3         * riscv-opc.c (riscv_opcodes): Change subset field
   4         to insn_class field for all instructions.
   5         (riscv_insn_types): Likewise.
   6
   7 2019-09-16  Phil Blundell  <pb@pbcl.net>
   8
   9         * configure: Regenerated.
  10
  11 2019-09-10  Miod Vallat  <miod@online.fr>
  12
  13         PR 24982
  14         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
  15
  16 2019-09-09  Phil Blundell  <pb@pbcl.net>
  17
  18         binutils 2.33 branch created.
  19
  20 2019-09-03  Nick Clifton  <nickc@redhat.com>
  21
  22         PR 24961
  23         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
  24         greater than zero before indexing via (bufcnt -1).
  25
  26 2019-09-03  Nick Clifton  <nickc@redhat.com>
  27
  28         PR 24958
  29         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
  30         (MAX_SPEC_REG_NAME_LEN): Define.
  31         (struct mmix_dis_info): Use defined constants for array lengths.
  32         (get_reg_name): New function.
  33         (get_sprec_reg_name): New function.
  34         (print_insn_mmix): Use new functions.
  35
  36 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
  37
  38         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
  39         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
  40         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
  41
  42 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
  43
  44         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
  45         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
  46         (aarch64_sys_reg_supported_p): Update checks for the above.
  47
  48 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
  49
  50         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
  51         cases MVE_SQRSHRL and MVE_UQRSHLL.
  52         (print_insn_mve): Add case for specifier 'k' to check
  53         specific bit of the instruction.
  54
  55 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
  56
  57         PR 24854
  58         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
  59         encountering an unknown machine type.
  60         (print_insn_arc): Handle arc_insn_length returning 0.  In error
  61         cases return -1 rather than calling abort.
  62
  63 2019-08-07  Jan Beulich  <jbeulich@suse.com>
  64
  65         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
  66         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
  67         IgnoreSize.
  68         * i386-tbl.h: Re-generate.
  69
  70 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
  71
  72         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
  73         instructions.
  74
  75 2019-07-30  Mel Chen <mel.chen@sifive.com>
  76
  77         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
  78         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
  79
  80         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
  81         fscsr.
  82
  83 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
  84
  85         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
  86         and MPY class instructions.
  87         (parse_option): Add nps400 option.
  88         (print_arc_disassembler_options): Add nps400 info.
  89
  90 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
  91
  92         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
  93         (bspop): Likewise.
  94         (modapp): Likewise.
  95         * arc-opc.c (RAD_CHK): Add.
  96         * arc-tbl.h: Regenerate.
  97
  98 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  99
 100         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 101         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 102
 103 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 104
 105         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 106         instructions as UNPREDICTABLE.
 107
 108 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 109
 110         * bpf-desc.c: Regenerated.
 111
 112 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 113
 114         * i386-gen.c (static_assert): Define.
 115         (main): Use it.
 116         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 117         (Opcode_Modifier_Num): ... this.
 118         (Mem): Delete.
 119
 120 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 121
 122         * i386-gen.c (operand_types): Move RegMem ...
 123         (opcode_modifiers): ... here.
 124         * i386-opc.h (RegMem): Move to opcode modifer enum.
 125         (union i386_operand_type): Move regmem field ...
 126         (struct i386_opcode_modifier): ... here.
 127         * i386-opc.tbl (RegMem): Define.
 128         (mov, movq): Move RegMem on segment, control, debug, and test
 129         register flavors.
 130         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 131         to non-SSE2AVX flavor.
 132         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 133         Move RegMem on register only flavors. Drop IgnoreSize from
 134         legacy encoding flavors.
 135         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 136         flavors.
 137         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 138         register only flavors.
 139         (vmovd): Move RegMem and drop IgnoreSize on register only
 140         flavor. Change opcode and operand order to store form.
 141         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 142
 143 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 144
 145         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 146         entries.
 147         * i386-opc.h (SReg2, SReg3): Replace by ...
 148         (SReg): ... this.
 149         (union i386_operand_type): Replace sreg fields.
 150         * i386-opc.tbl (mov, ): Use SReg.
 151         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 152         register flavors.
 153         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 154         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 155
 156 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 157
 158         * bpf-desc.c: Regenerate.
 159         * bpf-opc.c: Likewise.
 160         * bpf-opc.h: Likewise.
 161
 162 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 163
 164         * bpf-desc.c: Regenerate.
 165         * bpf-opc.c: Likewise.
 166
 167 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 168
 169         * arm-dis.c (print_insn_coprocessor): Rename index to
 170         index_operand.
 171
 172 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 173
 174         * riscv-opc.c (riscv_insn_types): Add r4 type.
 175
 176         * riscv-opc.c (riscv_insn_types): Add b and j type.
 177
 178         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 179         format for sb type and correct s type.
 180
 181 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 182
 183         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 184         SVE FMOV alias of FCPY.
 185
 186 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 187
 188         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 189         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 190
 191 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 192
 193         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 194         registers in an instruction prefixed by MOVPRFX.
 195
 196 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 197
 198         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 199         sve_size_13 icode to account for variant behaviour of
 200         pmull{t,b}.
 201         * aarch64-dis-2.c: Regenerate.
 202         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 203         sve_size_13 icode to account for variant behaviour of
 204         pmull{t,b}.
 205         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 206         (OP_SVE_VVV_Q_D): Add new qualifier.
 207         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 208         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 209         AES and those not.
 210
 211 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 212
 213         * opcodes/i386-gen.c (operand_type_init): Remove
 214         OPERAND_TYPE_VEC_IMM4 entry.
 215         (operand_types): Remove Vec_Imm4.
 216         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 217         (union i386_operand_type): Remove vec_imm4.
 218         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 219         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 220
 221 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 222
 223         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 224         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 225         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 226         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 227         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 228         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 229         * i386-tbl.h: Re-generate.
 230
 231 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 232
 233         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 234         register operands.
 235         * i386-tbl.h: Re-generate.
 236
 237 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 238
 239         * i386-opc.tbl (C): New.
 240         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 241         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 242         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 243         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 244         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 245         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 246         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 247         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 248         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 249         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 250         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 251         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 252         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 253         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 254         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 255         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 256         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 257         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 258         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 259         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 260         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 261         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 262         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 263         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 264         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 265         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 266         flavors.
 267         * i386-tbl.h: Re-generate.
 268
 269 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 270
 271         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 272         register operands.
 273         * i386-tbl.h: Re-generate.
 274
 275 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 276
 277         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 278         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 279         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 280         * i386-tbl.h: Re-generate.
 281
 282 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 283
 284         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 285         Disp8MemShift from register only templates.
 286         * i386-tbl.h: Re-generate.
 287
 288 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 289
 290         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 291         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 292         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 293         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 294         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 295         EVEX_W_0F11_P_3_M_1): Delete.
 296         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 297         EVEX_W_0F11_P_3): New.
 298         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 299         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 300         MOD_EVEX_0F11_PREFIX_3 table entries.
 301         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 302         PREFIX_EVEX_0F11 table entries.
 303         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 304         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 305         EVEX_W_0F11_P_3_M_{0,1} table entries.
 306
 307 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 308
 309         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 310         Delete.
 311
 312 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 313
 314         PR binutils/24719
 315         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 316         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 317         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 318         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 319         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 320         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 321         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 322         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 323         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 324         PREFIX_EVEX_0F38C6_REG_6 entries.
 325         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 326         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 327         EVEX_W_0F38C7_R_6_P_2 entries.
 328         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 329         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 330         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 331         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 332         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 333         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 334         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 335
 336 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 339         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 340         VEX_LEN_0F2D_P_3): Delete.
 341         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 342         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 343         (prefix_table): ... here.
 344
 345 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 346
 347         * i386-dis.c (Iq): Delete.
 348         (Id): New.
 349         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 350         TBM insns.
 351         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 352         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 353         (OP_E_memory): Also honor needindex when deciding whether an
 354         address size prefix needs printing.
 355         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 356
 357 2019-06-26  Jim Wilson  <jimw@sifive.com>
 358
 359         PR binutils/24739
 360         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 361         Set info->display_endian to info->endian_code.
 362
 363 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 364
 365         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 366         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 367         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 368         OPERAND_TYPE_ACC64 entries.
 369         * i386-init.h: Re-generate.
 370
 371 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 372
 373         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 374         Delete.
 375         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 376         of dqa_mode.
 377         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 378         entries here.
 379         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 380         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 381
 382 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 383
 384         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 385         variables.
 386
 387 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 388
 389         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 390         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 391         movnti.
 392         * i386-opc.tbl (movnti): Add IgnoreSize.
 393         * i386-tbl.h: Re-generate.
 394
 395 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 396
 397         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 398         * i386-tbl.h: Re-generate.
 399
 400 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 401
 402         * i386-dis-evex.h: Break into ...
 403         * i386-dis-evex-len.h: New file.
 404         * i386-dis-evex-mod.h: Likewise.
 405         * i386-dis-evex-prefix.h: Likewise.
 406         * i386-dis-evex-reg.h: Likewise.
 407         * i386-dis-evex-w.h: Likewise.
 408         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 409         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 410         i386-dis-evex-mod.h.
 411
 412 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 413
 414         PR binutils/24700
 415         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 416         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 417         EVEX_W_0F385B_P_2.
 418         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 419         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 420         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 421         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 422         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 423         EVEX_LEN_0F385B_P_2_W_1.
 424         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 425         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 426         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 427         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 428         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 429         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 430         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 431         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 432         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 433         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 434
 435 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 436
 437         PR binutils/24691
 438         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 439         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 440         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 441         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 442         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 443         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 444         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 445         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 446         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 447         EVEX_LEN_0F3A43_P_2_W_1.
 448         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 449         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 450         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 451         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 452         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 453         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 454         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 455         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 456         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 457         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 458         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 459         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 460
 461 2019-06-14  Nick Clifton  <nickc@redhat.com>
 462
 463         * po/fr.po; Updated French translation.
 464
 465 2019-06-13  Stafford Horne  <shorne@gmail.com>
 466
 467         * or1k-asm.c: Regenerated.
 468         * or1k-desc.c: Regenerated.
 469         * or1k-desc.h: Regenerated.
 470         * or1k-dis.c: Regenerated.
 471         * or1k-ibld.c: Regenerated.
 472         * or1k-opc.c: Regenerated.
 473         * or1k-opc.h: Regenerated.
 474         * or1k-opinst.c: Regenerated.
 475
 476 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 477
 478         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 479
 480 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 481
 482         PR binutils/24633
 483         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 484         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 485         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 486         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 487         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 488         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 489         EVEX_LEN_0F3A1B_P_2_W_1.
 490         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 491         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 492         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 493         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 494         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 495         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 496         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 497         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 498
 499 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 500
 501         PR binutils/24626
 502         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 503         EVEX.vvvv when disassembling VEX and EVEX instructions.
 504         (OP_VEX): Set vex.register_specifier to 0 after readding
 505         vex.register_specifier.
 506         (OP_Vex_2src_1): Likewise.
 507         (OP_Vex_2src_2): Likewise.
 508         (OP_LWP_E): Likewise.
 509         (OP_EX_Vex): Don't check vex.register_specifier.
 510         (OP_XMM_Vex): Likewise.
 511
 512 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 513             Lili Cui  <lili.cui@intel.com>
 514
 515         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 516         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 517         instructions.
 518         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 519         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 520         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 521         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 522         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 523         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 524         * i386-init.h: Regenerated.
 525         * i386-tbl.h: Likewise.
 526
 527 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 528             Lili Cui  <lili.cui@intel.com>
 529
 530         * doc/c-i386.texi: Document enqcmd.
 531         * testsuite/gas/i386/enqcmd-intel.d: New file.
 532         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 533         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 534         * testsuite/gas/i386/enqcmd.d: Likewise.
 535         * testsuite/gas/i386/enqcmd.s: Likewise.
 536         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 537         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 538         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 539         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 540         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 541         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 542         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 543         and x86-64-enqcmd.
 544
 545 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 546
 547         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 548
 549 2019-06-03  Alan Modra  <amodra@gmail.com>
 550
 551         * ppc-dis.c (prefix_opcd_indices): Correct size.
 552
 553 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 554
 555         PR gas/24625
 556         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 557         Disp8ShiftVL.
 558         * i386-tbl.h: Regenerated.
 559
 560 2019-05-24  Alan Modra  <amodra@gmail.com>
 561
 562         * po/POTFILES.in: Regenerate.
 563
 564 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 565             Alan Modra  <amodra@gmail.com>
 566
 567         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 568         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 569         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 570         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 571         XTOP>): Define and add entries.
 572         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 573         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 574         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 575         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 576
 577 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 578             Alan Modra  <amodra@gmail.com>
 579
 580         * ppc-dis.c (ppc_opts): Add "future" entry.
 581         (PREFIX_OPCD_SEGS): Define.
 582         (prefix_opcd_indices): New array.
 583         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 584         (lookup_prefix): New function.
 585         (print_insn_powerpc): Handle 64-bit prefix instructions.
 586         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 587         (PMRR, POWERXX): Define.
 588         (prefix_opcodes): New instruction table.
 589         (prefix_num_opcodes): New constant.
 590
 591 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 592
 593         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 594         * configure: Regenerated.
 595         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 596         and cpu/bpf.opc.
 597         (HFILES): Add bpf-desc.h and bpf-opc.h.
 598         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 599         bpf-ibld.c and bpf-opc.c.
 600         (BPF_DEPS): Define.
 601         * Makefile.in: Regenerated.
 602         * disassemble.c (ARCH_bpf): Define.
 603         (disassembler): Add case for bfd_arch_bpf.
 604         (disassemble_init_for_target): Likewise.
 605         (enum epbf_isa_attr): Define.
 606         * disassemble.h: extern print_insn_bpf.
 607         * bpf-asm.c: Generated.
 608         * bpf-opc.h: Likewise.
 609         * bpf-opc.c: Likewise.
 610         * bpf-ibld.c: Likewise.
 611         * bpf-dis.c: Likewise.
 612         * bpf-desc.h: Likewise.
 613         * bpf-desc.c: Likewise.
 614
 615 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 616
 617         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 618         and VMSR with the new operands.
 619
 620 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 621
 622         * arm-dis.c (enum mve_instructions): New enum
 623         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 624         and cneg.
 625         (mve_opcodes): New instructions as above.
 626         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 627         csneg and csel.
 628         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 629
 630 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 631
 632         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 633         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 634         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 635         uqshl, urshrl and urshr.
 636         (is_mve_okay_in_it): Add new instructions to TRUE list.
 637         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 638         (print_insn_mve): Updated to accept new %j,
 639         %<bitfield>m and %<bitfield>n patterns.
 640
 641 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 642
 643         * mips-opc.c (mips_builtin_opcodes): Change source register
 644         constraint for DAUI.
 645
 646 2019-05-20  Nick Clifton  <nickc@redhat.com>
 647
 648         * po/fr.po: Updated French translation.
 649
 650 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 651             Michael Collison <michael.collison@arm.com>
 652
 653         * arm-dis.c (thumb32_opcodes): Add new instructions.
 654         (enum mve_instructions): Likewise.
 655         (enum mve_undefined): Add new reasons.
 656         (is_mve_encoding_conflict): Handle new instructions.
 657         (is_mve_undefined): Likewise.
 658         (is_mve_unpredictable): Likewise.
 659         (print_mve_undefined): Likewise.
 660         (print_mve_size): Likewise.
 661
 662 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 663             Michael Collison <michael.collison@arm.com>
 664
 665         * arm-dis.c (thumb32_opcodes): Add new instructions.
 666         (enum mve_instructions): Likewise.
 667         (is_mve_encoding_conflict): Handle new instructions.
 668         (is_mve_undefined): Likewise.
 669         (is_mve_unpredictable): Likewise.
 670         (print_mve_size): Likewise.
 671
 672 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 673             Michael Collison <michael.collison@arm.com>
 674
 675         * arm-dis.c (thumb32_opcodes): Add new instructions.
 676         (enum mve_instructions): Likewise.
 677         (is_mve_encoding_conflict): Likewise.
 678         (is_mve_unpredictable): Likewise.
 679         (print_mve_size): Likewise.
 680
 681 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 682             Michael Collison <michael.collison@arm.com>
 683
 684         * arm-dis.c (thumb32_opcodes): Add new instructions.
 685         (enum mve_instructions): Likewise.
 686         (is_mve_encoding_conflict): Handle new instructions.
 687         (is_mve_undefined): Likewise.
 688         (is_mve_unpredictable): Likewise.
 689         (print_mve_size): Likewise.
 690
 691 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 692             Michael Collison <michael.collison@arm.com>
 693
 694         * arm-dis.c (thumb32_opcodes): Add new instructions.
 695         (enum mve_instructions): Likewise.
 696         (is_mve_encoding_conflict): Handle new instructions.
 697         (is_mve_undefined): Likewise.
 698         (is_mve_unpredictable): Likewise.
 699         (print_mve_size): Likewise.
 700         (print_insn_mve): Likewise.
 701
 702 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 703             Michael Collison <michael.collison@arm.com>
 704
 705         * arm-dis.c (thumb32_opcodes): Add new instructions.
 706         (print_insn_thumb32): Handle new instructions.
 707
 708 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 709             Michael Collison <michael.collison@arm.com>
 710
 711         * arm-dis.c (enum mve_instructions): Add new instructions.
 712         (enum mve_undefined): Add new reasons.
 713         (is_mve_encoding_conflict): Handle new instructions.
 714         (is_mve_undefined): Likewise.
 715         (is_mve_unpredictable): Likewise.
 716         (print_mve_undefined): Likewise.
 717         (print_mve_size): Likewise.
 718         (print_mve_shift_n): Likewise.
 719         (print_insn_mve): Likewise.
 720
 721 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 722             Michael Collison <michael.collison@arm.com>
 723
 724         * arm-dis.c (enum mve_instructions): Add new instructions.
 725         (is_mve_encoding_conflict): Handle new instructions.
 726         (is_mve_unpredictable): Likewise.
 727         (print_mve_rotate): Likewise.
 728         (print_mve_size): Likewise.
 729         (print_insn_mve): Likewise.
 730
 731 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 732             Michael Collison <michael.collison@arm.com>
 733
 734         * arm-dis.c (enum mve_instructions): Add new instructions.
 735         (is_mve_encoding_conflict): Handle new instructions.
 736         (is_mve_unpredictable): Likewise.
 737         (print_mve_size): Likewise.
 738         (print_insn_mve): Likewise.
 739
 740 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 741             Michael Collison <michael.collison@arm.com>
 742
 743         * arm-dis.c (enum mve_instructions): Add new instructions.
 744         (enum mve_undefined): Add new reasons.
 745         (is_mve_encoding_conflict): Handle new instructions.
 746         (is_mve_undefined): Likewise.
 747         (is_mve_unpredictable): Likewise.
 748         (print_mve_undefined): Likewise.
 749         (print_mve_size): Likewise.
 750         (print_insn_mve): Likewise.
 751
 752 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 753             Michael Collison <michael.collison@arm.com>
 754
 755         * arm-dis.c (enum mve_instructions): Add new instructions.
 756         (is_mve_encoding_conflict): Handle new instructions.
 757         (is_mve_undefined): Likewise.
 758         (is_mve_unpredictable): Likewise.
 759         (print_mve_size): Likewise.
 760         (print_insn_mve): Likewise.
 761
 762 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 763             Michael Collison <michael.collison@arm.com>
 764
 765         * arm-dis.c (enum mve_instructions): Add new instructions.
 766         (enum mve_unpredictable): Add new reasons.
 767         (enum mve_undefined): Likewise.
 768         (is_mve_okay_in_it): Handle new isntructions.
 769         (is_mve_encoding_conflict): Likewise.
 770         (is_mve_undefined): Likewise.
 771         (is_mve_unpredictable): Likewise.
 772         (print_mve_vmov_index): Likewise.
 773         (print_simd_imm8): Likewise.
 774         (print_mve_undefined): Likewise.
 775         (print_mve_unpredictable): Likewise.
 776         (print_mve_size): Likewise.
 777         (print_insn_mve): Likewise.
 778
 779 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 780             Michael Collison <michael.collison@arm.com>
 781
 782         * arm-dis.c (enum mve_instructions): Add new instructions.
 783         (enum mve_unpredictable): Add new reasons.
 784         (enum mve_undefined): Likewise.
 785         (is_mve_encoding_conflict): Handle new instructions.
 786         (is_mve_undefined): Likewise.
 787         (is_mve_unpredictable): Likewise.
 788         (print_mve_undefined): Likewise.
 789         (print_mve_unpredictable): Likewise.
 790         (print_mve_rounding_mode): Likewise.
 791         (print_mve_vcvt_size): Likewise.
 792         (print_mve_size): Likewise.
 793         (print_insn_mve): Likewise.
 794
 795 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 796             Michael Collison <michael.collison@arm.com>
 797
 798         * arm-dis.c (enum mve_instructions): Add new instructions.
 799         (enum mve_unpredictable): Add new reasons.
 800         (enum mve_undefined): Likewise.
 801         (is_mve_undefined): Handle new instructions.
 802         (is_mve_unpredictable): Likewise.
 803         (print_mve_undefined): Likewise.
 804         (print_mve_unpredictable): Likewise.
 805         (print_mve_size): Likewise.
 806         (print_insn_mve): Likewise.
 807
 808 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 809             Michael Collison <michael.collison@arm.com>
 810
 811         * arm-dis.c (enum mve_instructions): Add new instructions.
 812         (enum mve_undefined): Add new reasons.
 813         (insns): Add new instructions.
 814         (is_mve_encoding_conflict):
 815         (print_mve_vld_str_addr): New print function.
 816         (is_mve_undefined): Handle new instructions.
 817         (is_mve_unpredictable): Likewise.
 818         (print_mve_undefined): Likewise.
 819         (print_mve_size): Likewise.
 820         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 821         (print_insn_mve):  Handle new operands.
 822
 823 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 824             Michael Collison <michael.collison@arm.com>
 825
 826         * arm-dis.c (enum mve_instructions): Add new instructions.
 827         (enum mve_unpredictable): Add new reasons.
 828         (is_mve_encoding_conflict): Handle new instructions.
 829         (is_mve_unpredictable): Likewise.
 830         (mve_opcodes): Add new instructions.
 831         (print_mve_unpredictable): Handle new reasons.
 832         (print_mve_register_blocks): New print function.
 833         (print_mve_size): Handle new instructions.
 834         (print_insn_mve): Likewise.
 835
 836 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 837             Michael Collison <michael.collison@arm.com>
 838
 839         * arm-dis.c (enum mve_instructions): Add new instructions.
 840         (enum mve_unpredictable): Add new reasons.
 841         (enum mve_undefined): Likewise.
 842         (is_mve_encoding_conflict): Handle new instructions.
 843         (is_mve_undefined): Likewise.
 844         (is_mve_unpredictable): Likewise.
 845         (coprocessor_opcodes): Move NEON VDUP from here...
 846         (neon_opcodes): ... to here.
 847         (mve_opcodes): Add new instructions.
 848         (print_mve_undefined):  Handle new reasons.
 849         (print_mve_unpredictable): Likewise.
 850         (print_mve_size): Handle new instructions.
 851         (print_insn_neon): Handle vdup.
 852         (print_insn_mve): Handle new operands.
 853
 854 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 855             Michael Collison <michael.collison@arm.com>
 856
 857         * arm-dis.c (enum mve_instructions): Add new instructions.
 858         (enum mve_unpredictable): Add new values.
 859         (mve_opcodes): Add new instructions.
 860         (vec_condnames): New array with vector conditions.
 861         (mve_predicatenames): New array with predicate suffixes.
 862         (mve_vec_sizename): New array with vector sizes.
 863         (enum vpt_pred_state): New enum with vector predication states.
 864         (struct vpt_block): New struct type for vpt blocks.
 865         (vpt_block_state): Global struct to keep track of state.
 866         (mve_extract_pred_mask): New helper function.
 867         (num_instructions_vpt_block): Likewise.
 868         (mark_outside_vpt_block): Likewise.
 869         (mark_inside_vpt_block): Likewise.
 870         (invert_next_predicate_state): Likewise.
 871         (update_next_predicate_state): Likewise.
 872         (update_vpt_block_state): Likewise.
 873         (is_vpt_instruction): Likewise.
 874         (is_mve_encoding_conflict): Add entries for new instructions.
 875         (is_mve_unpredictable): Likewise.
 876         (print_mve_unpredictable): Handle new cases.
 877         (print_instruction_predicate): Likewise.
 878         (print_mve_size): New function.
 879         (print_vec_condition): New function.
 880         (print_insn_mve): Handle vpt blocks and new print operands.
 881
 882 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 883
 884         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 885         8, 14 and 15 for Armv8.1-M Mainline.
 886
 887 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 888             Michael Collison <michael.collison@arm.com>
 889
 890         * arm-dis.c (enum mve_instructions): New enum.
 891         (enum mve_unpredictable): Likewise.
 892         (enum mve_undefined): Likewise.
 893         (struct mopcode32): New struct.
 894         (is_mve_okay_in_it): New function.
 895         (is_mve_architecture): Likewise.
 896         (arm_decode_field): Likewise.
 897         (arm_decode_field_multiple): Likewise.
 898         (is_mve_encoding_conflict): Likewise.
 899         (is_mve_undefined): Likewise.
 900         (is_mve_unpredictable): Likewise.
 901         (print_mve_undefined): Likewise.
 902         (print_mve_unpredictable): Likewise.
 903         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 904         (print_insn_mve): New function.
 905         (print_insn_thumb32): Handle MVE architecture.
 906         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 907
 908 2019-05-10  Nick Clifton  <nickc@redhat.com>
 909
 910         PR 24538
 911         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 912         end of the table prematurely.
 913
 914 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 915
 916         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 917         macros for R6.
 918
 919 2019-05-11  Alan Modra  <amodra@gmail.com>
 920
 921         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 922         when -Mraw is in effect.
 923
 924 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 925
 926         * aarch64-dis-2.c: Regenerate.
 927         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 928         (OP_SVE_BBB): New variant set.
 929         (OP_SVE_DDDD): New variant set.
 930         (OP_SVE_HHH): New variant set.
 931         (OP_SVE_HHHU): New variant set.
 932         (OP_SVE_SSS): New variant set.
 933         (OP_SVE_SSSU): New variant set.
 934         (OP_SVE_SHH): New variant set.
 935         (OP_SVE_SBBU): New variant set.
 936         (OP_SVE_DSS): New variant set.
 937         (OP_SVE_DHHU): New variant set.
 938         (OP_SVE_VMV_HSD_BHS): New variant set.
 939         (OP_SVE_VVU_HSD_BHS): New variant set.
 940         (OP_SVE_VVVU_SD_BH): New variant set.
 941         (OP_SVE_VVVU_BHSD): New variant set.
 942         (OP_SVE_VVV_QHD_DBS): New variant set.
 943         (OP_SVE_VVV_HSD_BHS): New variant set.
 944         (OP_SVE_VVV_HSD_BHS2): New variant set.
 945         (OP_SVE_VVV_BHS_HSD): New variant set.
 946         (OP_SVE_VV_BHS_HSD): New variant set.
 947         (OP_SVE_VVV_SD): New variant set.
 948         (OP_SVE_VVU_BHS_HSD): New variant set.
 949         (OP_SVE_VZVV_SD): New variant set.
 950         (OP_SVE_VZVV_BH): New variant set.
 951         (OP_SVE_VZV_SD): New variant set.
 952         (aarch64_opcode_table): Add sve2 instructions.
 953
 954 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 955
 956         * aarch64-asm-2.c: Regenerated.
 957         * aarch64-dis-2.c: Regenerated.
 958         * aarch64-opc-2.c: Regenerated.
 959         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 960         for SVE_SHLIMM_UNPRED_22.
 961         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 962         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 963         operand.
 964
 965 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 966
 967         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 968         sve_size_tsz_bhs iclass encode.
 969         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 970         sve_size_tsz_bhs iclass decode.
 971
 972 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 973
 974         * aarch64-asm-2.c: Regenerated.
 975         * aarch64-dis-2.c: Regenerated.
 976         * aarch64-opc-2.c: Regenerated.
 977         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 978         for SVE_Zm4_11_INDEX.
 979         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 980         (fields): Handle SVE_i2h field.
 981         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 982         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 983
 984 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 985
 986         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 987         sve_shift_tsz_bhsd iclass encode.
 988         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 989         sve_shift_tsz_bhsd iclass decode.
 990
 991 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 992
 993         * aarch64-asm-2.c: Regenerated.
 994         * aarch64-dis-2.c: Regenerated.
 995         * aarch64-opc-2.c: Regenerated.
 996         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 997         (aarch64_encode_variant_using_iclass): Handle
 998         sve_shift_tsz_hsd iclass encode.
 999         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1000         sve_shift_tsz_hsd iclass decode.
1001         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1002         for SVE_SHRIMM_UNPRED_22.
1003         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1004         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1005         operand.
1006
1007 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1008
1009         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1010         sve_size_013 iclass encode.
1011         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1012         sve_size_013 iclass decode.
1013
1014 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1015
1016         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1017         sve_size_bh iclass encode.
1018         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1019         sve_size_bh iclass decode.
1020
1021 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1022
1023         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1024         sve_size_sd2 iclass encode.
1025         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1026         sve_size_sd2 iclass decode.
1027         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1028         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1029
1030 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1031
1032         * aarch64-asm-2.c: Regenerated.
1033         * aarch64-dis-2.c: Regenerated.
1034         * aarch64-opc-2.c: Regenerated.
1035         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1036         for SVE_ADDR_ZX.
1037         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1038         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1039
1040 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1041
1042         * aarch64-asm-2.c: Regenerated.
1043         * aarch64-dis-2.c: Regenerated.
1044         * aarch64-opc-2.c: Regenerated.
1045         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1046         for SVE_Zm3_11_INDEX.
1047         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1048         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1049         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1050         fields.
1051         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1052
1053 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1054
1055         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1056         sve_size_hsd2 iclass encode.
1057         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1058         sve_size_hsd2 iclass decode.
1059         * aarch64-opc.c (fields): Handle SVE_size field.
1060         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1061
1062 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1063
1064         * aarch64-asm-2.c: Regenerated.
1065         * aarch64-dis-2.c: Regenerated.
1066         * aarch64-opc-2.c: Regenerated.
1067         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1068         for SVE_IMM_ROT3.
1069         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1070         (fields): Handle SVE_rot3 field.
1071         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1072         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1073
1074 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1075
1076         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1077         instructions.
1078
1079 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1080
1081         * aarch64-tbl.h
1082         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1083         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1084         aarch64_feature_sve2bitperm): New feature sets.
1085         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1086         for feature set addresses.
1087         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1088         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1089
1090 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1091             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1092
1093         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1094         argument and set ASE_EVA_R6 appropriately.
1095         (set_default_mips_dis_options): Pass ISA to above.
1096         (parse_mips_dis_option): Likewise.
1097         * mips-opc.c (EVAR6): New macro.
1098         (mips_builtin_opcodes): Add llwpe, scwpe.
1099
1100 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1101
1102         * aarch64-asm-2.c: Regenerated.
1103         * aarch64-dis-2.c: Regenerated.
1104         * aarch64-opc-2.c: Regenerated.
1105         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1106         AARCH64_OPND_TME_UIMM16.
1107         (aarch64_print_operand): Likewise.
1108         * aarch64-tbl.h (QL_IMM_NIL): New.
1109         (TME): New.
1110         (_TME_INSN): New.
1111         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1112
1113 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1114
1115         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1116
1117 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1118             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1119
1120         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1121
1122 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1123
1124         * s12z-opc.h: Add extern "C" bracketing to help
1125         users who wish to use this interface in c++ code.
1126
1127 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1128
1129         * s12z-opc.c (bm_decode): Handle bit map operations with the
1130         "reserved0" mode.
1131
1132 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1133
1134         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1135         specifier.  Add entries for VLDR and VSTR of system registers.
1136         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1137         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1138         of %J and %K format specifier.
1139
1140 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1141
1142         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1143         Add new entries for VSCCLRM instruction.
1144         (print_insn_coprocessor): Handle new %C format control code.
1145
1146 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1147
1148         * arm-dis.c (enum isa): New enum.
1149         (struct sopcode32): New structure.
1150         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1151         set isa field of all current entries to ANY.
1152         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1153         Only match an entry if its isa field allows the current mode.
1154
1155 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1156
1157         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1158         CLRM.
1159         (print_insn_thumb32): Add logic to print %n CLRM register list.
1160
1161 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1162
1163         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1164         and %Q patterns.
1165
1166 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1167
1168         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1169         (print_insn_thumb32): Edit the switch case for %Z.
1170
1171 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1172
1173         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1174
1175 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1176
1177         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1178
1179 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1180
1181         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1182
1183 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1184
1185         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1186         Arm register with r13 and r15 unpredictable.
1187         (thumb32_opcodes): New instructions for bfx and bflx.
1188
1189 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1190
1191         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1192
1193 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1194
1195         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1196
1197 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1198
1199         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1200
1201 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1202
1203         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1204
1205 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1206
1207         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1208         "optr". ("operator" is a reserved word in c++).
1209
1210 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1211
1212         * aarch64-opc.c (aarch64_print_operand): Add case for
1213         AARCH64_OPND_Rt_SP.
1214         (verify_constraints): Likewise.
1215         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1216         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1217         to accept Rt|SP as first operand.
1218         (AARCH64_OPERANDS): Add new Rt_SP.
1219         * aarch64-asm-2.c: Regenerated.
1220         * aarch64-dis-2.c: Regenerated.
1221         * aarch64-opc-2.c: Regenerated.
1222
1223 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1224
1225         * aarch64-asm-2.c: Regenerated.
1226         * aarch64-dis-2.c: Likewise.
1227         * aarch64-opc-2.c: Likewise.
1228         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1229
1230 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1231
1232         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1233
1234 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1235
1236         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1237         * i386-init.h: Regenerated.
1238
1239 2019-04-07  Alan Modra  <amodra@gmail.com>
1240
1241         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1242         op_separator to control printing of spaces, comma and parens
1243         rather than need_comma, need_paren and spaces vars.
1244
1245 2019-04-07  Alan Modra  <amodra@gmail.com>
1246
1247         PR 24421
1248         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1249         (print_insn_neon, print_insn_arm): Likewise.
1250
1251 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1252
1253         * i386-dis-evex.h (evex_table): Updated to support BF16
1254         instructions.
1255         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1256         and EVEX_W_0F3872_P_3.
1257         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1258         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1259         * i386-opc.h (enum): Add CpuAVX512_BF16.
1260         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1261         * i386-opc.tbl: Add AVX512 BF16 instructions.
1262         * i386-init.h: Regenerated.
1263         * i386-tbl.h: Likewise.
1264
1265 2019-04-05  Alan Modra  <amodra@gmail.com>
1266
1267         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1268         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1269         to favour printing of "-" branch hint when using the "y" bit.
1270         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1271
1272 2019-04-05  Alan Modra  <amodra@gmail.com>
1273
1274         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1275         opcode until first operand is output.
1276
1277 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1278
1279         PR gas/24349
1280         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1281         (valid_bo_post_v2): Add support for 'at' branch hints.
1282         (insert_bo): Only error on branch on ctr.
1283         (get_bo_hint_mask): New function.
1284         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1285         for inserting 'at' branch hints.
1286         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1287         for extracting 'at' branch hints.
1288         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1289         (BOE): Delete operand.
1290         (BOM, BOP): New operands.
1291         (RM): Update value.
1292         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1293         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1294         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1295         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1296         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1297         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1298         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1299         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1300         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1301         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1302         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1303         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1304         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1305         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1306         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1307         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1308         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1309         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1310         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1311         bttarl+>: New extended mnemonics.
1312
1313 2019-03-28  Alan Modra  <amodra@gmail.com>
1314
1315         PR 24390
1316         * ppc-opc.c (BTF): Define.
1317         (powerpc_opcodes): Use for mtfsb*.
1318         * ppc-dis.c (print_insn_powerpc): Print fields with both
1319         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1320
1321 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1322
1323         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1324         (mapping_symbol_for_insn): Implement new algorithm.
1325         (print_insn): Remove duplicate code.
1326
1327 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1328
1329         * aarch64-dis.c (print_insn_aarch64):
1330         Implement override.
1331
1332 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1333
1334         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1335         order.
1336
1337 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1338
1339         * aarch64-dis.c (last_stop_offset): New.
1340         (print_insn_aarch64): Use stop_offset.
1341
1342 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1343
1344         PR gas/24359
1345         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1346         CPU_ANY_AVX2_FLAGS.
1347         * i386-init.h: Regenerated.
1348
1349 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1350
1351         PR gas/24348
1352         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1353         vmovdqu16, vmovdqu32 and vmovdqu64.
1354         * i386-tbl.h: Regenerated.
1355
1356 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1357
1358         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1359         from vstrszb, vstrszh, and vstrszf.
1360
1361 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1362
1363         * s390-opc.txt: Add instruction descriptions.
1364
1365 2019-02-08  Jim Wilson  <jimw@sifive.com>
1366
1367         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1368         <bne>: Likewise.
1369
1370 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1371
1372         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1373
1374 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1375
1376         PR binutils/23212
1377         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1378         * aarch64-opc.c (verify_elem_sd): New.
1379         (fields): Add FLD_sz entr.
1380         * aarch64-tbl.h (_SIMD_INSN): New.
1381         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1382         fmulx scalar and vector by element isns.
1383
1384 2019-02-07  Nick Clifton  <nickc@redhat.com>
1385
1386         * po/sv.po: Updated Swedish translation.
1387
1388 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1389
1390         * s390-mkopc.c (main): Accept arch13 as cpu string.
1391         * s390-opc.c: Add new instruction formats and instruction opcode
1392         masks.
1393         * s390-opc.txt: Add new arch13 instructions.
1394
1395 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1396
1397         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1398         (aarch64_opcode): Change encoding for stg, stzg
1399         st2g and st2zg.
1400         * aarch64-asm-2.c: Regenerated.
1401         * aarch64-dis-2.c: Regenerated.
1402         * aarch64-opc-2.c: Regenerated.
1403
1404 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1405
1406         * aarch64-asm-2.c: Regenerated.
1407         * aarch64-dis-2.c: Likewise.
1408         * aarch64-opc-2.c: Likewise.
1409         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1410
1411 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1412             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1413
1414         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1415         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1416         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1417         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1418         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1419         case for ldstgv_indexed.
1420         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1421         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1422         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1423         * aarch64-asm-2.c: Regenerated.
1424         * aarch64-dis-2.c: Regenerated.
1425         * aarch64-opc-2.c: Regenerated.
1426
1427 2019-01-23  Nick Clifton  <nickc@redhat.com>
1428
1429         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1430
1431 2019-01-21  Nick Clifton  <nickc@redhat.com>
1432
1433         * po/de.po: Updated German translation.
1434         * po/uk.po: Updated Ukranian translation.
1435
1436 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1437         * mips-dis.c (mips_arch_choices): Fix typo in
1438         gs464, gs464e and gs264e descriptors.
1439
1440 2019-01-19  Nick Clifton  <nickc@redhat.com>
1441
1442         * configure: Regenerate.
1443         * po/opcodes.pot: Regenerate.
1444
1445 2018-06-24  Nick Clifton  <nickc@redhat.com>
1446
1447         2.32 branch created.
1448
1449 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1450
1451         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1452         if it is null.
1453         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1454         zero.
1455
1456 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1457
1458         * configure: Regenerate.
1459
1460 2019-01-07  Alan Modra  <amodra@gmail.com>
1461
1462         * configure: Regenerate.
1463         * po/POTFILES.in: Regenerate.
1464
1465 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1466
1467         * s12z-opc.c: New file.
1468         * s12z-opc.h: New file.
1469         * s12z-dis.c: Removed all code not directly related to display
1470         of instructions.  Used the interface provided by the new files
1471         instead.
1472         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1473         * Makefile.in: Regenerate.
1474         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1475         * configure: Regenerate.
1476
1477 2019-01-01  Alan Modra  <amodra@gmail.com>
1478
1479         Update year range in copyright notice of all files.
1480
1481 For older changes see ChangeLog-2018
1482 \f
1483 Copyright (C) 2019 Free Software Foundation, Inc.
1484
1485 Copying and distribution of this file, with or without modification,
1486 are permitted in any medium without royalty provided the copyright
1487 notice and this notice are preserved.
1488
1489 Local Variables:
1490 mode: change-log
1491 left-margin: 8
1492 fill-column: 74
1493 version-control: never
1494 End: