opcodes/ChangeLog

   1 2011-11-29  Andrew Pinski  <apinski@cavium.com>
   2
   3         * mips-dis.c (mips_arch_choices): Add Octeon+.
   4         * mips-opc.c (IOCT): Include Octeon+.
   5         (IOCTP): New macro.
   6         (mips_builtin_opcodes): Add "saa" and "saad".
   7
   8 2011-11-25  Pierre Muller  <muller@ics.u-strasbg.fr>
   9
  10         * mips-dis.c (print_insn_micromips): Rename local variable iprintf
  11         to infprintf to avoid shadow warning.
  12
  13 2011-11-25  Nick Clifton  <nickc@redhat.com>
  14
  15         * po/it.po: Updated Italian translation.
  16
  17 2011-11-16  Maciej W. Rozycki  <macro@codesourcery.com>
  18
  19         * micromips-opc.c (micromips_opcodes): Use NODS rather than TRAP
  20         for "alnv.ps".
  21
  22 2011-11-02  Nick Clifton  <nickc@redhat.com>
  23
  24         * po/it.po: New Italian translation.
  25         * configure.in (ALL_LINGUAS): Add it.
  26         * configure: Regenerate.
  27         * po/opcodes.pot: Regenerate.
  28
  29 2011-11-01  DJ Delorie  <dj@redhat.com>
  30
  31         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
  32         rl78-dis.c.
  33         (MAINTAINERCLEANFILES): Add rl78-decode.c.
  34         (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
  35         * Makefile.in: Regenerate.
  36         * configure.in: Add bfd_rl78_arch case.
  37         * configure: Regenerate.
  38         * disassemble.c: Define ARCH_rl78.
  39         (disassembler): Add ARCH_rl78 case.
  40         * rl78-decode.c: New file.
  41         * rl78-decode.opc: New file.
  42         * rl78-dis.c: New file.
  43
  44 2011-10-27  Peter Bergner  <bergner@vnet.ibm.com>
  45
  46         * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
  47         dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
  48         diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
  49         instructions.
  50
  51 2011-10-26  Nick Clifton  <nickc@redhat.com>
  52
  53         PR binutils/13348
  54         * i386-dis.c (print_insn): Fix testing of array subscript.
  55
  56 2011-10-26  Joern Rennecke  <joern.rennecke@embecosm.com>
  57
  58         * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
  59         * epiphany-asm.c, epiphany-opc.h: Regenerate.
  60
  61 2011-10-25  Joern Rennecke  <joern.rennecke@embecosm.com>
  62
  63         * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
  64         (TARGET_LIBOPCODES_CFILES): Add  epiphany-asm.c, epiphany-desc.c,
  65         epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
  66         (CLEANFILES): Add stamp-epiphany.
  67         (EPIPHANY_DEPS): Set.  Make CGEN-generated Epiphany files depend on it.
  68         (stamp-epiphany): New rule.
  69         * configure.in: Handle bfd_epiphany_arch.
  70         * disassemble.c (ARCH_epiphany): Define.
  71         (disassembler): Handle bfd_arch_epiphany.
  72         * epiphany-asm.c: New file.
  73         * epiphany-desc.c: New file.
  74         * epiphany-desc.h: New file.
  75         * epiphany-dis.c: New file.
  76         * epiphany-ibld.c: New file.
  77         * epiphany-opc.c: New file.
  78         * epiphany-opc.h: New file.
  79         * Makefile.in: Regenerate.
  80         * configure: Regenerate.
  81         * po/POTFILES.in: Regenerate.
  82         * po/opcodes.pot: Regenerate.
  83
  84 2011-10-24  Julian Brown  <julian@codesourcery.com>
  85
  86         * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
  87
  88 2011-10-21  Jan Glauber  <jang@linux.vnet.ibm.com>
  89
  90         * s390-opc.txt: Add CPUMF instructions.
  91
  92 2011-10-18  Jie Zhang  <jie@codesourcery.com>
  93             Julian Brown  <julian@codesourcery.com>
  94
  95         * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
  96
  97 2011-10-10  Nick Clifton  <nickc@redhat.com>
  98
  99         * po/es.po: Updated Spanish translation.
 100         * po/fi.po: Updated Finnish translation.
 101
 102 2011-09-28  Jan Beulich  <jbeulich@suse.com>
 103
 104         * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
 105         RBX): New.
 106         (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
 107         (powerpc_opcodes): Use RAX for second and RBXC for third operand of
 108         lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
 109         lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
 110         mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
 111         on DFP quad instructions.
 112
 113 2011-09-27  David S. Miller  <davem@davemloft.net>
 114
 115         * sparc-opc.c (sparc_opcodes): Fix random instruction to write
 116         to a float instead of an integer register.
 117
 118 2011-09-26  David S. Miller  <davem@davemloft.net>
 119
 120         * sparc-opc.c (sparc_opcodes): Add integer multiply-add
 121         instructions.
 122
 123 2011-09-21  David S. Miller  <davem@davemloft.net>
 124
 125         * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
 126         bits.  Fix "fchksm16" mnemonic.
 127
 128 2011-09-08  Mark Fortescue <mark@mtfhpc.demon.co.uk>
 129
 130         The changes below bring 'mov' and 'ticc' instructions into line
 131         with the V8 SPARC Architecture Manual.
 132         * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
 133         * sparc-opc.c (sparc_opcodes): Add alias entries for
 134         'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
 135         'mov regrs2,%wim' and 'mov regrs2,%tbr'.
 136         * sparc-opc.c (sparc_opcodes): Move/Change entries for
 137         'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
 138         and 'mov imm,%tbr'.
 139         * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
 140         mov aliases.
 141
 142         * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
 143         This has been reported as being accepted by the Sun assmebler.
 144
 145 2011-09-08  David S. Miller  <davem@davemloft.net>
 146
 147         * sparc-opc.c (pdistn): Destination is integer not float register.
 148
 149 2011-09-07  Andreas Schwab  <schwab@linux-m68k.org>
 150
 151         PR gas/13145
 152         * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
 153
 154 2011-08-26  Nick Clifton  <nickc@redhat.com>
 155
 156         * po/es.po: Updated Spanish translation.
 157
 158 2011-08-22  Nick Clifton  <nickc@redhat.com>
 159
 160         * Makefile.am (CPUDIR): Redfine to point to top level cpu
 161         directory.
 162         (stamp-frv): Use CPUDIR.
 163         (stamp-iq2000): Likewise.
 164         (stamp-lm32): Likewise.
 165         (stamp-m32c): Likewise.
 166         (stamp-mt): Likewise.
 167         (stamp-xc16x): Likewise.
 168         * Makefile.in: Regenerate.
 169
 170 2011-08-09  Chao-ying Fu  <fu@mips.com>
 171             Maciej W. Rozycki  <macro@codesourcery.com>
 172
 173         * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
 174         and "mips64r2".
 175         (print_insn_args, print_insn_micromips): Handle MCU.
 176         * micromips-opc.c (MC): New macro.
 177         (micromips_opcodes): Add "aclr", "aset" and "iret".
 178         * mips-opc.c (MC): New macro.
 179         (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
 180
 181 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 182
 183         * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
 184         (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
 185         (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
 186         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
 187         (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
 188         (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
 189         (WR_s): Update macro.
 190         (micromips_opcodes): Update register use flags of: "addiu",
 191         "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
 192         "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
 193         "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
 194         "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
 195         "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
 196         "swm" and "xor" instructions.
 197
 198 2011-08-05  David S. Miller  <davem@davemloft.net>
 199
 200         * sparc-dis.c (v9a_ast_reg_names): Add "cps".
 201         (X_RS3): New macro.
 202         (print_insn_sparc): Handle '4', '5', and '(' format codes.
 203         Accept %asr numbers below 28.
 204         * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
 205         instructions.
 206
 207 2011-08-02  Quentin Neill  <quentin.neill@amd.com>
 208
 209         * i386-dis.c (xop_table): Remove spurious bextr insn.
 210
 211 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 212
 213         PR ld/13048
 214         * i386-dis.c (print_insn): Optimize info->mach check.
 215
 216 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 217
 218         PR gas/13046
 219         * i386-opc.tbl: Add Disp32S to 64bit call.
 220         * i386-tbl.h: Regenerated.
 221
 222 2011-07-24  Chao-ying Fu  <fu@mips.com>
 223             Maciej W. Rozycki  <macro@codesourcery.com>
 224
 225         * micromips-opc.c: New file.
 226         * mips-dis.c (micromips_to_32_reg_b_map): New array.
 227         (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
 228         (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
 229         (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
 230         (micromips_to_32_reg_q_map): Likewise.
 231         (micromips_imm_b_map, micromips_imm_c_map): Likewise.
 232         (micromips_ase): New variable.
 233         (is_micromips): New function.
 234         (set_default_mips_dis_options): Handle microMIPS ASE.
 235         (print_insn_micromips): New function.
 236         (is_compressed_mode_p): Likewise.
 237         (_print_insn_mips): Handle microMIPS instructions.
 238         * Makefile.am (CFILES): Add micromips-opc.c.
 239         * configure.in (bfd_mips_arch): Add micromips-opc.lo.
 240         * Makefile.in: Regenerate.
 241         * configure: Regenerate.
 242
 243         * mips-dis.c (micromips_to_32_reg_h_map): New variable.
 244         (micromips_to_32_reg_i_map): Likewise.
 245         (micromips_to_32_reg_m_map): Likewise.
 246         (micromips_to_32_reg_n_map): New macro.
 247
 248 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 249
 250         * mips-opc.c (NODS): New macro.
 251         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 252         (DSP_VOLA): Likewise.
 253         (mips_builtin_opcodes): Add NODS annotation to "deret" and
 254         "eret". Replace INSN_SYNC with NODS throughout.  Use NODS in
 255         place of TRAP for "wait", "waiti" and "yield".
 256         * mips16-opc.c (NODS): New macro.
 257         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 258         (mips16_opcodes):  Use NODS in place of TRAP for "jalrc", "jrc",
 259         "restore" and "save".
 260
 261 2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 262
 263         * configure.in: Handle bfd_k1om_arch.
 264         * configure: Regenerated.
 265
 266         * disassemble.c (disassembler): Handle bfd_k1om_arch.
 267
 268         * i386-dis.c (print_insn): Handle bfd_mach_k1om and
 269         bfd_mach_k1om_intel_syntax.
 270
 271         * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
 272         ~(CpuL1OM|CpuK1OM).  Add CPU_K1OM_FLAGS.
 273         (cpu_flags): Add CpuK1OM.
 274
 275         * i386-opc.h (CpuK1OM): New.
 276         (i386_cpu_flags): Add cpuk1om.
 277
 278         * i386-init.h: Regenerated.
 279         * i386-tbl.h: Likewise.
 280
 281 2011-07-12  Nick Clifton  <nickc@redhat.com>
 282
 283         * arm-dis.c (print_insn_arm): Revert previous, undocumented,
 284         accidental change.
 285
 286 2011-07-01  Nick Clifton  <nickc@redhat.com>
 287
 288         PR binutils/12329
 289         * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
 290         insns using post-increment addressing.
 291
 292 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 293
 294         * i386-dis.c (vex_len_table): Update rorxS.
 295
 296 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 297
 298         AVX Programming Reference (June, 2011)
 299         * i386-dis.c (vex_len_table): Correct rorxS.
 300
 301         * i386-opc.tbl: Correct rorx.
 302         * i386-tbl.h: Regenerated.
 303
 304 2011-06-29  H.J. Lu  <hongjiu.lu@intel.com>
 305
 306         * tilegx-opc.c (find_opcode): Replace "index" with "i".
 307         * tilepro-opc.c (find_opcode): Likewise.
 308
 309 2011-06-29  Richard Sandiford  <rdsandiford@googlemail.com>
 310
 311         * mips16-opc.c (jalrc, jrc): Move earlier in file.
 312
 313 2011-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 314
 315         * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
 316         PREFIX_VEX_0F388E.
 317
 318 2011-06-17  Andreas Schwab  <schwab@redhat.com>
 319
 320         * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
 321         (MOSTLYCLEANFILES): ... here.
 322         * Makefile.in: Regenerate.
 323
 324 2011-06-14  Alan Modra  <amodra@gmail.com>
 325
 326         * Makefile.in: Regenerate.
 327
 328 2011-06-13  Walter Lee  <walt@tilera.com>
 329
 330         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
 331         tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
 332         * Makefile.in: Regenerate.
 333         * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
 334         * configure: Regenerate.
 335         * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
 336         * po/POTFILES.in: Regenerate.
 337         * tilegx-dis.c: New file.
 338         * tilegx-opc.c: New file.
 339         * tilepro-dis.c: New file.
 340         * tilepro-opc.c: New file.
 341
 342 2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 343
 344         AVX Programming Reference (June, 2011)
 345         * i386-dis.c (XMGatherQ): New.
 346         * i386-dis.c (EXxmm_mb): New.
 347         (EXxmm_mb): Likewise.
 348         (EXxmm_mw): Likewise.
 349         (EXxmm_md): Likewise.
 350         (EXxmm_mq): Likewise.
 351         (EXxmmdw): Likewise.
 352         (EXxmmqd): Likewise.
 353         (VexGatherQ): Likewise.
 354         (MVexVSIBDWpX): Likewise.
 355         (MVexVSIBQWpX): Likewise.
 356         (xmm_mb_mode): Likewise.
 357         (xmm_mw_mode): Likewise.
 358         (xmm_md_mode): Likewise.
 359         (xmm_mq_mode): Likewise.
 360         (xmmdw_mode): Likewise.
 361         (xmmqd_mode): Likewise.
 362         (ymmxmm_mode): Likewise.
 363         (vex_vsib_d_w_dq_mode): Likewise.
 364         (vex_vsib_q_w_dq_mode): Likewise.
 365         (MOD_VEX_0F385A_PREFIX_2): Likewise.
 366         (MOD_VEX_0F388C_PREFIX_2): Likewise.
 367         (MOD_VEX_0F388E_PREFIX_2): Likewise.
 368         (PREFIX_0F3882): Likewise.
 369         (PREFIX_VEX_0F3816): Likewise.
 370         (PREFIX_VEX_0F3836): Likewise.
 371         (PREFIX_VEX_0F3845): Likewise.
 372         (PREFIX_VEX_0F3846): Likewise.
 373         (PREFIX_VEX_0F3847): Likewise.
 374         (PREFIX_VEX_0F3858): Likewise.
 375         (PREFIX_VEX_0F3859): Likewise.
 376         (PREFIX_VEX_0F385A): Likewise.
 377         (PREFIX_VEX_0F3878): Likewise.
 378         (PREFIX_VEX_0F3879): Likewise.
 379         (PREFIX_VEX_0F388C): Likewise.
 380         (PREFIX_VEX_0F388E): Likewise.
 381         (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
 382         (PREFIX_VEX_0F38F5): Likewise.
 383         (PREFIX_VEX_0F38F6): Likewise.
 384         (PREFIX_VEX_0F3A00): Likewise.
 385         (PREFIX_VEX_0F3A01): Likewise.
 386         (PREFIX_VEX_0F3A02): Likewise.
 387         (PREFIX_VEX_0F3A38): Likewise.
 388         (PREFIX_VEX_0F3A39): Likewise.
 389         (PREFIX_VEX_0F3A46): Likewise.
 390         (PREFIX_VEX_0F3AF0): Likewise.
 391         (VEX_LEN_0F3816_P_2): Likewise.
 392         (VEX_LEN_0F3819_P_2): Likewise.
 393         (VEX_LEN_0F3836_P_2): Likewise.
 394         (VEX_LEN_0F385A_P_2_M_0): Likewise.
 395         (VEX_LEN_0F38F5_P_0): Likewise.
 396         (VEX_LEN_0F38F5_P_1): Likewise.
 397         (VEX_LEN_0F38F5_P_3): Likewise.
 398         (VEX_LEN_0F38F6_P_3): Likewise.
 399         (VEX_LEN_0F38F7_P_1): Likewise.
 400         (VEX_LEN_0F38F7_P_2): Likewise.
 401         (VEX_LEN_0F38F7_P_3): Likewise.
 402         (VEX_LEN_0F3A00_P_2): Likewise.
 403         (VEX_LEN_0F3A01_P_2): Likewise.
 404         (VEX_LEN_0F3A38_P_2): Likewise.
 405         (VEX_LEN_0F3A39_P_2): Likewise.
 406         (VEX_LEN_0F3A46_P_2): Likewise.
 407         (VEX_LEN_0F3AF0_P_3): Likewise.
 408         (VEX_W_0F3816_P_2): Likewise.
 409         (VEX_W_0F3818_P_2): Likewise.
 410         (VEX_W_0F3819_P_2): Likewise.
 411         (VEX_W_0F3836_P_2): Likewise.
 412         (VEX_W_0F3846_P_2): Likewise.
 413         (VEX_W_0F3858_P_2): Likewise.
 414         (VEX_W_0F3859_P_2): Likewise.
 415         (VEX_W_0F385A_P_2_M_0): Likewise.
 416         (VEX_W_0F3878_P_2): Likewise.
 417         (VEX_W_0F3879_P_2): Likewise.
 418         (VEX_W_0F3A00_P_2): Likewise.
 419         (VEX_W_0F3A01_P_2): Likewise.
 420         (VEX_W_0F3A02_P_2): Likewise.
 421         (VEX_W_0F3A38_P_2): Likewise.
 422         (VEX_W_0F3A39_P_2): Likewise.
 423         (VEX_W_0F3A46_P_2): Likewise.
 424         (MOD_VEX_0F3818_PREFIX_2): Removed.
 425         (MOD_VEX_0F3819_PREFIX_2): Likewise.
 426         (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
 427         (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
 428         (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
 429         (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
 430         (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
 431         (VEX_LEN_0F3A0E_P_2): Likewise.
 432         (VEX_LEN_0F3A0F_P_2): Likewise.
 433         (VEX_LEN_0F3A42_P_2): Likewise.
 434         (VEX_LEN_0F3A4C_P_2): Likewise.
 435         (VEX_W_0F3818_P_2_M_0): Likewise.
 436         (VEX_W_0F3819_P_2_M_0): Likewise.
 437         (prefix_table): Updated.
 438         (three_byte_table): Likewise.
 439         (vex_table): Likewise.
 440         (vex_len_table): Likewise.
 441         (vex_w_table): Likewise.
 442         (mod_table): Likewise.
 443         (putop): Handle "LW".
 444         (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
 445         xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
 446         vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
 447         (OP_EX): Likewise.
 448         (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
 449         vex_vsib_q_w_dq_mode.
 450         (OP_XMM): Handle vex_vsib_q_w_dq_mode.
 451         (OP_VEX): Likewise.
 452
 453         * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
 454         and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
 455         CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
 456         (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
 457         (opcode_modifiers): Add VecSIB.
 458
 459         * i386-opc.h (CpuAVX2): New.
 460         (CpuBMI2): Likewise.
 461         (CpuLZCNT): Likewise.
 462         (CpuINVPCID): Likewise.
 463         (VecSIB128): Likewise.
 464         (VecSIB256): Likewise.
 465         (VecSIB): Likewise.
 466         (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
 467         (i386_opcode_modifier): Add vecsib.
 468
 469         * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
 470         * i386-init.h: Regenerated.
 471         * i386-tbl.h: Likewise.
 472
 473 2011-06-03  Quentin Neill  <quentin.neill@amd.com>
 474
 475         * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
 476         * i386-init.h: Regenerated.
 477
 478 2011-06-03  Nick Clifton  <nickc@redhat.com>
 479
 480         PR binutils/12752
 481         * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
 482         computing address offsets.
 483         (print_arm_address): Likewise.
 484         (print_insn_arm): Likewise.
 485         (print_insn_thumb16): Likewise.
 486         (print_insn_thumb32): Likewise.
 487
 488 2011-06-02  Jie Zhang <jie@codesourcery.com>
 489             Nathan Sidwell <nathan@codesourcery.com>
 490             Maciej Rozycki <macro@codesourcery.com>
 491
 492         * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
 493         as address offset.
 494         (print_arm_address): Likewise. Elide positive #0 appropriately.
 495         (print_insn_arm): Likewise.
 496
 497 2011-06-02  Nick Clifton  <nickc@redhat.com>
 498
 499         PR gas/12752
 500         * arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
 501         passed to print_address_func.
 502
 503 2011-06-02  Nick Clifton  <nickc@redhat.com>
 504
 505         * arm-dis.c: Fix spelling mistakes.
 506         * op/opcodes.pot: Regenerate.
 507
 508 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 509
 510         * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
 511         S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
 512         * s390-opc.txt: Fix cxr instruction type.
 513
 514 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 515
 516         * s390-opc.c: Add new instruction types marking register pair
 517         operands.
 518         * s390-opc.txt: Match instructions having register pair operands
 519         to the new instruction types.
 520
 521 2011-05-19  Nick Clifton  <nickc@redhat.com>
 522
 523         * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
 524         operands.
 525
 526 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
 527
 528         * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
 529         * i386-init.h: Regenerated.
 530
 531 2011-04-27  Nick Clifton  <nickc@redhat.com>
 532
 533         * po/da.po: Updated Danish translation.
 534
 535 2011-04-26  Anton Blanchard  <anton@samba.org>
 536
 537         * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
 538
 539 2011-04-21  DJ Delorie  <dj@redhat.com>
 540
 541         * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
 542         * rx-decode.c: Regenerate.
 543
 544 2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 545
 546         * i386-init.h: Regenerated.
 547
 548 2011-04-19  Quentin Neill  <quentin.neill@amd.com>
 549
 550         * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
 551         from bdver1 flags.
 552
 553 2011-04-13  Nick Clifton  <nickc@redhat.com>
 554
 555         * v850-dis.c (disassemble): Always print a closing square brace if
 556         an opening square brace was printed.
 557
 558 2011-04-12  Nick Clifton  <nickc@redhat.com>
 559
 560         PR binutils/12534
 561         * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
 562         patterns.
 563         (print_insn_thumb32): Handle %L.
 564
 565 2011-04-11  Julian Brown  <julian@codesourcery.com>
 566
 567         * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
 568         (print_insn_thumb32): Add APSR bitmask support.
 569
 570 2011-04-07  Paul Carroll<pcarroll@codesourcery.com>
 571
 572         * arm-dis.c (print_insn): init vars moved into private_data structure.
 573
 574 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 575
 576         * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
 577
 578 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 579
 580         * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
 581         post-increment to support LPM Z+ instruction. Add support for 'E'
 582         constraint for DES instruction.
 583         (print_insn_avr): Adjust calls to avr_operand. Rename variable.
 584
 585 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 586
 587         * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
 588
 589 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 590
 591         * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
 592         Use branch types instead.
 593         (print_insn): Likewise.
 594
 595 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 596
 597         * mips-opc.c (mips_builtin_opcodes): Correct register use
 598         annotation of "alnv.ps".
 599
 600 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 601
 602         * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 603
 604 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 605
 606         * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
 607
 608 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 609
 610         * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
 611
 612 2011-02-19  Mike Frysinger  <vapier@gentoo.org>
 613
 614         * bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
 615         a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
 616         av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
 617         exception, end_of_registers, msize, memory, bfd_mach.
 618         (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
 619         LB0REG, LC1REG, LT1REG, LB1REG): Delete
 620         (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
 621         (get_allreg): Change to new defines.  Fallback to abort().
 622
 623 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 624
 625         * bfin-dis.c: Add whitespace/parenthesis where needed.
 626
 627 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 628
 629         * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
 630         than 7.
 631
 632 2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 633
 634         * configure: Regenerate.
 635
 636 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 637
 638         * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
 639
 640 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 641
 642         * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
 643         dregs only when P is set, and dregs_lo otherwise.
 644
 645 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 646
 647         * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
 648
 649 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 650
 651         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
 652
 653 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 654
 655         * bfin-dis.c (machine_registers): Delete REG_GP.
 656         (reg_names): Delete "GP".
 657         (decode_allregs): Change REG_GP to REG_LASTREG.
 658
 659 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 660
 661         * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
 662         M_IH, M_IU): Delete.
 663
 664 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 665
 666         * bfin-dis.c (reg_names): Add const.
 667         (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
 668         decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
 669         decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
 670         decode_counters, decode_allregs): Likewise.
 671
 672 2011-02-09  Michael Snyder  <msnyder@vmware.com>
 673
 674         * i386-dis.c (OP_J): Parenthesize expression to prevent
 675         truncated addresses.
 676         (print_insn): Fix indentation off-by-one.
 677
 678 2011-02-01  Nick Clifton  <nickc@redhat.com>
 679
 680         * po/da.po: Updated Danish translation.
 681
 682 2011-01-21  Dave Murphy  <davem@devkitpro.org>
 683
 684         * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
 685
 686 2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>
 687
 688         * i386-dis.c (sIbT): New.
 689         (b_T_mode): Likewise.
 690         (dis386): Replace sIb with sIbT on "pushT".
 691         (x86_64_table): Replace sIb with Ib on "aam" and "aad".
 692         (OP_sI): Handle b_T_mode.  Properly sign-extend byte.
 693
 694 2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>
 695
 696         * i386-init.h: Regenerated.
 697         * i386-tbl.h: Regenerated
 698
 699 2011-01-17  Quentin Neill  <quentin.neill@amd.com>
 700
 701         * i386-dis.c (REG_XOP_TBM_01): New.
 702         (REG_XOP_TBM_02): New.
 703         (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
 704         (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
 705         entries, and add bextr instruction.
 706
 707         * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
 708         (cpu_flags): Add CpuTBM.
 709
 710         * i386-opc.h (CpuTBM) New.
 711         (i386_cpu_flags): Add bit cputbm.
 712
 713         * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
 714         blcs, blsfill, blsic, t1mskc, and tzmsk.
 715
 716 2011-01-12  DJ Delorie  <dj@redhat.com>
 717
 718         * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
 719
 720 2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>
 721
 722         * mips-dis.c (print_insn_args): Adjust the value to print the real
 723         offset for "+c" argument.
 724
 725 2011-01-10  Nick Clifton  <nickc@redhat.com>
 726
 727         * po/da.po: Updated Danish translation.
 728
 729 2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
 730
 731         * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
 732
 733 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 734
 735         * i386-dis.c (REG_VEX_38F3): New.
 736         (PREFIX_0FBC): Likewise.
 737         (PREFIX_VEX_38F2): Likewise.
 738         (PREFIX_VEX_38F3_REG_1): Likewise.
 739         (PREFIX_VEX_38F3_REG_2): Likewise.
 740         (PREFIX_VEX_38F3_REG_3): Likewise.
 741         (PREFIX_VEX_38F7): Likewise.
 742         (VEX_LEN_38F2_P_0): Likewise.
 743         (VEX_LEN_38F3_R_1_P_0): Likewise.
 744         (VEX_LEN_38F3_R_2_P_0): Likewise.
 745         (VEX_LEN_38F3_R_3_P_0): Likewise.
 746         (VEX_LEN_38F7_P_0): Likewise.
 747         (dis386_twobyte): Use PREFIX_0FBC.
 748         (reg_table): Add REG_VEX_38F3.
 749         (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
 750         PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
 751         PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
 752         (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
 753         PREFIX_VEX_38F7.
 754         (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
 755         VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
 756         VEX_LEN_38F7_P_0.
 757
 758         * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
 759         (cpu_flags): Add CpuBMI.
 760
 761         * i386-opc.h (CpuBMI): New.
 762         (i386_cpu_flags): Add cpubmi.
 763
 764         * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
 765         * i386-init.h: Regenerated.
 766         * i386-tbl.h: Likewise.
 767
 768 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 769
 770         * i386-dis.c (VexGdq): New.
 771         (OP_VEX): Handle dq_mode.
 772
 773 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 774
 775         * i386-gen.c (process_copyright): Update copyright to 2011.
 776
 777 For older changes see ChangeLog-2010
 778 \f
 779 Local Variables:
 780 mode: change-log
 781 left-margin: 8
 782 fill-column: 74
 783 version-control: never
 784 End: