opcodes/ChangeLog

   1 2020-04-29  Nick Clifton  <nickc@redhat.com>
   2
   3         PR 22699
   4         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
   5         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
   6         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
   7         IMM0_8U case.
   8
   9 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
  10
  11         PR 25848
  12         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
  13         cmpi only on m68020up and cpu32.
  14
  15 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  16
  17         * aarch64-asm.c (aarch64_ins_none): New.
  18         * aarch64-asm.h (ins_none): New declaration.
  19         * aarch64-dis.c (aarch64_ext_none): New.
  20         * aarch64-dis.h (ext_none): New declaration.
  21         * aarch64-opc.c (aarch64_print_operand): Update case for
  22         AARCH64_OPND_BARRIER_PSB.
  23         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
  24         (AARCH64_OPERANDS): Update inserter/extracter for
  25         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
  26         * aarch64-asm-2.c: Regenerated.
  27         * aarch64-dis-2.c: Regenerated.
  28         * aarch64-opc-2.c: Regenerated.
  29
  30 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  31
  32         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
  33         (aarch64_feature_ras, RAS): Likewise.
  34         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
  35         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
  36         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
  37         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
  38         * aarch64-asm-2.c: Regenerated.
  39         * aarch64-dis-2.c: Regenerated.
  40         * aarch64-opc-2.c: Regenerated.
  41
  42 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
  43
  44         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
  45         (print_insn_neon): Support disassembly of conditional
  46         instructions.
  47
  48 2020-02-16  David Faust  <david.faust@oracle.com>
  49
  50         * bpf-desc.c: Regenerate.
  51         * bpf-desc.h: Likewise.
  52         * bpf-opc.c: Regenerate.
  53         * bpf-opc.h: Likewise.
  54
  55 2020-04-07  Lili Cui  <lili.cui@intel.com>
  56
  57         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
  58         (prefix_table): New instructions (see prefixes above).
  59         (rm_table): Likewise
  60         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
  61         CPU_ANY_TSXLDTRK_FLAGS.
  62         (cpu_flags): Add CpuTSXLDTRK.
  63         * i386-opc.h (enum): Add CpuTSXLDTRK.
  64         (i386_cpu_flags): Add cputsxldtrk.
  65         * i386-opc.tbl: Add XSUSPLDTRK insns.
  66         * i386-init.h: Regenerate.
  67         * i386-tbl.h: Likewise.
  68
  69 2020-04-02  Lili Cui  <lili.cui@intel.com>
  70
  71         * i386-dis.c (prefix_table): New instructions serialize.
  72         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
  73         CPU_ANY_SERIALIZE_FLAGS.
  74         (cpu_flags): Add CpuSERIALIZE.
  75         * i386-opc.h (enum): Add CpuSERIALIZE.
  76         (i386_cpu_flags): Add cpuserialize.
  77         * i386-opc.tbl: Add SERIALIZE insns.
  78         * i386-init.h: Regenerate.
  79         * i386-tbl.h: Likewise.
  80
  81 2020-03-26  Alan Modra  <amodra@gmail.com>
  82
  83         * disassemble.h (opcodes_assert): Declare.
  84         (OPCODES_ASSERT): Define.
  85         * disassemble.c: Don't include assert.h.  Include opintl.h.
  86         (opcodes_assert): New function.
  87         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
  88         (bfd_h8_disassemble): Reduce size of data array.  Correctly
  89         calculate maxlen.  Omit insn decoding when insn length exceeds
  90         maxlen.  Exit from nibble loop when looking for E, before
  91         accessing next data byte.  Move processing of E outside loop.
  92         Replace tests of maxlen in loop with assertions.
  93
  94 2020-03-26  Alan Modra  <amodra@gmail.com>
  95
  96         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
  97
  98 2020-03-25  Alan Modra  <amodra@gmail.com>
  99
 100         * z80-dis.c (suffix): Init mybuf.
 101
 102 2020-03-22  Alan Modra  <amodra@gmail.com>
 103
 104         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 105         successflly read from section.
 106
 107 2020-03-22  Alan Modra  <amodra@gmail.com>
 108
 109         * arc-dis.c (find_format): Use ISO C string concatenation rather
 110         than line continuation within a string.  Don't access needs_limm
 111         before testing opcode != NULL.
 112
 113 2020-03-22  Alan Modra  <amodra@gmail.com>
 114
 115         * ns32k-dis.c (print_insn_arg): Update comment.
 116         (print_insn_ns32k): Reduce size of index_offset array, and
 117         initialize, passing -1 to print_insn_arg for args that are not
 118         an index.  Don't exit arg loop early.  Abort on bad arg number.
 119
 120 2020-03-22  Alan Modra  <amodra@gmail.com>
 121
 122         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 123         * s12z-opc.c: Formatting.
 124         (operands_f): Return an int.
 125         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 126         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 127         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 128         (exg_sex_discrim): Likewise.
 129         (create_immediate_operand, create_bitfield_operand),
 130         (create_register_operand_with_size, create_register_all_operand),
 131         (create_register_all16_operand, create_simple_memory_operand),
 132         (create_memory_operand, create_memory_auto_operand): Don't
 133         segfault on malloc failure.
 134         (z_ext24_decode): Return an int status, negative on fail, zero
 135         on success.
 136         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 137         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 138         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 139         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 140         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 141         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 142         (loop_primitive_decode, shift_decode, psh_pul_decode),
 143         (bit_field_decode): Similarly.
 144         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 145         to return value, update callers.
 146         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 147         Don't segfault on NULL operand.
 148         (decode_operation): Return OP_INVALID on first fail.
 149         (decode_s12z): Check all reads, returning -1 on fail.
 150
 151 2020-03-20  Alan Modra  <amodra@gmail.com>
 152
 153         * metag-dis.c (print_insn_metag): Don't ignore status from
 154         read_memory_func.
 155
 156 2020-03-20  Alan Modra  <amodra@gmail.com>
 157
 158         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 159         Initialize parts of buffer not written when handling a possible
 160         2-byte insn at end of section.  Don't attempt decoding of such
 161         an insn by the 4-byte machinery.
 162
 163 2020-03-20  Alan Modra  <amodra@gmail.com>
 164
 165         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 166         partially filled buffer.  Prevent lookup of 4-byte insns when
 167         only VLE 2-byte insns are possible due to section size.  Print
 168         ".word" rather than ".long" for 2-byte leftovers.
 169
 170 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 171
 172         PR 25641
 173         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 174
 175 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 176
 177         * i386-dis.c (X86_64_0D): Rename to ...
 178         (X86_64_0E): ... this.
 179
 180 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 181
 182         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 183         * Makefile.in: Regenerated.
 184
 185 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 186
 187         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 188         3-operand pseudos.
 189         * i386-tbl.h: Re-generate.
 190
 191 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 194         vprot*, vpsha*, and vpshl*.
 195         * i386-tbl.h: Re-generate.
 196
 197 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 200         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 201         * i386-tbl.h: Re-generate.
 202
 203 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 204
 205         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 206         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 207         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 208         * i386-tbl.h: Re-generate.
 209
 210 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 211
 212         * i386-gen.c (struct template_arg, struct template_instance,
 213         struct template_param, struct template, templates,
 214         parse_template, expand_templates): New.
 215         (process_i386_opcodes): Various local variables moved to
 216         expand_templates. Call parse_template and expand_templates.
 217         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 218         * i386-tbl.h: Re-generate.
 219
 220 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 221
 222         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 223         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 224         register and memory source templates. Replace VexW= by VexW*
 225         where applicable.
 226         * i386-tbl.h: Re-generate.
 227
 228 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 229
 230         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 231         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 232         * i386-tbl.h: Re-generate.
 233
 234 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 235
 236         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 237         * i386-tbl.h: Re-generate.
 238
 239 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 240
 241         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 242         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 243         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 244         VexW0 on SSE2AVX variants.
 245         (vmovq): Drop NoRex64 from XMM/XMM variants.
 246         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 247         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 248         applicable use VexW0.
 249         * i386-tbl.h: Re-generate.
 250
 251 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 254         * i386-opc.h (Rex64): Delete.
 255         (struct i386_opcode_modifier): Remove rex64 field.
 256         * i386-opc.tbl (crc32): Drop Rex64.
 257         Replace Rex64 with Size64 everywhere else.
 258         * i386-tbl.h: Re-generate.
 259
 260 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 261
 262         * i386-dis.c (OP_E_memory): Exclude recording of used address
 263         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 264         addressed memory operands for MPX insns.
 265
 266 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 269         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 270         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 271         (ptwrite): Split into non-64-bit and 64-bit forms.
 272         * i386-tbl.h: Re-generate.
 273
 274 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 275
 276         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 277         template.
 278         * i386-tbl.h: Re-generate.
 279
 280 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 283         (prefix_table): Move vmmcall here. Add vmgexit.
 284         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 285         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 286         (cpu_flags): Add CpuSEV_ES entry.
 287         * i386-opc.h (CpuSEV_ES): New.
 288         (union i386_cpu_flags): Add cpusev_es field.
 289         * i386-opc.tbl (vmgexit): New.
 290         * i386-init.h, i386-tbl.h: Re-generate.
 291
 292 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 293
 294         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 295         with MnemonicSize.
 296         * i386-opc.h (IGNORESIZE): New.
 297         (DEFAULTSIZE): Likewise.
 298         (IgnoreSize): Removed.
 299         (DefaultSize): Likewise.
 300         (MnemonicSize): New.
 301         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 302         mnemonicsize.
 303         * i386-opc.tbl (IgnoreSize): New.
 304         (DefaultSize): Likewise.
 305         * i386-tbl.h: Regenerated.
 306
 307 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 308
 309         PR 25627
 310         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 311         instructions.
 312
 313 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 314
 315         PR gas/25622
 316         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 317         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 318         * i386-tbl.h: Regenerated.
 319
 320 2020-02-26  Alan Modra  <amodra@gmail.com>
 321
 322         * aarch64-asm.c: Indent labels correctly.
 323         * aarch64-dis.c: Likewise.
 324         * aarch64-gen.c: Likewise.
 325         * aarch64-opc.c: Likewise.
 326         * alpha-dis.c: Likewise.
 327         * i386-dis.c: Likewise.
 328         * nds32-asm.c: Likewise.
 329         * nfp-dis.c: Likewise.
 330         * visium-dis.c: Likewise.
 331
 332 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 333
 334         * arc-regs.h (int_vector_base): Make it available for all ARC
 335         CPUs.
 336
 337 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 338
 339         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 340         changed.
 341
 342 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 343
 344         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 345         c.mv/c.li if rs1 is zero.
 346
 347 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 348
 349         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 350         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 351         CPU_POPCNT_FLAGS.
 352         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 353         * i386-opc.h (CpuABM): Removed.
 354         (CpuPOPCNT): New.
 355         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 356         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 357         popcnt.  Remove CpuABM from lzcnt.
 358         * i386-init.h: Regenerated.
 359         * i386-tbl.h: Likewise.
 360
 361 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 362
 363         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 364         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 365         VexW1 instead of open-coding them.
 366         * i386-tbl.h: Re-generate.
 367
 368 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 369
 370         * i386-opc.tbl (AddrPrefixOpReg): Define.
 371         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 372         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 373         templates. Drop NoRex64.
 374         * i386-tbl.h: Re-generate.
 375
 376 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 377
 378         PR gas/6518
 379         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 380         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 381         into Intel syntax instance (with Unpsecified) and AT&T one
 382         (without).
 383         (vcvtneps2bf16): Likewise, along with folding the two so far
 384         separate ones.
 385         * i386-tbl.h: Re-generate.
 386
 387 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 388
 389         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 390         CPU_ANY_SSE4A_FLAGS.
 391
 392 2020-02-17  Alan Modra  <amodra@gmail.com>
 393
 394         * i386-gen.c (cpu_flag_init): Correct last change.
 395
 396 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 397
 398         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 399         CPU_ANY_SSE4_FLAGS.
 400
 401 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 402
 403         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 404         (movzx): Likewise.
 405
 406 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 407
 408         PR gas/25438
 409         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 410         destination for Cpu64-only variant.
 411         (movzx): Fold patterns.
 412         * i386-tbl.h: Re-generate.
 413
 414 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 415
 416         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 417         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 418         CPU_ANY_SSE4_FLAGS entry.
 419         * i386-init.h: Re-generate.
 420
 421 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 422
 423         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 424         with Unspecified, making the present one AT&T syntax only.
 425         * i386-tbl.h: Re-generate.
 426
 427 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 428
 429         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 430         * i386-tbl.h: Re-generate.
 431
 432 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 433
 434         PR gas/24546
 435         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 436         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 437         Amd64 and Intel64 templates.
 438         (call, jmp): Likewise for far indirect variants. Dro
 439         Unspecified.
 440         * i386-tbl.h: Re-generate.
 441
 442 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 443
 444         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 445         * i386-opc.h (ShortForm): Delete.
 446         (struct i386_opcode_modifier): Remove shortform field.
 447         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 448         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 449         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 450         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 451         Drop ShortForm.
 452         * i386-tbl.h: Re-generate.
 453
 454 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 455
 456         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 457         fucompi): Drop ShortForm from operand-less templates.
 458         * i386-tbl.h: Re-generate.
 459
 460 2020-02-11  Alan Modra  <amodra@gmail.com>
 461
 462         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 463         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 464         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 465         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 466         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 467
 468 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 469
 470         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 471         (cde_opcodes): Add VCX* instructions.
 472
 473 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 474             Matthew Malcomson  <matthew.malcomson@arm.com>
 475
 476         * arm-dis.c (struct cdeopcode32): New.
 477         (CDE_OPCODE): New macro.
 478         (cde_opcodes): New disassembly table.
 479         (regnames): New option to table.
 480         (cde_coprocs): New global variable.
 481         (print_insn_cde): New
 482         (print_insn_thumb32): Use print_insn_cde.
 483         (parse_arm_disassembler_options): Parse coprocN args.
 484
 485 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 486
 487         PR gas/25516
 488         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 489         with ISA64.
 490         * i386-opc.h (AMD64): Removed.
 491         (Intel64): Likewose.
 492         (AMD64): New.
 493         (INTEL64): Likewise.
 494         (INTEL64ONLY): Likewise.
 495         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 496         * i386-opc.tbl (Amd64): New.
 497         (Intel64): Likewise.
 498         (Intel64Only): Likewise.
 499         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 500         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 501         * i386-tbl.h: Regenerated.
 502
 503 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 504
 505         PR 25469
 506         * z80-dis.c: Add support for GBZ80 opcodes.
 507
 508 2020-02-04  Alan Modra  <amodra@gmail.com>
 509
 510         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 511
 512 2020-02-03  Alan Modra  <amodra@gmail.com>
 513
 514         * m32c-ibld.c: Regenerate.
 515
 516 2020-02-01  Alan Modra  <amodra@gmail.com>
 517
 518         * frv-ibld.c: Regenerate.
 519
 520 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 521
 522         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 523         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 524         (OP_E_memory): Replace xmm_mdq_mode case label by
 525         vex_scalar_w_dq_mode one.
 526         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 527
 528 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 529
 530         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 531         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 532         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 533         (intel_operand_size): Drop vex_w_dq_mode case label.
 534
 535 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 536
 537         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 538         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 539
 540 2020-01-30  Alan Modra  <amodra@gmail.com>
 541
 542         * m32c-ibld.c: Regenerate.
 543
 544 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 545
 546         * bpf-opc.c: Regenerate.
 547
 548 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 549
 550         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 551         (dis386): Use them to replace C2/C3 table entries.
 552         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 553         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 554         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 555         * i386-tbl.h: Re-generate.
 556
 557 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 558
 559         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 560         forms.
 561         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 562         DefaultSize.
 563         * i386-tbl.h: Re-generate.
 564
 565 2020-01-30  Alan Modra  <amodra@gmail.com>
 566
 567         * tic4x-dis.c (tic4x_dp): Make unsigned.
 568
 569 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 570             Jan Beulich  <jbeulich@suse.com>
 571
 572         PR binutils/25445
 573         * i386-dis.c (MOVSXD_Fixup): New function.
 574         (movsxd_mode): New enum.
 575         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 576         (intel_operand_size): Handle movsxd_mode.
 577         (OP_E_register): Likewise.
 578         (OP_G): Likewise.
 579         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 580         register on movsxd.  Add movsxd with 16-bit destination register
 581         for AMD64 and Intel64 ISAs.
 582         * i386-tbl.h: Regenerated.
 583
 584 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 585
 586         PR 25403
 587         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 588         * aarch64-asm-2.c: Regenerate
 589         * aarch64-dis-2.c: Likewise.
 590         * aarch64-opc-2.c: Likewise.
 591
 592 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-opc.tbl (sysret): Drop DefaultSize.
 595         * i386-tbl.h: Re-generate.
 596
 597 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 598
 599         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 600         Dword.
 601         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 602         * i386-tbl.h: Re-generate.
 603
 604 2020-01-20  Nick Clifton  <nickc@redhat.com>
 605
 606         * po/de.po: Updated German translation.
 607         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 608         * po/uk.po: Updated Ukranian translation.
 609
 610 2020-01-20  Alan Modra  <amodra@gmail.com>
 611
 612         * hppa-dis.c (fput_const): Remove useless cast.
 613
 614 2020-01-20  Alan Modra  <amodra@gmail.com>
 615
 616         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 617
 618 2020-01-18  Nick Clifton  <nickc@redhat.com>
 619
 620         * configure: Regenerate.
 621         * po/opcodes.pot: Regenerate.
 622
 623 2020-01-18  Nick Clifton  <nickc@redhat.com>
 624
 625         Binutils 2.34 branch created.
 626
 627 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 628
 629         * opintl.h: Fix spelling error (seperate).
 630
 631 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 632
 633         * i386-opc.tbl: Add {vex} pseudo prefix.
 634         * i386-tbl.h: Regenerated.
 635
 636 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 637
 638         PR 25376
 639         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 640         (neon_opcodes): Likewise.
 641         (select_arm_features): Make sure we enable MVE bits when selecting
 642         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 643         any architecture.
 644
 645 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 646
 647         * i386-opc.tbl: Drop stale comment from XOP section.
 648
 649 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 650
 651         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 652         (extractps): Add VexWIG to SSE2AVX forms.
 653         * i386-tbl.h: Re-generate.
 654
 655 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 656
 657         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 658         Size64 from and use VexW1 on SSE2AVX forms.
 659         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 660         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 661         * i386-tbl.h: Re-generate.
 662
 663 2020-01-15  Alan Modra  <amodra@gmail.com>
 664
 665         * tic4x-dis.c (tic4x_version): Make unsigned long.
 666         (optab, optab_special, registernames): New file scope vars.
 667         (tic4x_print_register): Set up registernames rather than
 668         malloc'd registertable.
 669         (tic4x_disassemble): Delete optable and optable_special.  Use
 670         optab and optab_special instead.  Throw away old optab,
 671         optab_special and registernames when info->mach changes.
 672
 673 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 674
 675         PR 25377
 676         * z80-dis.c (suffix): Use .db instruction to generate double
 677         prefix.
 678
 679 2020-01-14  Alan Modra  <amodra@gmail.com>
 680
 681         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 682         values to unsigned before shifting.
 683
 684 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 685
 686         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 687         flow instructions.
 688         (print_insn_thumb16, print_insn_thumb32): Likewise.
 689         (print_insn): Initialize the insn info.
 690         * i386-dis.c (print_insn): Initialize the insn info fields, and
 691         detect jumps.
 692
 693 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 694
 695         * arc-opc.c (C_NE): Make it required.
 696
 697 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 698
 699         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 700         reserved register name.
 701
 702 2020-01-13  Alan Modra  <amodra@gmail.com>
 703
 704         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 705         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 706
 707 2020-01-13  Alan Modra  <amodra@gmail.com>
 708
 709         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 710         result of wasm_read_leb128 in a uint64_t and check that bits
 711         are not lost when copying to other locals.  Use uint32_t for
 712         most locals.  Use PRId64 when printing int64_t.
 713
 714 2020-01-13  Alan Modra  <amodra@gmail.com>
 715
 716         * score-dis.c: Formatting.
 717         * score7-dis.c: Formatting.
 718
 719 2020-01-13  Alan Modra  <amodra@gmail.com>
 720
 721         * score-dis.c (print_insn_score48): Use unsigned variables for
 722         unsigned values.  Don't left shift negative values.
 723         (print_insn_score32): Likewise.
 724         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 725
 726 2020-01-13  Alan Modra  <amodra@gmail.com>
 727
 728         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 729
 730 2020-01-13  Alan Modra  <amodra@gmail.com>
 731
 732         * fr30-ibld.c: Regenerate.
 733
 734 2020-01-13  Alan Modra  <amodra@gmail.com>
 735
 736         * xgate-dis.c (print_insn): Don't left shift signed value.
 737         (ripBits): Formatting, use 1u.
 738
 739 2020-01-10  Alan Modra  <amodra@gmail.com>
 740
 741         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 742         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 743
 744 2020-01-10  Alan Modra  <amodra@gmail.com>
 745
 746         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 747         and XRREG value earlier to avoid a shift with negative exponent.
 748         * m10200-dis.c (disassemble): Similarly.
 749
 750 2020-01-09  Nick Clifton  <nickc@redhat.com>
 751
 752         PR 25224
 753         * z80-dis.c (ld_ii_ii): Use correct cast.
 754
 755 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 756
 757         PR 25224
 758         * z80-dis.c (ld_ii_ii): Use character constant when checking
 759         opcode byte value.
 760
 761 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 762
 763         * i386-dis.c (SEP_Fixup): New.
 764         (SEP): Define.
 765         (dis386_twobyte): Use it for sysenter/sysexit.
 766         (enum x86_64_isa): Change amd64 enumerator to value 1.
 767         (OP_J): Compare isa64 against intel64 instead of amd64.
 768         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 769         forms.
 770         * i386-tbl.h: Re-generate.
 771
 772 2020-01-08  Alan Modra  <amodra@gmail.com>
 773
 774         * z8k-dis.c: Include libiberty.h
 775         (instr_data_s): Make max_fetched unsigned.
 776         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 777         Don't exceed byte_info bounds.
 778         (output_instr): Make num_bytes unsigned.
 779         (unpack_instr): Likewise for nibl_count and loop.
 780         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 781         idx unsigned.
 782         * z8k-opc.h: Regenerate.
 783
 784 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 785
 786         * arc-tbl.h (llock): Use 'LLOCK' as class.
 787         (llockd): Likewise.
 788         (scond): Use 'SCOND' as class.
 789         (scondd): Likewise.
 790         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 791         (scondd): Likewise.
 792
 793 2020-01-06  Alan Modra  <amodra@gmail.com>
 794
 795         * m32c-ibld.c: Regenerate.
 796
 797 2020-01-06  Alan Modra  <amodra@gmail.com>
 798
 799         PR 25344
 800         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 801         Peek at next byte to prevent recursion on repeated prefix bytes.
 802         Ensure uninitialised "mybuf" is not accessed.
 803         (print_insn_z80): Don't zero n_fetch and n_used here,..
 804         (print_insn_z80_buf): ..do it here instead.
 805
 806 2020-01-04  Alan Modra  <amodra@gmail.com>
 807
 808         * m32r-ibld.c: Regenerate.
 809
 810 2020-01-04  Alan Modra  <amodra@gmail.com>
 811
 812         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 813
 814 2020-01-04  Alan Modra  <amodra@gmail.com>
 815
 816         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 817
 818 2020-01-04  Alan Modra  <amodra@gmail.com>
 819
 820         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 821
 822 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 823
 824         * aarch64-tbl.h (aarch64_opcode_table): Use
 825         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 826
 827 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 828
 829         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 830         forms of SUDOT and USDOT.
 831
 832 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 833
 834         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 835         uzip{1,2}.
 836         * opcodes/aarch64-dis-2.c: Re-generate.
 837
 838 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 839
 840         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 841         FMMLA encoding.
 842         * opcodes/aarch64-dis-2.c: Re-generate.
 843
 844 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 845
 846         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 847
 848 2020-01-01  Alan Modra  <amodra@gmail.com>
 849
 850         Update year range in copyright notice of all files.
 851
 852 For older changes see ChangeLog-2019
 853 \f
 854 Copyright (C) 2020 Free Software Foundation, Inc.
 855
 856 Copying and distribution of this file, with or without modification,
 857 are permitted in any medium without royalty provided the copyright
 858 notice and this notice are preserved.
 859
 860 Local Variables:
 861 mode: change-log
 862 left-margin: 8
 863 fill-column: 74
 864 version-control: never
 865 End: