opcodes/ChangeLog

   1 2013-12-13  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
   2
   3         * nds32-dis.c (mnemonic_96): Fix typo.
   4
   5 2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
   6             Wei-Cheng Wang  <cole945@gmail.com>
   7
   8         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nds32-asm.c
   9         and nds32-dis.c.
  10         * Makefile.in: Regenerate.
  11         * configure.in: Add case for bfd_nds32_arch.
  12         * configure: Regenerate.
  13         * disassemble.c (ARCH_nds32): Define.
  14         * nds32-asm.c: New file for nds32.
  15         * nds32-asm.h: New file for nds32.
  16         * nds32-dis.c: New file for nds32.
  17         * nds32-opc.h: New file for nds32.
  18
  19 2013-12-05  Nick Clifton  <nickc@redhat.com>
  20
  21         * s390-mkopc.c (dumpTable): Provide a format string to printf so
  22         that compiling with -Werror=format-security does not produce an
  23         error.
  24
  25 2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
  26
  27         * aarch64-opc.c (aarch64_pstatefields): Update.
  28
  29 2013-11-19  Catherine Moore  <clm@codesourcery.com>
  30
  31         * micromips-opc.c (LM): Define.
  32         (micromips_opcodes): Add LM to load instructions.
  33         * mips-opc.c (prefe): Add LM attribute.
  34
  35 2013-11-18  Yufeng Zhang  <yufeng.zhang@arm.com>
  36
  37         Revert
  38
  39         2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  40
  41         * aarch64-opc.c (CPENT): New define.
  42         (F_READONLY, F_WRITEONLY): Likewise.
  43         (aarch64_sys_regs): Add trace unit registers.
  44         (aarch64_sys_reg_readonly_p): New function.
  45         (aarch64_sys_reg_writeonly_p): Ditto.
  46
  47 2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  48
  49         * aarch64-opc.c (CPENT): New define.
  50         (F_READONLY, F_WRITEONLY): Likewise.
  51         (aarch64_sys_regs): Add trace unit registers.
  52         (aarch64_sys_reg_readonly_p): New function.
  53         (aarch64_sys_reg_writeonly_p): Ditto.
  54
  55 2013-11-15  Maciej W. Rozycki  <macro@codesourcery.com>
  56
  57         * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
  58         "mtcr".
  59
  60 2013-11-11  Catherine Moore  <clm@codesourcery.com>
  61
  62         * mips-dis.c (print_insn_mips): Use
  63         INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
  64         (print_insn_micromips): Likewise.
  65         * mips-opc.c (LDD): Remove.
  66         (CLD): Include INSN_LOAD_MEMORY.
  67         (LM): New.
  68         (mips_builtin_opcodes): Use LM instead of LDD.
  69         Add LM to load instructions.
  70
  71 2013-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  72
  73         PR gas/16140
  74         * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
  75         * i386-init.h: Regenerated.
  76
  77 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  78
  79         * aarch64-opc.c (F_DEPRECATED): New macro.
  80         (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
  81         F_DEPRECATED.
  82         (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
  83         AARCH64_OPND_SYSREG.
  84
  85 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  86
  87         * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
  88         (convert_from_csel): Likewise.
  89         * aarch64-opc.c (operand_general_constraint_met_p): Handle
  90         AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
  91         (aarch64_print_operand): Handle AARCH64_OPND_COND1.
  92         * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
  93         COND for cinc, cset, cinv, csetm and cneg.
  94         (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
  95         * aarch64-asm-2.c: Re-generated.
  96         * aarch64-dis-2.c: Ditto.
  97         * aarch64-opc-2.c: Ditto.
  98
  99 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 100
 101         * aarch64-opc.c (set_syntax_error): New function.
 102         (operand_general_constraint_met_p): Replace set_other_error
 103         with set_syntax_error.
 104
 105 2013-10-30  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 106
 107         * s390-dis.c (init_disasm): Default to full 'zarch' opcode
 108         availability even for 31-bit programs.
 109
 110 2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 111
 112         * arm-dis.c (neon_opcodes): Adjust print string for vshll.
 113
 114 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 115
 116         * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
 117         +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
 118         +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 119         (MSA): New define.
 120         (MSA64): New define.
 121         (micromips_opcodes): Add MSA instructions.
 122         * mips-dis.c (msa_control_names): New array.
 123         (mips_abi_choice): Add ASE_MSA to mips32r2.
 124         Remove ASE_MDMX from mips64r2.
 125         Add ASE_MSA and ASE_MSA64 to mips64r2.
 126         (parse_mips_dis_option): Handle -Mmsa.
 127         (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
 128         (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
 129         (print_mips_disassembler_options): Print -Mmsa.
 130         * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
 131         +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 132         (MSA): New define.
 133         (MSA64): New define.
 134         (mips_builtin_op): Add MSA instructions.
 135
 136 2013-10-13  Sandra Loosemore  <sandra@codesourcery.com>
 137
 138         * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
 139         as the primary name of r30.
 140
 141 2013-10-12  Jan Beulich <jbeulich@suse.com>
 142
 143         * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
 144         default case.
 145         (OP_E_register): Move v_bnd_mode alongside m_mode.
 146         * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
 147         Drop Reg16 and Disp16. Add NoRex64.
 148         (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
 149         * i386-tbl.h: Re-generate.
 150
 151 2013-10-10  Sean Keys <skeys@ipdatasys.com>
 152
 153         * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
 154         table.
 155         * xgate-dis.c (print_insn): Refactor to work with table change.
 156
 157 2013-10-10  Roland McGrath  <mcgrathr@google.com>
 158
 159         * i386-dis.c (oappend_maybe_intel): New function.
 160         (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
 161         (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
 162         (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
 163
 164         * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
 165         possible compiler warnings when the union's initializer is
 166         actually meant for the 'preg' enum typed member.
 167         * crx-opc.c (REG): Likewise.
 168
 169         * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
 170         Remove duplicate const qualifier.
 171
 172 2013-10-08  Jan Beulich <jbeulich@suse.com>
 173
 174         * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
 175         (clflush): Use Anysize instead of Byte|Unspecified.
 176         (prefetch*): Likewise.
 177         * i386-tbl.h: Re-generate.
 178
 179 2013-10-07  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 180
 181         * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
 182
 183 2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 184
 185         * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
 186         * i386-init.h: Regenerated.
 187
 188 2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 189
 190         * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
 191         * i386-init.h: Regenerated.
 192
 193 2013-09-20  Alan Modra  <amodra@gmail.com>
 194
 195         * configure: Regenerate.
 196
 197 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 198
 199         * s390-opc.txt (clih): Make the immediate unsigned.
 200
 201 2013-09-04  Roland McGrath  <mcgrathr@google.com>
 202
 203         PR gas/15914
 204         * arm-dis.c (arm_opcodes): Add udf.
 205         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
 206         (thumb32_opcodes): Add udf.w.
 207         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
 208
 209 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 210
 211         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
 212         For the load fp integer instructions only the suppression flag was
 213         new with z196 version.
 214
 215 2013-08-28  Nick Clifton  <nickc@redhat.com>
 216
 217         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
 218         immediate is not suitable for the 32-bit ABI.
 219
 220 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
 221
 222         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
 223         replacing NODS.
 224
 225 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
 226
 227         PR binutils/15834
 228         * aarch64-asm.c: Fix typos.
 229         * aarch64-dis.c: Likewise.
 230         * msp430-dis.c: Likewise.
 231
 232 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 233
 234         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
 235         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
 236         Use +H rather than +C for the real "dext".
 237         * mips-opc.c (mips_builtin_opcodes): Likewise.
 238
 239 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 240
 241         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
 242         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
 243         and OPTIONAL_MAPPED_REG.
 244         * mips-opc.c (decode_mips_operand): Likewise.
 245         * mips16-opc.c (decode_mips16_operand): Likewise.
 246         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
 247
 248 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
 249
 250         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
 251         (PREFIX_EVEX_0F3A3F): Likewise.
 252         * i386-dis-evex.h (evex_table): Updated.
 253
 254 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
 255
 256         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
 257         VCLIPW.
 258
 259 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
 260             Konrad Eisele  <konrad@gaisler.com>
 261
 262         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
 263         bfd_mach_sparc.
 264         * sparc-opc.c (MASK_LEON): Define.
 265         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
 266         (letandleon): New macro.
 267         (v9andleon): Likewise.
 268         (sparc_opc): Add leon.
 269         (umac): Enable for letandleon.
 270         (smac): Likewise.
 271         (casa): Enable for v9andleon.
 272         (cas): Likewise.
 273         (casl): Likewise.
 274
 275 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 276             Richard Sandiford  <rdsandiford@googlemail.com>
 277
 278         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
 279         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
 280         (print_vu0_channel): New function.
 281         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
 282         (print_insn_args): Handle '#'.
 283         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
 284         * mips-opc.c (mips_vu0_channel_mask): New constant.
 285         (decode_mips_operand): Handle new VU0 operand types.
 286         (VU0, VU0CH): New macros.
 287         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
 288         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
 289         Use "+6" rather than "G" for QMFC2 and QMTC2.
 290
 291 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 292
 293         * mips-formats.h (PCREL): Reorder parameters and update the definition
 294         to match new mips_pcrel_operand layout.
 295         (JUMP, JALX, BRANCH): Update accordingly.
 296         * mips16-opc.c (decode_mips16_operand): Likewise.
 297
 298 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 299
 300         * micromips-opc.c (WR_s): Delete.
 301
 302 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 303
 304         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 305         New macros.
 306         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 307         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 308         (mips_builtin_opcodes): Use the new position-based read-write flags
 309         instead of field-based ones.  Use UDI for "udi..." instructions.
 310         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 311         New macros.
 312         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 313         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 314         (WR_SP, RD_16): New macros.
 315         (RD_SP): Redefine as an INSN2_* flag.
 316         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 317         (mips16_opcodes): Use the new position-based read-write flags
 318         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 319         pinfo2 field.
 320         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 321         New macros.
 322         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 323         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 324         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 325         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 326         (micromips_opcodes): Use the new position-based read-write flags
 327         instead of field-based ones.
 328         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 329         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 330         of field-based flags.
 331
 332 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 333
 334         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 335         (WR_SP): Replace with...
 336         (MOD_SP): ...this.
 337         (mips16_opcodes): Update accordingly.
 338         * mips-dis.c (print_insn_mips16): Likewise.
 339
 340 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 341
 342         * mips16-opc.c (mips16_opcodes): Reformat.
 343
 344 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 345
 346         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 347         for operands that are hard-coded to $0.
 348         * micromips-opc.c (micromips_opcodes): Likewise.
 349
 350 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 351
 352         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 353         for the single-operand forms of JALR and JALR.HB.
 354         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 355         and JALRS.HB.
 356
 357 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 358
 359         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 360         instructions.  Fix them to use WR_MACC instead of WR_CC and
 361         add missing RD_MACCs.
 362
 363 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 364
 365         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 366
 367 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 368
 369         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 370
 371 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 372             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 373             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 374             Sergey Lega  <sergey.s.lega@intel.com>
 375             Anna Tikhonova  <anna.tikhonova@intel.com>
 376             Ilya Tocar  <ilya.tocar@intel.com>
 377             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 378             Ilya Verbin  <ilya.verbin@intel.com>
 379             Kirill Yukhin  <kirill.yukhin@intel.com>
 380             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 381
 382         * i386-dis-evex.h: New.
 383         * i386-dis.c (OP_Rounding): New.
 384         (VPCMP_Fixup): New.
 385         (OP_Mask): New.
 386         (Rdq): New.
 387         (XMxmmq): New.
 388         (EXdScalarS): New.
 389         (EXymm): New.
 390         (EXEvexHalfBcstXmmq): New.
 391         (EXxmm_mdq): New.
 392         (EXEvexXGscat): New.
 393         (EXEvexXNoBcst): New.
 394         (VPCMP): New.
 395         (EXxEVexR): New.
 396         (EXxEVexS): New.
 397         (XMask): New.
 398         (MaskG): New.
 399         (MaskE): New.
 400         (MaskR): New.
 401         (MaskVex): New.
 402         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 403         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 404         evex_rounding_mode, evex_sae_mode, mask_mode.
 405         (USE_EVEX_TABLE): New.
 406         (EVEX_TABLE): New.
 407         (EVEX enum): New.
 408         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 409         REG_EVEX_0F38C7.
 410         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 411         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 412         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 413         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 414         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 415         MOD_EVEX_0F38C7_REG_6.
 416         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 417         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 418         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 419         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 420         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 421         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 422         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 423         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 424         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 425         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 426         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 427         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 428         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 429         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 430         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 431         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 432         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 433         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 434         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 435         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 436         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 437         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 438         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 439         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 440         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 441         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 442         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 443         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 444         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 445         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 446         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 447         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 448         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 449         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 450         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 451         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 452         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 453         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 454         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 455         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 456         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 457         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 458         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 459         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 460         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 461         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 462         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 463         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 464         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 465         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 466         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 467         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 468         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 469         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 470         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 471         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 472         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 473         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 474         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 475         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 476         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 477         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 478         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 479         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 480         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 481         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 482         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 483         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 484         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 485         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 486         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 487         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 488         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 489         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 490         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 491         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 492         PREFIX_EVEX_0F3A55.
 493         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 494         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 495         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 496         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 497         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 498         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 499         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 500         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 501         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 502         VEX_W_0F3A32_P_2_LEN_0.
 503         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 504         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 505         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 506         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 507         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 508         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 509         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 510         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 511         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 512         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 513         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 514         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 515         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 516         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 517         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 518         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 519         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 520         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 521         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 522         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 523         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 524         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 525         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 526         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 527         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 528         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 529         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 530         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 531         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 532         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 533         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 534         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 535         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 536         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 537         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 538         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 539         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 540         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 541         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 542         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 543         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 544         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 545         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 546         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 547         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 548         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 549         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 550         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 551         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 552         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 553         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 554         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 555         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 556         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 557         (struct vex): Add fields evex, r, v, mask_register_specifier,
 558         zeroing, ll, b.
 559         (intel_names_xmm): Add upper 16 registers.
 560         (att_names_xmm): Ditto.
 561         (intel_names_ymm): Ditto.
 562         (att_names_ymm): Ditto.
 563         (names_zmm): New.
 564         (intel_names_zmm): Ditto.
 565         (att_names_zmm): Ditto.
 566         (names_mask): Ditto.
 567         (intel_names_mask): Ditto.
 568         (att_names_mask): Ditto.
 569         (names_rounding): Ditto.
 570         (names_broadcast): Ditto.
 571         (x86_64_table): Add escape to evex-table.
 572         (reg_table): Include reg_table evex-entries from
 573         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 574         (prefix_table): Add entries for new instructions.
 575         (vex_table): Ditto.
 576         (vex_len_table): Ditto.
 577         (vex_w_table): Ditto.
 578         (mod_table): Ditto.
 579         (get_valid_dis386): Properly handle new instructions.
 580         (print_insn): Handle zmm and mask registers, print mask operand.
 581         (intel_operand_size): Support EVEX, new modes and sizes.
 582         (OP_E_register): Handle new modes.
 583         (OP_E_memory): Ditto.
 584         (OP_G): Ditto.
 585         (OP_XMM): Ditto.
 586         (OP_EX): Ditto.
 587         (OP_VEX): Ditto.
 588         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 589         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 590         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 591         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 592         CpuAVX512PF and CpuVREX.
 593         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 594         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 595         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 596         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 597         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 598         * i386-init.h: Regenerate.
 599         * i386-opc.h (CpuAVX512F): New.
 600         (CpuAVX512CD): New.
 601         (CpuAVX512ER): New.
 602         (CpuAVX512PF): New.
 603         (CpuVREX): New.
 604         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 605         cpuavx512pf and cpuvrex fields.
 606         (VecSIB): Add VecSIB512.
 607         (EVex): New.
 608         (Masking): New.
 609         (VecESize): New.
 610         (Broadcast): New.
 611         (StaticRounding): New.
 612         (SAE): New.
 613         (Disp8MemShift): New.
 614         (NoDefMask): New.
 615         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 616         staticrounding, sae, disp8memshift and nodefmask.
 617         (RegZMM): New.
 618         (Zmmword): Ditto.
 619         (Vec_Disp8): Ditto.
 620         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 621         fields.
 622         (RegVRex): New.
 623         * i386-opc.tbl: Add AVX512 instructions.
 624         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 625         registers, mask registers.
 626         * i386-tbl.h: Regenerate.
 627
 628 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 629
 630         PR gas/15220
 631         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 632         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 633
 634 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 635
 636         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 637         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 638         PREFIX_0F3ACC.
 639         (prefix_table): Updated.
 640         (three_byte_table): Likewise.
 641         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 642         (cpu_flags): Add CpuSHA.
 643         (i386_cpu_flags): Add cpusha.
 644         * i386-init.h: Regenerate.
 645         * i386-opc.h (CpuSHA): New.
 646         (CpuUnused): Restored.
 647         (i386_cpu_flags): Add cpusha.
 648         * i386-opc.tbl: Add SHA instructions.
 649         * i386-tbl.h: Regenerate.
 650
 651 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 652             Kirill Yukhin  <kirill.yukhin@intel.com>
 653             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 654
 655         * i386-dis.c (BND_Fixup): New.
 656         (Ebnd): New.
 657         (Ev_bnd): New.
 658         (Gbnd): New.
 659         (BND): New.
 660         (v_bnd_mode): New.
 661         (bnd_mode): New.
 662         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 663         MOD_0F1B_PREFIX_1.
 664         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 665         (dis tables): Replace XX with BND for near branch and call
 666         instructions.
 667         (prefix_table): Add new entries.
 668         (mod_table): Likewise.
 669         (names_bnd): New.
 670         (intel_names_bnd): New.
 671         (att_names_bnd): New.
 672         (BND_PREFIX): New.
 673         (prefix_name): Handle BND_PREFIX.
 674         (print_insn): Initialize names_bnd.
 675         (intel_operand_size): Handle new modes.
 676         (OP_E_register): Likewise.
 677         (OP_E_memory): Likewise.
 678         (OP_G): Likewise.
 679         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 680         (cpu_flags): Add CpuMPX.
 681         (operand_type_init): Add RegBND.
 682         (opcode_modifiers): Add BNDPrefixOk.
 683         (operand_types): Add RegBND.
 684         * i386-init.h: Regenerate.
 685         * i386-opc.h (CpuMPX): New.
 686         (CpuUnused): Comment out.
 687         (i386_cpu_flags): Add cpumpx.
 688         (BNDPrefixOk): New.
 689         (i386_opcode_modifier): Add bndprefixok.
 690         (RegBND): New.
 691         (i386_operand_type): Add regbnd.
 692         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 693         Add MPX instructions and bnd prefix.
 694         * i386-reg.tbl: Add bnd0-bnd3 registers.
 695         * i386-tbl.h: Regenerate.
 696
 697 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 698
 699         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 700         ATTRIBUTE_UNUSED.
 701
 702 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 703
 704         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 705         special rules.
 706         * Makefile.in: Regenerate.
 707         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 708         all fields.  Reformat.
 709
 710 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 711
 712         * mips16-opc.c: Include mips-formats.h.
 713         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 714         static arrays.
 715         (decode_mips16_operand): New function.
 716         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 717         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 718         Abort for OP_SAVE_RESTORE_LIST.
 719         (print_mips16_insn_arg): Change interface.  Use mips_operand
 720         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 721         (print_insn_mips16): ...here.  Call init_print_arg_state.
 722         Update the call to print_mips16_insn_arg.
 723
 724 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 725
 726         * mips-formats.h: New file.
 727         * mips-opc.c: Include mips-formats.h.
 728         (reg_0_map): New static array.
 729         (decode_mips_operand): New function.
 730         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 731         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 732         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 733         (int_c_map): New static arrays.
 734         (decode_micromips_operand): New function.
 735         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 736         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 737         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 738         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 739         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 740         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 741         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 742         (print_reg): New function.
 743         (mips_print_arg_state): New structure.
 744         (init_print_arg_state, print_insn_arg): New functions.
 745         (print_insn_args): Change interface and use mips_operand structures.
 746         Delete GET_OP_S.  Move GET_OP definition to...
 747         (print_insn_mips): ...here.  Update the call to print_insn_args.
 748         (print_insn_micromips): Use print_insn_args.
 749
 750 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 751
 752         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 753         in macros.
 754
 755 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 756
 757         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 758         ADDA.S, MULA.S and SUBA.S.
 759
 760 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 761
 762         PR gas/13572
 763         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 764         * i386-tbl.h: Regenerated.
 765
 766 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 767
 768         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 769         and SD A(B) macros up.
 770         * micromips-opc.c (micromips_opcodes): Likewise.
 771
 772 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 773
 774         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 775         instructions.
 776
 777 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 778
 779         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 780         MDMX-like instructions.
 781         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 782         printing "Q" operands for INSN_5400 instructions.
 783
 784 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 785
 786         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 787         "+S" for "cins".
 788         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 789         Combine cases.
 790
 791 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 792
 793         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 794         "jalx".
 795         * mips16-opc.c (mips16_opcodes): Likewise.
 796         * micromips-opc.c (micromips_opcodes): Likewise.
 797         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 798         (print_insn_mips16): Handle "+i".
 799         (print_insn_micromips): Likewise.  Conditionally preserve the
 800         ISA bit for "a" but not for "+i".
 801
 802 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 803
 804         * micromips-opc.c (WR_mhi): Rename to..
 805         (WR_mh): ...this.
 806         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 807         "mh,mi" with "mh".
 808         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 809         (micromips_to_32_reg_h_map1): ...this.
 810         (micromips_to_32_reg_i_map): Rename to...
 811         (micromips_to_32_reg_h_map2): ...this.
 812         (print_micromips_insn): Remove "mi" case.  Print both registers
 813         in the pair for "mh".
 814
 815 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 816
 817         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 818         * micromips-opc.c (micromips_opcodes): Likewise.
 819         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 820         and "+T" handling.  Check for a "0" suffix when deciding whether to
 821         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 822
 823 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 824
 825         * s390-opc.c (J12_12, J24_24): New macros.
 826         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 827         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 828         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 829
 830 2013-07-04  Alan Modra  <amodra@gmail.com>
 831
 832         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 833
 834 2013-06-26  Nick Clifton  <nickc@redhat.com>
 835
 836         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 837         field when checking for type 2 nop.
 838         * rx-decode.c: Regenerate.
 839
 840 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 841
 842         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 843         and "movep" macros.
 844
 845 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 846
 847         * mips-dis.c (is_mips16_plt_tail): New function.
 848         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 849         word.
 850         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 851
 852 2013-06-21  DJ Delorie  <dj@redhat.com>
 853
 854         * msp430-decode.opc: New.
 855         * msp430-decode.c: New/generated.
 856         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 857         (MAINTAINER_CLEANFILES): Likewise.
 858         Add rule to build msp430-decode.c frommsp430decode.opc
 859         using the opc2c program.
 860         * Makefile.in: Regenerate.
 861         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 862         * configure: Regenerate.
 863
 864 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 865
 866         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 867         (SYMTAB_AVAILABLE): Removed.
 868         (#include "elf/aarch64.h): Ditto.
 869
 870 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 871             Maciej W. Rozycki  <macro@codesourcery.com>
 872             Chao-Ying Fu  <fu@mips.com>
 873
 874         * micromips-opc.c (EVA): Define.
 875         (TLBINV): Define.
 876         (micromips_opcodes): Add EVA opcodes.
 877         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 878         (print_insn_args): Handle EVA offsets.
 879         (print_insn_micromips): Likewise.
 880         * mips-opc.c (EVA): Define.
 881         (TLBINV): Define.
 882         (mips_builtin_opcodes): Add EVA opcodes.
 883
 884 2013-06-17  Alan Modra  <amodra@gmail.com>
 885
 886         * Makefile.am (mips-opc.lo): Add rules to create automatic
 887         dependency files.  Pass archdefs.
 888         (micromips-opc.lo, mips16-opc.lo): Likewise.
 889         * Makefile.in: Regenerate.
 890
 891 2013-06-14  DJ Delorie  <dj@redhat.com>
 892
 893         * rx-decode.opc (rx_decode_opcode): Bit operations on
 894         registers are 32-bit operations, not 8-bit operations.
 895         * rx-decode.c: Regenerate.
 896
 897 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 898
 899         * micromips-opc.c (IVIRT): New define.
 900         (IVIRT64): New define.
 901         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 902         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 903
 904         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 905         dmtgc0 to print cp0 names.
 906
 907 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 908
 909         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 910         argument.
 911
 912 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 913             Richard Sandiford  <rdsandiford@googlemail.com>
 914
 915         * micromips-opc.c (D32, D33, MC): Update definitions.
 916         (micromips_opcodes):  Initialize ase field.
 917         * mips-dis.c (mips_arch_choice): Add ase field.
 918         (mips_arch_choices): Initialize ase field.
 919         (set_default_mips_dis_options): Declare and setup mips_ase.
 920         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 921         MT32, MC): Update definitions.
 922         (mips_builtin_opcodes): Initialize ase field.
 923
 924 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 925
 926         * s390-opc.txt (flogr): Require a register pair destination.
 927
 928 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 929
 930         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 931         instruction format.
 932
 933 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 934
 935         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 936
 937 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 938
 939         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 940         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 941         XLS_MASK, PPCVSX2): New defines.
 942         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 943         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 944         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 945         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 946         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 947         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 948         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 949         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 950         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 951         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 952         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 953         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 954         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 955         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 956         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 957         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 958         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 959         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 960         <lxvx, stxvx>: New extended mnemonics.
 961
 962 2013-05-17  Alan Modra  <amodra@gmail.com>
 963
 964         * ia64-raw.tbl: Replace non-ASCII char.
 965         * ia64-waw.tbl: Likewise.
 966         * ia64-asmtab.c: Regenerate.
 967
 968 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 969
 970         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 971         * i386-init.h: Regenerated.
 972
 973 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 974
 975         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 976         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 977         check from [0, 255] to [-128, 255].
 978
 979 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 980
 981         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 982         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 983         (parse_mips_dis_option): Handle the virt option.
 984         (print_insn_args): Handle "+J".
 985         (print_mips_disassembler_options): Print out message about virt64.
 986         * mips-opc.c (IVIRT): New define.
 987         (IVIRT64): New define.
 988         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 989         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 990         Move rfe to the bottom as it conflicts with tlbgp.
 991
 992 2013-05-09  Alan Modra  <amodra@gmail.com>
 993
 994         * ppc-opc.c (extract_vlesi): Properly sign extend.
 995         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 996
 997 2013-05-02  Nick Clifton  <nickc@redhat.com>
 998
 999         * msp430-dis.c: Add support for MSP430X instructions.
1000
1001 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
1002
1003         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
1004         to "eccinj".
1005
1006 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
1007
1008         PR binutils/15369
1009         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
1010         of CGEN_CPU_ENDIAN.
1011         (hash_insns_list): Likewise.
1012
1013 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
1014
1015         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
1016         warning workaround.
1017
1018 2013-04-08  Jan Beulich <jbeulich@suse.com>
1019
1020         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
1021         * i386-tbl.h: Re-generate.
1022
1023 2013-04-06  David S. Miller  <davem@davemloft.net>
1024
1025         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
1026         of an opcode, prefer the one with F_PREFERRED set.
1027         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
1028         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
1029         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
1030         mark existing mnenomics as aliases.  Add "cc" suffix to edge
1031         instructions generating condition codes, mark existing mnenomics
1032         as aliases.  Add "fp" prefix to VIS compare instructions, mark
1033         existing mnenomics as aliases.
1034
1035 2013-04-03  Nick Clifton  <nickc@redhat.com>
1036
1037         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
1038         destination address by subtracting the operand from the current
1039         address.
1040         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
1041         a positive value in the insn.
1042         (extract_u16_loop): Do not negate the returned value.
1043         (D16_LOOP): Add V850_INVERSE_PCREL flag.
1044
1045         (ceilf.sw): Remove duplicate entry.
1046         (cvtf.hs): New entry.
1047         (cvtf.sh): Likewise.
1048         (fmaf.s): Likewise.
1049         (fmsf.s): Likewise.
1050         (fnmaf.s): Likewise.
1051         (fnmsf.s): Likewise.
1052         (maddf.s): Restrict to E3V5 architectures.
1053         (msubf.s): Likewise.
1054         (nmaddf.s): Likewise.
1055         (nmsubf.s): Likewise.
1056
1057 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
1058
1059         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
1060         check address mode.
1061         (print_insn): Pass sizeflag to get_sib.
1062
1063 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
1064
1065         PR binutils/15068
1066         * tic6x-dis.c: Add support for displaying 16-bit insns.
1067
1068 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
1069
1070         PR gas/15095
1071         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
1072         individual msb and lsb halves in src1 & src2 fields.  Discard the
1073         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1074         follow what Ti SDK does in that case as any value in the src1
1075         field yields the same output with SDK disassembler.
1076
1077 2013-03-12  Michael Eager <eager@eagercon.com>
1078
1079         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
1080
1081 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1082
1083         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1084
1085 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1086
1087         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1088
1089 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1090
1091         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1092
1093 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1094
1095         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1096         (thumb32_opcodes): Likewise.
1097         (print_insn_thumb32): Handle 'S' control char.
1098
1099 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
1100
1101         * lm32-desc.c: Regenerate.
1102
1103 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1104
1105         * i386-reg.tbl (riz): Add RegRex64.
1106         * i386-tbl.h: Regenerated.
1107
1108 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
1109
1110         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1111         (aarch64_feature_crc): New static.
1112         (CRC): New macro.
1113         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1114         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1115         * aarch64-asm-2.c: Re-generate.
1116         * aarch64-dis-2.c: Ditto.
1117         * aarch64-opc-2.c: Ditto.
1118
1119 2013-02-27  Alan Modra  <amodra@gmail.com>
1120
1121         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1122         * rl78-decode.c: Regenerate.
1123
1124 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
1125
1126         * rl78-decode.opc: Fix encoding of DIVWU insn.
1127         * rl78-decode.c: Regenerate.
1128
1129 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
1130
1131         PR gas/15159
1132         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1133
1134         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1135         (cpu_flags): Add CpuSMAP.
1136
1137         * i386-opc.h (CpuSMAP): New.
1138         (i386_cpu_flags): Add cpusmap.
1139
1140         * i386-opc.tbl: Add clac and stac.
1141
1142         * i386-init.h: Regenerated.
1143         * i386-tbl.h: Likewise.
1144
1145 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
1146
1147         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1148         which also makes the disassembler output be in little
1149         endian like it should be.
1150
1151 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
1152
1153         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1154         fields to NULL.
1155         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1156
1157 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
1158
1159         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1160         section disassembled.
1161
1162 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1163
1164         * arm-dis.c: Update strht pattern.
1165
1166 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
1167
1168         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1169         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
1170         trunc.w.s macro for EE.
1171
1172 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
1173             Andrew Jenner <andrew@codesourcery.com>
1174
1175         Based on patches from Altera Corporation.
1176
1177         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1178         nios2-opc.c.
1179         * Makefile.in: Regenerated.
1180         * configure.in: Add case for bfd_nios2_arch.
1181         * configure: Regenerated.
1182         * disassemble.c (ARCH_nios2): Define.
1183         (disassembler): Add case for bfd_arch_nios2.
1184         * nios2-dis.c: New file.
1185         * nios2-opc.c: New file.
1186
1187 2013-02-04  Alan Modra  <amodra@gmail.com>
1188
1189         * po/POTFILES.in: Regenerate.
1190         * rl78-decode.c: Regenerate.
1191         * rx-decode.c: Regenerate.
1192
1193 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1194
1195         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1196         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1197         * aarch64-asm.c (convert_xtl_to_shll): New function.
1198         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1199         calling convert_xtl_to_shll.
1200         * aarch64-dis.c (convert_shll_to_xtl): New function.
1201         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1202         calling convert_shll_to_xtl.
1203         * aarch64-gen.c: Update copyright year.
1204         * aarch64-asm-2.c: Re-generate.
1205         * aarch64-dis-2.c: Re-generate.
1206         * aarch64-opc-2.c: Re-generate.
1207
1208 2013-01-24  Nick Clifton  <nickc@redhat.com>
1209
1210         * v850-dis.c: Add support for e3v5 architecture.
1211         * v850-opc.c: Likewise.
1212
1213 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1214
1215         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1216         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1217         * aarch64-opc.c (operand_general_constraint_met_p): For
1218         AARCH64_MOD_LSL, move the range check on the shift amount before the
1219         alignment check; change to call set_sft_amount_out_of_range_error
1220         instead of set_imm_out_of_range_error.
1221         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1222         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1223         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1224         SIMD_IMM_SFT.
1225
1226 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1227
1228         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1229
1230         * i386-init.h: Regenerated.
1231         * i386-tbl.h: Likewise.
1232
1233 2013-01-15  Nick Clifton  <nickc@redhat.com>
1234
1235         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1236         values.
1237         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1238
1239 2013-01-14  Will Newton <will.newton@imgtec.com>
1240
1241         * metag-dis.c (REG_WIDTH): Increase to 64.
1242
1243 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1244
1245         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1246         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1247         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1248         (SH6): Update.
1249         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1250         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1251         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1252         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1253
1254 2013-01-10  Will Newton <will.newton@imgtec.com>
1255
1256         * Makefile.am: Add Meta.
1257         * configure.in: Add Meta.
1258         * disassemble.c: Add Meta support.
1259         * metag-dis.c: New file.
1260         * Makefile.in: Regenerate.
1261         * configure: Regenerate.
1262
1263 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1264
1265         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1266         (match_opcode): Rename to cr16_match_opcode.
1267
1268 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1269
1270         * mips-dis.c: Add names for CP0 registers of r5900.
1271         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1272         instructions sq and lq.
1273         Add support for MIPS r5900 CPU.
1274         Add support for 128 bit MMI (Multimedia Instructions).
1275         Add support for EE instructions (Emotion Engine).
1276         Disable unsupported floating point instructions (64 bit and
1277         undefined compare operations).
1278         Enable instructions of MIPS ISA IV which are supported by r5900.
1279         Disable 64 bit co processor instructions.
1280         Disable 64 bit multiplication and division instructions.
1281         Disable instructions for co-processor 2 and 3, because these are
1282         not supported (preparation for later VU0 support (Vector Unit)).
1283         Disable cvt.w.s because this behaves like trunc.w.s and the
1284         correct execution can't be ensured on r5900.
1285         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1286         will confuse less developers and compilers.
1287
1288 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1289
1290         * aarch64-opc.c (aarch64_print_operand): Change to print
1291         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1292         in comment.
1293         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1294         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1295         OP_MOV_IMM_WIDE.
1296
1297 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1298
1299         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1300         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1301
1302 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1303
1304         * i386-gen.c (process_copyright): Update copyright year to 2013.
1305
1306 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1307
1308         * cr16-dis.c (match_opcode,make_instruction): Remove static
1309         declaration.
1310         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1311         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1312
1313 For older changes see ChangeLog-2012
1314 \f
1315 Copyright (C) 2013 Free Software Foundation, Inc.
1316
1317 Copying and distribution of this file, with or without modification,
1318 are permitted in any medium without royalty provided the copyright
1319 notice and this notice are preserved.
1320
1321 Local Variables:
1322 mode: change-log
1323 left-margin: 8
1324 fill-column: 74
1325 version-control: never
1326 End: