opcodes/ChangeLog

   1 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
   2
   3         * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
   4         (convert_from_csel): Likewise.
   5         * aarch64-opc.c (operand_general_constraint_met_p): Handle
   6         AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
   7         (aarch64_print_operand): Handle AARCH64_OPND_COND1.
   8         * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
   9         COND for cinc, cset, cinv, csetm and cneg.
  10         (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
  11         * aarch64-asm-2.c: Re-generated.
  12         * aarch64-dis-2.c: Ditto.
  13         * aarch64-opc-2.c: Ditto.
  14
  15 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  16
  17         * aarch64-opc.c (set_syntax_error): New function.
  18         (operand_general_constraint_met_p): Replace set_other_error
  19         with set_syntax_error.
  20
  21 2013-10-30  Andreas Arnez  <arnez@linux.vnet.ibm.com>
  22
  23         * s390-dis.c (init_disasm): Default to full 'zarch' opcode
  24         availability even for 31-bit programs.
  25
  26 2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
  27
  28         * arm-dis.c (neon_opcodes): Adjust print string for vshll.
  29
  30 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
  31
  32         * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
  33         +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
  34         +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
  35         (MSA): New define.
  36         (MSA64): New define.
  37         (micromips_opcodes): Add MSA instructions.
  38         * mips-dis.c (msa_control_names): New array.
  39         (mips_abi_choice): Add ASE_MSA to mips32r2.
  40         Remove ASE_MDMX from mips64r2.
  41         Add ASE_MSA and ASE_MSA64 to mips64r2.
  42         (parse_mips_dis_option): Handle -Mmsa.
  43         (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
  44         (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
  45         (print_mips_disassembler_options): Print -Mmsa.
  46         * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
  47         +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
  48         (MSA): New define.
  49         (MSA64): New define.
  50         (mips_builtin_op): Add MSA instructions.
  51
  52 2013-10-13  Sandra Loosemore  <sandra@codesourcery.com>
  53
  54         * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
  55         as the primary name of r30.
  56
  57 2013-10-12  Jan Beulich <jbeulich@suse.com>
  58
  59         * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
  60         default case.
  61         (OP_E_register): Move v_bnd_mode alongside m_mode.
  62         * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
  63         Drop Reg16 and Disp16. Add NoRex64.
  64         (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
  65         * i386-tbl.h: Re-generate.
  66
  67 2013-10-10  Sean Keys <skeys@ipdatasys.com>
  68
  69         * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
  70         table.
  71         * xgate-dis.c (print_insn): Refactor to work with table change.
  72
  73 2013-10-10  Roland McGrath  <mcgrathr@google.com>
  74
  75         * i386-dis.c (oappend_maybe_intel): New function.
  76         (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
  77         (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
  78         (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
  79
  80         * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
  81         possible compiler warnings when the union's initializer is
  82         actually meant for the 'preg' enum typed member.
  83         * crx-opc.c (REG): Likewise.
  84
  85         * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
  86         Remove duplicate const qualifier.
  87
  88 2013-10-08  Jan Beulich <jbeulich@suse.com>
  89
  90         * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
  91         (clflush): Use Anysize instead of Byte|Unspecified.
  92         (prefetch*): Likewise.
  93         * i386-tbl.h: Re-generate.
  94
  95 2013-10-07  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
  96
  97         * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
  98
  99 2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 100
 101         * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
 102         * i386-init.h: Regenerated.
 103
 104 2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 105
 106         * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
 107         * i386-init.h: Regenerated.
 108
 109 2013-09-20  Alan Modra  <amodra@gmail.com>
 110
 111         * configure: Regenerate.
 112
 113 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 114
 115         * s390-opc.txt (clih): Make the immediate unsigned.
 116
 117 2013-09-04  Roland McGrath  <mcgrathr@google.com>
 118
 119         PR gas/15914
 120         * arm-dis.c (arm_opcodes): Add udf.
 121         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
 122         (thumb32_opcodes): Add udf.w.
 123         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
 124
 125 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 126
 127         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
 128         For the load fp integer instructions only the suppression flag was
 129         new with z196 version.
 130
 131 2013-08-28  Nick Clifton  <nickc@redhat.com>
 132
 133         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
 134         immediate is not suitable for the 32-bit ABI.
 135
 136 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
 137
 138         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
 139         replacing NODS.
 140
 141 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
 142
 143         PR binutils/15834
 144         * aarch64-asm.c: Fix typos.
 145         * aarch64-dis.c: Likewise.
 146         * msp430-dis.c: Likewise.
 147
 148 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 149
 150         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
 151         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
 152         Use +H rather than +C for the real "dext".
 153         * mips-opc.c (mips_builtin_opcodes): Likewise.
 154
 155 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 156
 157         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
 158         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
 159         and OPTIONAL_MAPPED_REG.
 160         * mips-opc.c (decode_mips_operand): Likewise.
 161         * mips16-opc.c (decode_mips16_operand): Likewise.
 162         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
 163
 164 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
 165
 166         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
 167         (PREFIX_EVEX_0F3A3F): Likewise.
 168         * i386-dis-evex.h (evex_table): Updated.
 169
 170 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
 171
 172         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
 173         VCLIPW.
 174
 175 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
 176             Konrad Eisele  <konrad@gaisler.com>
 177
 178         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
 179         bfd_mach_sparc.
 180         * sparc-opc.c (MASK_LEON): Define.
 181         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
 182         (letandleon): New macro.
 183         (v9andleon): Likewise.
 184         (sparc_opc): Add leon.
 185         (umac): Enable for letandleon.
 186         (smac): Likewise.
 187         (casa): Enable for v9andleon.
 188         (cas): Likewise.
 189         (casl): Likewise.
 190
 191 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 192             Richard Sandiford  <rdsandiford@googlemail.com>
 193
 194         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
 195         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
 196         (print_vu0_channel): New function.
 197         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
 198         (print_insn_args): Handle '#'.
 199         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
 200         * mips-opc.c (mips_vu0_channel_mask): New constant.
 201         (decode_mips_operand): Handle new VU0 operand types.
 202         (VU0, VU0CH): New macros.
 203         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
 204         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
 205         Use "+6" rather than "G" for QMFC2 and QMTC2.
 206
 207 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 208
 209         * mips-formats.h (PCREL): Reorder parameters and update the definition
 210         to match new mips_pcrel_operand layout.
 211         (JUMP, JALX, BRANCH): Update accordingly.
 212         * mips16-opc.c (decode_mips16_operand): Likewise.
 213
 214 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 215
 216         * micromips-opc.c (WR_s): Delete.
 217
 218 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 219
 220         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 221         New macros.
 222         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 223         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 224         (mips_builtin_opcodes): Use the new position-based read-write flags
 225         instead of field-based ones.  Use UDI for "udi..." instructions.
 226         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 227         New macros.
 228         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 229         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 230         (WR_SP, RD_16): New macros.
 231         (RD_SP): Redefine as an INSN2_* flag.
 232         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 233         (mips16_opcodes): Use the new position-based read-write flags
 234         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 235         pinfo2 field.
 236         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 237         New macros.
 238         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 239         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 240         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 241         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 242         (micromips_opcodes): Use the new position-based read-write flags
 243         instead of field-based ones.
 244         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 245         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 246         of field-based flags.
 247
 248 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 249
 250         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 251         (WR_SP): Replace with...
 252         (MOD_SP): ...this.
 253         (mips16_opcodes): Update accordingly.
 254         * mips-dis.c (print_insn_mips16): Likewise.
 255
 256 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 257
 258         * mips16-opc.c (mips16_opcodes): Reformat.
 259
 260 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 261
 262         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 263         for operands that are hard-coded to $0.
 264         * micromips-opc.c (micromips_opcodes): Likewise.
 265
 266 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 267
 268         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 269         for the single-operand forms of JALR and JALR.HB.
 270         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 271         and JALRS.HB.
 272
 273 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 274
 275         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 276         instructions.  Fix them to use WR_MACC instead of WR_CC and
 277         add missing RD_MACCs.
 278
 279 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 280
 281         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 282
 283 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 284
 285         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 286
 287 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 288             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 289             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 290             Sergey Lega  <sergey.s.lega@intel.com>
 291             Anna Tikhonova  <anna.tikhonova@intel.com>
 292             Ilya Tocar  <ilya.tocar@intel.com>
 293             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 294             Ilya Verbin  <ilya.verbin@intel.com>
 295             Kirill Yukhin  <kirill.yukhin@intel.com>
 296             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 297
 298         * i386-dis-evex.h: New.
 299         * i386-dis.c (OP_Rounding): New.
 300         (VPCMP_Fixup): New.
 301         (OP_Mask): New.
 302         (Rdq): New.
 303         (XMxmmq): New.
 304         (EXdScalarS): New.
 305         (EXymm): New.
 306         (EXEvexHalfBcstXmmq): New.
 307         (EXxmm_mdq): New.
 308         (EXEvexXGscat): New.
 309         (EXEvexXNoBcst): New.
 310         (VPCMP): New.
 311         (EXxEVexR): New.
 312         (EXxEVexS): New.
 313         (XMask): New.
 314         (MaskG): New.
 315         (MaskE): New.
 316         (MaskR): New.
 317         (MaskVex): New.
 318         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 319         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 320         evex_rounding_mode, evex_sae_mode, mask_mode.
 321         (USE_EVEX_TABLE): New.
 322         (EVEX_TABLE): New.
 323         (EVEX enum): New.
 324         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 325         REG_EVEX_0F38C7.
 326         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 327         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 328         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 329         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 330         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 331         MOD_EVEX_0F38C7_REG_6.
 332         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 333         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 334         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 335         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 336         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 337         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 338         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 339         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 340         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 341         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 342         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 343         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 344         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 345         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 346         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 347         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 348         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 349         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 350         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 351         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 352         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 353         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 354         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 355         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 356         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 357         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 358         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 359         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 360         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 361         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 362         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 363         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 364         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 365         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 366         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 367         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 368         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 369         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 370         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 371         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 372         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 373         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 374         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 375         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 376         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 377         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 378         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 379         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 380         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 381         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 382         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 383         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 384         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 385         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 386         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 387         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 388         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 389         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 390         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 391         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 392         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 393         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 394         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 395         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 396         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 397         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 398         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 399         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 400         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 401         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 402         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 403         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 404         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 405         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 406         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 407         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 408         PREFIX_EVEX_0F3A55.
 409         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 410         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 411         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 412         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 413         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 414         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 415         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 416         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 417         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 418         VEX_W_0F3A32_P_2_LEN_0.
 419         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 420         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 421         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 422         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 423         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 424         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 425         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 426         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 427         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 428         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 429         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 430         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 431         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 432         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 433         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 434         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 435         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 436         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 437         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 438         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 439         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 440         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 441         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 442         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 443         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 444         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 445         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 446         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 447         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 448         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 449         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 450         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 451         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 452         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 453         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 454         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 455         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 456         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 457         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 458         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 459         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 460         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 461         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 462         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 463         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 464         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 465         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 466         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 467         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 468         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 469         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 470         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 471         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 472         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 473         (struct vex): Add fields evex, r, v, mask_register_specifier,
 474         zeroing, ll, b.
 475         (intel_names_xmm): Add upper 16 registers.
 476         (att_names_xmm): Ditto.
 477         (intel_names_ymm): Ditto.
 478         (att_names_ymm): Ditto.
 479         (names_zmm): New.
 480         (intel_names_zmm): Ditto.
 481         (att_names_zmm): Ditto.
 482         (names_mask): Ditto.
 483         (intel_names_mask): Ditto.
 484         (att_names_mask): Ditto.
 485         (names_rounding): Ditto.
 486         (names_broadcast): Ditto.
 487         (x86_64_table): Add escape to evex-table.
 488         (reg_table): Include reg_table evex-entries from
 489         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 490         (prefix_table): Add entries for new instructions.
 491         (vex_table): Ditto.
 492         (vex_len_table): Ditto.
 493         (vex_w_table): Ditto.
 494         (mod_table): Ditto.
 495         (get_valid_dis386): Properly handle new instructions.
 496         (print_insn): Handle zmm and mask registers, print mask operand.
 497         (intel_operand_size): Support EVEX, new modes and sizes.
 498         (OP_E_register): Handle new modes.
 499         (OP_E_memory): Ditto.
 500         (OP_G): Ditto.
 501         (OP_XMM): Ditto.
 502         (OP_EX): Ditto.
 503         (OP_VEX): Ditto.
 504         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 505         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 506         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 507         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 508         CpuAVX512PF and CpuVREX.
 509         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 510         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 511         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 512         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 513         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 514         * i386-init.h: Regenerate.
 515         * i386-opc.h (CpuAVX512F): New.
 516         (CpuAVX512CD): New.
 517         (CpuAVX512ER): New.
 518         (CpuAVX512PF): New.
 519         (CpuVREX): New.
 520         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 521         cpuavx512pf and cpuvrex fields.
 522         (VecSIB): Add VecSIB512.
 523         (EVex): New.
 524         (Masking): New.
 525         (VecESize): New.
 526         (Broadcast): New.
 527         (StaticRounding): New.
 528         (SAE): New.
 529         (Disp8MemShift): New.
 530         (NoDefMask): New.
 531         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 532         staticrounding, sae, disp8memshift and nodefmask.
 533         (RegZMM): New.
 534         (Zmmword): Ditto.
 535         (Vec_Disp8): Ditto.
 536         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 537         fields.
 538         (RegVRex): New.
 539         * i386-opc.tbl: Add AVX512 instructions.
 540         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 541         registers, mask registers.
 542         * i386-tbl.h: Regenerate.
 543
 544 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 545
 546         PR gas/15220
 547         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 548         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 549
 550 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 551
 552         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 553         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 554         PREFIX_0F3ACC.
 555         (prefix_table): Updated.
 556         (three_byte_table): Likewise.
 557         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 558         (cpu_flags): Add CpuSHA.
 559         (i386_cpu_flags): Add cpusha.
 560         * i386-init.h: Regenerate.
 561         * i386-opc.h (CpuSHA): New.
 562         (CpuUnused): Restored.
 563         (i386_cpu_flags): Add cpusha.
 564         * i386-opc.tbl: Add SHA instructions.
 565         * i386-tbl.h: Regenerate.
 566
 567 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 568             Kirill Yukhin  <kirill.yukhin@intel.com>
 569             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 570
 571         * i386-dis.c (BND_Fixup): New.
 572         (Ebnd): New.
 573         (Ev_bnd): New.
 574         (Gbnd): New.
 575         (BND): New.
 576         (v_bnd_mode): New.
 577         (bnd_mode): New.
 578         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 579         MOD_0F1B_PREFIX_1.
 580         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 581         (dis tables): Replace XX with BND for near branch and call
 582         instructions.
 583         (prefix_table): Add new entries.
 584         (mod_table): Likewise.
 585         (names_bnd): New.
 586         (intel_names_bnd): New.
 587         (att_names_bnd): New.
 588         (BND_PREFIX): New.
 589         (prefix_name): Handle BND_PREFIX.
 590         (print_insn): Initialize names_bnd.
 591         (intel_operand_size): Handle new modes.
 592         (OP_E_register): Likewise.
 593         (OP_E_memory): Likewise.
 594         (OP_G): Likewise.
 595         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 596         (cpu_flags): Add CpuMPX.
 597         (operand_type_init): Add RegBND.
 598         (opcode_modifiers): Add BNDPrefixOk.
 599         (operand_types): Add RegBND.
 600         * i386-init.h: Regenerate.
 601         * i386-opc.h (CpuMPX): New.
 602         (CpuUnused): Comment out.
 603         (i386_cpu_flags): Add cpumpx.
 604         (BNDPrefixOk): New.
 605         (i386_opcode_modifier): Add bndprefixok.
 606         (RegBND): New.
 607         (i386_operand_type): Add regbnd.
 608         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 609         Add MPX instructions and bnd prefix.
 610         * i386-reg.tbl: Add bnd0-bnd3 registers.
 611         * i386-tbl.h: Regenerate.
 612
 613 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 614
 615         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 616         ATTRIBUTE_UNUSED.
 617
 618 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 619
 620         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 621         special rules.
 622         * Makefile.in: Regenerate.
 623         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 624         all fields.  Reformat.
 625
 626 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 627
 628         * mips16-opc.c: Include mips-formats.h.
 629         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 630         static arrays.
 631         (decode_mips16_operand): New function.
 632         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 633         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 634         Abort for OP_SAVE_RESTORE_LIST.
 635         (print_mips16_insn_arg): Change interface.  Use mips_operand
 636         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 637         (print_insn_mips16): ...here.  Call init_print_arg_state.
 638         Update the call to print_mips16_insn_arg.
 639
 640 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 641
 642         * mips-formats.h: New file.
 643         * mips-opc.c: Include mips-formats.h.
 644         (reg_0_map): New static array.
 645         (decode_mips_operand): New function.
 646         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 647         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 648         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 649         (int_c_map): New static arrays.
 650         (decode_micromips_operand): New function.
 651         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 652         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 653         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 654         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 655         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 656         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 657         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 658         (print_reg): New function.
 659         (mips_print_arg_state): New structure.
 660         (init_print_arg_state, print_insn_arg): New functions.
 661         (print_insn_args): Change interface and use mips_operand structures.
 662         Delete GET_OP_S.  Move GET_OP definition to...
 663         (print_insn_mips): ...here.  Update the call to print_insn_args.
 664         (print_insn_micromips): Use print_insn_args.
 665
 666 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 667
 668         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 669         in macros.
 670
 671 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 672
 673         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 674         ADDA.S, MULA.S and SUBA.S.
 675
 676 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 677
 678         PR gas/13572
 679         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 680         * i386-tbl.h: Regenerated.
 681
 682 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 683
 684         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 685         and SD A(B) macros up.
 686         * micromips-opc.c (micromips_opcodes): Likewise.
 687
 688 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 689
 690         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 691         instructions.
 692
 693 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 694
 695         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 696         MDMX-like instructions.
 697         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 698         printing "Q" operands for INSN_5400 instructions.
 699
 700 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 701
 702         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 703         "+S" for "cins".
 704         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 705         Combine cases.
 706
 707 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 708
 709         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 710         "jalx".
 711         * mips16-opc.c (mips16_opcodes): Likewise.
 712         * micromips-opc.c (micromips_opcodes): Likewise.
 713         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 714         (print_insn_mips16): Handle "+i".
 715         (print_insn_micromips): Likewise.  Conditionally preserve the
 716         ISA bit for "a" but not for "+i".
 717
 718 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 719
 720         * micromips-opc.c (WR_mhi): Rename to..
 721         (WR_mh): ...this.
 722         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 723         "mh,mi" with "mh".
 724         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 725         (micromips_to_32_reg_h_map1): ...this.
 726         (micromips_to_32_reg_i_map): Rename to...
 727         (micromips_to_32_reg_h_map2): ...this.
 728         (print_micromips_insn): Remove "mi" case.  Print both registers
 729         in the pair for "mh".
 730
 731 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 732
 733         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 734         * micromips-opc.c (micromips_opcodes): Likewise.
 735         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 736         and "+T" handling.  Check for a "0" suffix when deciding whether to
 737         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 738
 739 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 740
 741         * s390-opc.c (J12_12, J24_24): New macros.
 742         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 743         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 744         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 745
 746 2013-07-04  Alan Modra  <amodra@gmail.com>
 747
 748         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 749
 750 2013-06-26  Nick Clifton  <nickc@redhat.com>
 751
 752         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 753         field when checking for type 2 nop.
 754         * rx-decode.c: Regenerate.
 755
 756 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 757
 758         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 759         and "movep" macros.
 760
 761 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 762
 763         * mips-dis.c (is_mips16_plt_tail): New function.
 764         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 765         word.
 766         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 767
 768 2013-06-21  DJ Delorie  <dj@redhat.com>
 769
 770         * msp430-decode.opc: New.
 771         * msp430-decode.c: New/generated.
 772         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 773         (MAINTAINER_CLEANFILES): Likewise.
 774         Add rule to build msp430-decode.c frommsp430decode.opc
 775         using the opc2c program.
 776         * Makefile.in: Regenerate.
 777         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 778         * configure: Regenerate.
 779
 780 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 781
 782         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 783         (SYMTAB_AVAILABLE): Removed.
 784         (#include "elf/aarch64.h): Ditto.
 785
 786 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 787             Maciej W. Rozycki  <macro@codesourcery.com>
 788             Chao-Ying Fu  <fu@mips.com>
 789
 790         * micromips-opc.c (EVA): Define.
 791         (TLBINV): Define.
 792         (micromips_opcodes): Add EVA opcodes.
 793         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 794         (print_insn_args): Handle EVA offsets.
 795         (print_insn_micromips): Likewise.
 796         * mips-opc.c (EVA): Define.
 797         (TLBINV): Define.
 798         (mips_builtin_opcodes): Add EVA opcodes.
 799
 800 2013-06-17  Alan Modra  <amodra@gmail.com>
 801
 802         * Makefile.am (mips-opc.lo): Add rules to create automatic
 803         dependency files.  Pass archdefs.
 804         (micromips-opc.lo, mips16-opc.lo): Likewise.
 805         * Makefile.in: Regenerate.
 806
 807 2013-06-14  DJ Delorie  <dj@redhat.com>
 808
 809         * rx-decode.opc (rx_decode_opcode): Bit operations on
 810         registers are 32-bit operations, not 8-bit operations.
 811         * rx-decode.c: Regenerate.
 812
 813 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 814
 815         * micromips-opc.c (IVIRT): New define.
 816         (IVIRT64): New define.
 817         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 818         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 819
 820         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 821         dmtgc0 to print cp0 names.
 822
 823 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 824
 825         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 826         argument.
 827
 828 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 829             Richard Sandiford  <rdsandiford@googlemail.com>
 830
 831         * micromips-opc.c (D32, D33, MC): Update definitions.
 832         (micromips_opcodes):  Initialize ase field.
 833         * mips-dis.c (mips_arch_choice): Add ase field.
 834         (mips_arch_choices): Initialize ase field.
 835         (set_default_mips_dis_options): Declare and setup mips_ase.
 836         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 837         MT32, MC): Update definitions.
 838         (mips_builtin_opcodes): Initialize ase field.
 839
 840 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 841
 842         * s390-opc.txt (flogr): Require a register pair destination.
 843
 844 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 845
 846         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 847         instruction format.
 848
 849 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 850
 851         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 852
 853 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 854
 855         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 856         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 857         XLS_MASK, PPCVSX2): New defines.
 858         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 859         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 860         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 861         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 862         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 863         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 864         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 865         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 866         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 867         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 868         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 869         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 870         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 871         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 872         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 873         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 874         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 875         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 876         <lxvx, stxvx>: New extended mnemonics.
 877
 878 2013-05-17  Alan Modra  <amodra@gmail.com>
 879
 880         * ia64-raw.tbl: Replace non-ASCII char.
 881         * ia64-waw.tbl: Likewise.
 882         * ia64-asmtab.c: Regenerate.
 883
 884 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 885
 886         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 887         * i386-init.h: Regenerated.
 888
 889 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 890
 891         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 892         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 893         check from [0, 255] to [-128, 255].
 894
 895 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 896
 897         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 898         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 899         (parse_mips_dis_option): Handle the virt option.
 900         (print_insn_args): Handle "+J".
 901         (print_mips_disassembler_options): Print out message about virt64.
 902         * mips-opc.c (IVIRT): New define.
 903         (IVIRT64): New define.
 904         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 905         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 906         Move rfe to the bottom as it conflicts with tlbgp.
 907
 908 2013-05-09  Alan Modra  <amodra@gmail.com>
 909
 910         * ppc-opc.c (extract_vlesi): Properly sign extend.
 911         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 912
 913 2013-05-02  Nick Clifton  <nickc@redhat.com>
 914
 915         * msp430-dis.c: Add support for MSP430X instructions.
 916
 917 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 918
 919         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 920         to "eccinj".
 921
 922 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 923
 924         PR binutils/15369
 925         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 926         of CGEN_CPU_ENDIAN.
 927         (hash_insns_list): Likewise.
 928
 929 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 930
 931         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 932         warning workaround.
 933
 934 2013-04-08  Jan Beulich <jbeulich@suse.com>
 935
 936         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 937         * i386-tbl.h: Re-generate.
 938
 939 2013-04-06  David S. Miller  <davem@davemloft.net>
 940
 941         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 942         of an opcode, prefer the one with F_PREFERRED set.
 943         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 944         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 945         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 946         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 947         instructions generating condition codes, mark existing mnenomics
 948         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 949         existing mnenomics as aliases.
 950
 951 2013-04-03  Nick Clifton  <nickc@redhat.com>
 952
 953         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 954         destination address by subtracting the operand from the current
 955         address.
 956         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 957         a positive value in the insn.
 958         (extract_u16_loop): Do not negate the returned value.
 959         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 960
 961         (ceilf.sw): Remove duplicate entry.
 962         (cvtf.hs): New entry.
 963         (cvtf.sh): Likewise.
 964         (fmaf.s): Likewise.
 965         (fmsf.s): Likewise.
 966         (fnmaf.s): Likewise.
 967         (fnmsf.s): Likewise.
 968         (maddf.s): Restrict to E3V5 architectures.
 969         (msubf.s): Likewise.
 970         (nmaddf.s): Likewise.
 971         (nmsubf.s): Likewise.
 972
 973 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 974
 975         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 976         check address mode.
 977         (print_insn): Pass sizeflag to get_sib.
 978
 979 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 980
 981         PR binutils/15068
 982         * tic6x-dis.c: Add support for displaying 16-bit insns.
 983
 984 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 985
 986         PR gas/15095
 987         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 988         individual msb and lsb halves in src1 & src2 fields.  Discard the
 989         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 990         follow what Ti SDK does in that case as any value in the src1
 991         field yields the same output with SDK disassembler.
 992
 993 2013-03-12  Michael Eager <eager@eagercon.com>
 994
 995         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 996
 997 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 998
 999         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1000
1001 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1002
1003         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1004
1005 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1006
1007         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1008
1009 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1010
1011         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1012         (thumb32_opcodes): Likewise.
1013         (print_insn_thumb32): Handle 'S' control char.
1014
1015 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
1016
1017         * lm32-desc.c: Regenerate.
1018
1019 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1020
1021         * i386-reg.tbl (riz): Add RegRex64.
1022         * i386-tbl.h: Regenerated.
1023
1024 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
1025
1026         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1027         (aarch64_feature_crc): New static.
1028         (CRC): New macro.
1029         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1030         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1031         * aarch64-asm-2.c: Re-generate.
1032         * aarch64-dis-2.c: Ditto.
1033         * aarch64-opc-2.c: Ditto.
1034
1035 2013-02-27  Alan Modra  <amodra@gmail.com>
1036
1037         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1038         * rl78-decode.c: Regenerate.
1039
1040 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
1041
1042         * rl78-decode.opc: Fix encoding of DIVWU insn.
1043         * rl78-decode.c: Regenerate.
1044
1045 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
1046
1047         PR gas/15159
1048         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1049
1050         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1051         (cpu_flags): Add CpuSMAP.
1052
1053         * i386-opc.h (CpuSMAP): New.
1054         (i386_cpu_flags): Add cpusmap.
1055
1056         * i386-opc.tbl: Add clac and stac.
1057
1058         * i386-init.h: Regenerated.
1059         * i386-tbl.h: Likewise.
1060
1061 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
1062
1063         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1064         which also makes the disassembler output be in little
1065         endian like it should be.
1066
1067 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
1068
1069         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1070         fields to NULL.
1071         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1072
1073 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
1074
1075         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1076         section disassembled.
1077
1078 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1079
1080         * arm-dis.c: Update strht pattern.
1081
1082 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
1083
1084         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1085         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
1086         trunc.w.s macro for EE.
1087
1088 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
1089             Andrew Jenner <andrew@codesourcery.com>
1090
1091         Based on patches from Altera Corporation.
1092
1093         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1094         nios2-opc.c.
1095         * Makefile.in: Regenerated.
1096         * configure.in: Add case for bfd_nios2_arch.
1097         * configure: Regenerated.
1098         * disassemble.c (ARCH_nios2): Define.
1099         (disassembler): Add case for bfd_arch_nios2.
1100         * nios2-dis.c: New file.
1101         * nios2-opc.c: New file.
1102
1103 2013-02-04  Alan Modra  <amodra@gmail.com>
1104
1105         * po/POTFILES.in: Regenerate.
1106         * rl78-decode.c: Regenerate.
1107         * rx-decode.c: Regenerate.
1108
1109 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1110
1111         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1112         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1113         * aarch64-asm.c (convert_xtl_to_shll): New function.
1114         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1115         calling convert_xtl_to_shll.
1116         * aarch64-dis.c (convert_shll_to_xtl): New function.
1117         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1118         calling convert_shll_to_xtl.
1119         * aarch64-gen.c: Update copyright year.
1120         * aarch64-asm-2.c: Re-generate.
1121         * aarch64-dis-2.c: Re-generate.
1122         * aarch64-opc-2.c: Re-generate.
1123
1124 2013-01-24  Nick Clifton  <nickc@redhat.com>
1125
1126         * v850-dis.c: Add support for e3v5 architecture.
1127         * v850-opc.c: Likewise.
1128
1129 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1130
1131         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1132         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1133         * aarch64-opc.c (operand_general_constraint_met_p): For
1134         AARCH64_MOD_LSL, move the range check on the shift amount before the
1135         alignment check; change to call set_sft_amount_out_of_range_error
1136         instead of set_imm_out_of_range_error.
1137         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1138         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1139         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1140         SIMD_IMM_SFT.
1141
1142 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1143
1144         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1145
1146         * i386-init.h: Regenerated.
1147         * i386-tbl.h: Likewise.
1148
1149 2013-01-15  Nick Clifton  <nickc@redhat.com>
1150
1151         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1152         values.
1153         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1154
1155 2013-01-14  Will Newton <will.newton@imgtec.com>
1156
1157         * metag-dis.c (REG_WIDTH): Increase to 64.
1158
1159 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1160
1161         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1162         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1163         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1164         (SH6): Update.
1165         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1166         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1167         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1168         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1169
1170 2013-01-10  Will Newton <will.newton@imgtec.com>
1171
1172         * Makefile.am: Add Meta.
1173         * configure.in: Add Meta.
1174         * disassemble.c: Add Meta support.
1175         * metag-dis.c: New file.
1176         * Makefile.in: Regenerate.
1177         * configure: Regenerate.
1178
1179 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1180
1181         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1182         (match_opcode): Rename to cr16_match_opcode.
1183
1184 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1185
1186         * mips-dis.c: Add names for CP0 registers of r5900.
1187         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1188         instructions sq and lq.
1189         Add support for MIPS r5900 CPU.
1190         Add support for 128 bit MMI (Multimedia Instructions).
1191         Add support for EE instructions (Emotion Engine).
1192         Disable unsupported floating point instructions (64 bit and
1193         undefined compare operations).
1194         Enable instructions of MIPS ISA IV which are supported by r5900.
1195         Disable 64 bit co processor instructions.
1196         Disable 64 bit multiplication and division instructions.
1197         Disable instructions for co-processor 2 and 3, because these are
1198         not supported (preparation for later VU0 support (Vector Unit)).
1199         Disable cvt.w.s because this behaves like trunc.w.s and the
1200         correct execution can't be ensured on r5900.
1201         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1202         will confuse less developers and compilers.
1203
1204 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1205
1206         * aarch64-opc.c (aarch64_print_operand): Change to print
1207         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1208         in comment.
1209         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1210         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1211         OP_MOV_IMM_WIDE.
1212
1213 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1214
1215         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1216         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1217
1218 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1219
1220         * i386-gen.c (process_copyright): Update copyright year to 2013.
1221
1222 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1223
1224         * cr16-dis.c (match_opcode,make_instruction): Remove static
1225         declaration.
1226         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1227         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1228
1229 For older changes see ChangeLog-2012
1230 \f
1231 Copyright (C) 2013 Free Software Foundation, Inc.
1232
1233 Copying and distribution of this file, with or without modification,
1234 are permitted in any medium without royalty provided the copyright
1235 notice and this notice are preserved.
1236
1237 Local Variables:
1238 mode: change-log
1239 left-margin: 8
1240 fill-column: 74
1241 version-control: never
1242 End: