opcodes/ChangeLog

   1 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
   2
   3         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
   4         * i386-init.h: Regenerated.
   5
   6 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         PR binutils/13571
   9         * i386-dis.c (MOD_0FC3): New.
  10         (PREFIX_0FC3): Renamed to ...
  11         (PREFIX_MOD_0_0FC3): This.
  12         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
  13         (prefix_table): Replace Ma with Ev on movntiS.
  14         (mod_table): Add MOD_0FC3.
  15
  16 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
  17
  18         * configure: Regenerated.
  19
  20 2015-07-23  Alan Modra  <amodra@gmail.com>
  21
  22         PR 18708
  23         * i386-dis.c (get64): Avoid signed integer overflow.
  24
  25 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
  26
  27         PR binutils/18631
  28         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
  29         "EXEvexHalfBcstXmmq" for the second operand.
  30         (EVEX_W_0F79_P_2): Likewise.
  31         (EVEX_W_0F7A_P_2): Likewise.
  32         (EVEX_W_0F7B_P_2): Likewise.
  33
  34 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
  35
  36         * arm-dis.c (print_insn_coprocessor): Added support for quarter
  37         float bitfield format.
  38         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
  39         quarter float bitfield format.
  40
  41 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
  42
  43         * configure: Regenerated.
  44
  45 2015-07-03  Alan Modra  <amodra@gmail.com>
  46
  47         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
  48         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
  49         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
  50
  51 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
  52             Cesar Philippidis  <cesar@codesourcery.com>
  53
  54         * nios2-dis.c (nios2_extract_opcode): New.
  55         (nios2_disassembler_state): New.
  56         (nios2_find_opcode_hash): Use mach parameter to select correct
  57         disassembler state.
  58         (nios2_print_insn_arg): Extend to support new R2 argument letters
  59         and formats.
  60         (print_insn_nios2): Check for 16-bit instruction at end of memory.
  61         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
  62         (NIOS2_NUM_OPCODES): Rename to...
  63         (NIOS2_NUM_R1_OPCODES): This.
  64         (nios2_r2_opcodes): New.
  65         (NIOS2_NUM_R2_OPCODES): New.
  66         (nios2_num_r2_opcodes): New.
  67         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
  68         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
  69         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
  70         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
  71         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
  72
  73 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
  74
  75         * i386-dis.c (OP_Mwaitx): New.
  76         (rm_table): Add monitorx/mwaitx.
  77         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
  78         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
  79         (operand_type_init): Add CpuMWAITX.
  80         * i386-opc.h (CpuMWAITX): New.
  81         (i386_cpu_flags): Add cpumwaitx.
  82         * i386-opc.tbl: Add monitorx and mwaitx.
  83         * i386-init.h: Regenerated.
  84         * i386-tbl.h: Likewise.
  85
  86 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
  87
  88         * ppc-opc.c (insert_ls): Test for invalid LS operands.
  89         (insert_esync): New function.
  90         (LS, WC): Use insert_ls.
  91         (ESYNC): Use insert_esync.
  92
  93 2015-06-22  Nick Clifton  <nickc@redhat.com>
  94
  95         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
  96         requested region lies beyond it.
  97         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
  98         looking for 32-bit insns.
  99         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 100         data.
 101         * sh-dis.c (print_insn_sh): Likewise.
 102         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 103         blocks of instructions.
 104         * vax-dis.c (print_insn_vax): Check that the requested address
 105         does not clash with the stop_vma.
 106
 107 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 108
 109         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 110         * ppc-opc.c (FXM4): Add non-zero optional value.
 111         (TBR): Likewise.
 112         (SXL): Likewise.
 113         (insert_fxm): Handle new default operand value.
 114         (extract_fxm): Likewise.
 115         (insert_tbr): Likewise.
 116         (extract_tbr): Likewise.
 117
 118 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 119
 120         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 121
 122 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 123
 124         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 125
 126 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 127
 128         * ppc-opc.c: Add comment accidentally removed by old commit.
 129         (MTMSRD_L): Delete.
 130
 131 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 132
 133         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 134
 135 2015-06-04  Nick Clifton  <nickc@redhat.com>
 136
 137         PR 18474
 138         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 139
 140 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 141
 142         * arm-dis.c (arm_opcodes): Add "setpan".
 143         (thumb_opcodes): Add "setpan".
 144
 145 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 146
 147         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 148         macros.
 149
 150 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 151
 152         * aarch64-tbl.h (aarch64_feature_rdma): New.
 153         (RDMA): New.
 154         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 155         * aarch64-asm-2.c: Regenerate.
 156         * aarch64-dis-2.c: Regenerate.
 157         * aarch64-opc-2.c: Regenerate.
 158
 159 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 160
 161         * aarch64-tbl.h (aarch64_feature_lor): New.
 162         (LOR): New.
 163         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 164         "stllrb", "stllrh".
 165         * aarch64-asm-2.c: Regenerate.
 166         * aarch64-dis-2.c: Regenerate.
 167         * aarch64-opc-2.c: Regenerate.
 168
 169 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 170
 171         * aarch64-opc.c (F_ARCHEXT): New.
 172         (aarch64_sys_regs): Add "pan".
 173         (aarch64_sys_reg_supported_p): New.
 174         (aarch64_pstatefields): Add "pan".
 175         (aarch64_pstatefield_supported_p): New.
 176
 177 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 178
 179         * i386-tbl.h: Regenerate.
 180
 181 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 182
 183         * i386-dis.c (print_insn): Swap rounding mode specifier and
 184         general purpose register in Intel mode.
 185
 186 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 187
 188         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 189         * i386-tbl.h: Regenerate.
 190
 191 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 194         * i386-init.h: Regenerated.
 195
 196 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 197
 198         PR binutis/18386
 199         * i386-dis.c: Add comments for '@'.
 200         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 201         (enum x86_64_isa): New.
 202         (isa64): Likewise.
 203         (print_i386_disassembler_options): Add amd64 and intel64.
 204         (print_insn): Handle amd64 and intel64.
 205         (putop): Handle '@'.
 206         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 207         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 208         * i386-opc.h (AMD64): New.
 209         (CpuIntel64): Likewise.
 210         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 211         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 212         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 213         * i386-init.h: Regenerated.
 214         * i386-tbl.h: Likewise.
 215
 216 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 217
 218         * ppc-opc.c (IH) New define.
 219         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 220         <tlbie>: Add RS operand for POWER7.
 221         <slbia>: Add IH operand for POWER6.
 222
 223 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 224
 225         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 226         direct branch.
 227         (jmp): Likewise.
 228         * i386-tbl.h: Regenerated.
 229
 230 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 231
 232         * configure.ac: Support bfd_iamcu_arch.
 233         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 234         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 235         CPU_IAMCU_COMPAT_FLAGS.
 236         (cpu_flags): Add CpuIAMCU.
 237         * i386-opc.h (CpuIAMCU): New.
 238         (i386_cpu_flags): Add cpuiamcu.
 239         * configure: Regenerated.
 240         * i386-init.h: Likewise.
 241         * i386-tbl.h: Likewise.
 242
 243 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 244
 245         PR binutis/18386
 246         * i386-dis.c (X86_64_E8): New.
 247         (X86_64_E9): Likewise.
 248         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 249         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 250         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 251         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 252         (putop): Handle '^'.
 253         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 254         REX_W.
 255
 256 2015-04-30  DJ Delorie  <dj@redhat.com>
 257
 258         * disassemble.c (disassembler): Choose suitable disassembler based
 259         on E_ABI.
 260         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 261         it to decode mul/div insns.
 262         * rl78-decode.c: Regenerate.
 263         * rl78-dis.c (print_insn_rl78): Rename to...
 264         (print_insn_rl78_common): ...this, take ISA parameter.
 265         (print_insn_rl78): New.
 266         (print_insn_rl78_g10): New.
 267         (print_insn_rl78_g13): New.
 268         (print_insn_rl78_g14): New.
 269         (rl78_get_disassembler): New.
 270
 271 2015-04-29  Nick Clifton  <nickc@redhat.com>
 272
 273         * po/fr.po: Updated French translation.
 274
 275 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 276
 277         * ppc-opc.c (DCBT_EO): New define.
 278         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 279         <lharx>: Likewise.
 280         <stbcx.>: Likewise.
 281         <sthcx.>: Likewise.
 282         <waitrsv>: Do not enable for POWER7 and later.
 283         <waitimpl>: Likewise.
 284         <dcbt>: Default to the two operand form of the instruction for all
 285         "old" cpus.  For "new" cpus, use the operand ordering that matches
 286         whether the cpu is server or embedded.
 287         <dcbtst>: Likewise.
 288
 289 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 290
 291         * s390-opc.c: New instruction type VV0UU2.
 292         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 293         and WFC.
 294
 295 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 296
 297         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 298         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 299         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 300         (vfpclasspd, vfpclassps): Add %XZ.
 301
 302 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 303
 304         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 305         (PREFIX_UD_REPZ): Likewise.
 306         (PREFIX_UD_REPNZ): Likewise.
 307         (PREFIX_UD_DATA): Likewise.
 308         (PREFIX_UD_ADDR): Likewise.
 309         (PREFIX_UD_LOCK): Likewise.
 310
 311 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 312
 313         * i386-dis.c (prefix_requirement): Removed.
 314         (print_insn): Don't set prefix_requirement.  Check
 315         dp->prefix_requirement instead of prefix_requirement.
 316
 317 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 318
 319         PR binutils/17898
 320         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 321         (PREFIX_MOD_0_0FC7_REG_6): This.
 322         (PREFIX_MOD_3_0FC7_REG_6): New.
 323         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 324         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 325         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 326         PREFIX_MOD_3_0FC7_REG_7.
 327         (mod_table): Replace PREFIX_0FC7_REG_6 with
 328         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 329         PREFIX_MOD_3_0FC7_REG_7.
 330
 331 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 332
 333         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 334         (PREFIX_MANDATORY_REPNZ): Likewise.
 335         (PREFIX_MANDATORY_DATA): Likewise.
 336         (PREFIX_MANDATORY_ADDR): Likewise.
 337         (PREFIX_MANDATORY_LOCK): Likewise.
 338         (PREFIX_MANDATORY): Likewise.
 339         (PREFIX_UD_SHIFT): Set to 8
 340         (PREFIX_UD_REPZ): Updated.
 341         (PREFIX_UD_REPNZ): Likewise.
 342         (PREFIX_UD_DATA): Likewise.
 343         (PREFIX_UD_ADDR): Likewise.
 344         (PREFIX_UD_LOCK): Likewise.
 345         (PREFIX_IGNORED_SHIFT): New.
 346         (PREFIX_IGNORED_REPZ): Likewise.
 347         (PREFIX_IGNORED_REPNZ): Likewise.
 348         (PREFIX_IGNORED_DATA): Likewise.
 349         (PREFIX_IGNORED_ADDR): Likewise.
 350         (PREFIX_IGNORED_LOCK): Likewise.
 351         (PREFIX_OPCODE): Likewise.
 352         (PREFIX_IGNORED): Likewise.
 353         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 354         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 355         (three_byte_table): Likewise.
 356         (mod_table): Likewise.
 357         (mandatory_prefix): Renamed to ...
 358         (prefix_requirement): This.
 359         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 360         Update PREFIX_90 entry.
 361         (get_valid_dis386): Check prefix_requirement to see if a prefix
 362         should be ignored.
 363         (print_insn): Replace mandatory_prefix with prefix_requirement.
 364
 365 2015-04-15  Renlin Li  <renlin.li@arm.com>
 366
 367         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 368         use it for ssat and ssat16.
 369         (print_insn_thumb32): Add handle case for 'D' control code.
 370
 371 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 372             H.J. Lu  <hongjiu.lu@intel.com>
 373
 374         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 375         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 376         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 377         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 378         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 379         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 380         Fill prefix_requirement field.
 381         (struct dis386): Add prefix_requirement field.
 382         (dis386): Fill prefix_requirement field.
 383         (dis386_twobyte): Ditto.
 384         (twobyte_has_mandatory_prefix_: Remove.
 385         (reg_table): Fill prefix_requirement field.
 386         (prefix_table): Ditto.
 387         (x86_64_table): Ditto.
 388         (three_byte_table): Ditto.
 389         (xop_table): Ditto.
 390         (vex_table): Ditto.
 391         (vex_len_table): Ditto.
 392         (vex_w_table): Ditto.
 393         (mod_table): Ditto.
 394         (bad_opcode): Ditto.
 395         (print_insn): Use prefix_requirement.
 396         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 397         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 398         (float_reg): Ditto.
 399
 400 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 401
 402         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 403
 404 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 405
 406         * Makefile.in: Regenerated.
 407
 408 2015-03-25  Anton Blanchard  <anton@samba.org>
 409
 410         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 411         powerpc_opcd_indices and vle_opcd_indices once.
 412
 413 2015-03-25  Anton Blanchard  <anton@samba.org>
 414
 415         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 416
 417 2015-03-24  Terry Guo  <terry.guo@arm.com>
 418
 419         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 420         (opcode16): Likewise.
 421         (coprocessor_opcodes): Replace bit with feature struct.
 422         (neon_opcodes): Likewise.
 423         (arm_opcodes): Likewise.
 424         (thumb_opcodes): Likewise.
 425         (thumb32_opcodes): Likewise.
 426         (print_insn_coprocessor): Likewise.
 427         (print_insn_arm): Likewise.
 428         (select_arm_features): Follow new feature struct.
 429
 430 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 431
 432         * i386-dis.c (rm_table): Add clzero.
 433         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 434         Add CPU_CLZERO_FLAGS.
 435         (cpu_flags): Add CpuCLZERO.
 436         * i386-opc.h: Add CpuCLZERO.
 437         * i386-opc.tbl: Add clzero.
 438         * i386-init.h: Re-generated.
 439         * i386-tbl.h: Re-generated.
 440
 441 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 442
 443         * mips-opc.c (decode_mips_operand): Fix constraint issues
 444         with u and y operands.
 445
 446 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 447
 448         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 449
 450 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 451
 452         * s390-opc.c: Add new IBM z13 instructions.
 453         * s390-opc.txt: Likewise.
 454
 455 2015-03-10  Renlin Li  <renlin.li@arm.com>
 456
 457         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 458         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 459         related alias.
 460         * aarch64-asm-2.c: Regenerate.
 461         * aarch64-dis-2.c: Likewise.
 462         * aarch64-opc-2.c: Likewise.
 463
 464 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 465
 466         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 467
 468 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 469
 470         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 471         arch_sh_up.
 472         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 473         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 474
 475 2015-02-23  Vinay  <Vinay.G@kpit.com>
 476
 477         * rl78-decode.opc (MOV): Added space between two operands for
 478         'mov' instruction in index addressing mode.
 479         * rl78-decode.c: Regenerate.
 480
 481 2015-02-19  Pedro Alves  <palves@redhat.com>
 482
 483         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 484
 485 2015-02-10  Pedro Alves  <palves@redhat.com>
 486             Tom Tromey  <tromey@redhat.com>
 487
 488         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 489         microblaze_and, microblaze_xor.
 490         * microblaze-opc.h (opcodes): Adjust.
 491
 492 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 493
 494         * Makefile.am: Add FT32 files.
 495         * configure.ac: Handle FT32.
 496         * disassemble.c (disassembler): Call print_insn_ft32.
 497         * ft32-dis.c: New file.
 498         * ft32-opc.c: New file.
 499         * Makefile.in: Regenerate.
 500         * configure: Regenerate.
 501         * po/POTFILES.in: Regenerate.
 502
 503 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 504
 505         * nds32-asm.c (keyword_sr): Add new system registers.
 506
 507 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 508
 509         * s390-dis.c (s390_extract_operand): Support vector register
 510         operands.
 511         (s390_print_insn_with_opcode): Support new operands types and add
 512         new handling of optional operands.
 513         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 514         and include opcode/s390.h instead.
 515         (struct op_struct): New field `flags'.
 516         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 517         (dumpTable): Dump flags.
 518         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 519         string.
 520         * s390-opc.c: Add new operands types, instruction formats, and
 521         instruction masks.
 522         (s390_opformats): Add new formats for .insn.
 523         * s390-opc.txt: Add new instructions.
 524
 525 2015-01-01  Alan Modra  <amodra@gmail.com>
 526
 527         Update year range in copyright notice of all files.
 528
 529 For older changes see ChangeLog-2014
 530 \f
 531 Copyright (C) 2015 Free Software Foundation, Inc.
 532
 533 Copying and distribution of this file, with or without modification,
 534 are permitted in any medium without royalty provided the copyright
 535 notice and this notice are preserved.
 536
 537 Local Variables:
 538 mode: change-log
 539 left-margin: 8
 540 fill-column: 74
 541 version-control: never
 542 End: