opcodes/ChangeLog

   1 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-opc.c (print_register_list): Add a prefix parameter.
   4         (aarch64_print_operand): Update accordingly.
   5
   6 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   7
   8         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
   9         for FPIMM.
  10         * aarch64-asm.h (ins_fpimm): New inserter.
  11         * aarch64-asm.c (aarch64_ins_fpimm): New function.
  12         * aarch64-asm-2.c: Regenerate.
  13         * aarch64-dis.h (ext_fpimm): New extractor.
  14         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
  15         (aarch64_ext_fpimm): New function.
  16         * aarch64-dis-2.c: Regenerate.
  17
  18 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  19
  20         * aarch64-asm.c: Include libiberty.h.
  21         (insert_fields): New function.
  22         (aarch64_ins_imm): Use it.
  23         * aarch64-dis.c (extract_fields): New function.
  24         (aarch64_ext_imm): Use it.
  25
  26 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  27
  28         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
  29         with an esize parameter.
  30         (operand_general_constraint_met_p): Update accordingly.
  31         Fix misindented code.
  32         * aarch64-asm.c (aarch64_ins_limm): Update call to
  33         aarch64_logical_immediate_p.
  34
  35 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  36
  37         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
  38
  39 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  40
  41         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
  42
  43 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
  44
  45         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
  46
  47 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
  48
  49         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
  50         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
  51         xor3>: Delete mnemonics.
  52         <cp_abort>: Rename mnemonic from ...
  53         <cpabort>: ...to this.
  54         <setb>: Change to a X form instruction.
  55         <sync>: Change to 1 operand form.
  56         <copy>: Delete mnemonic.
  57         <copy_first>: Rename mnemonic from ...
  58         <copy>: ...to this.
  59         <paste, paste.>: Delete mnemonics.
  60         <paste_last>: Rename mnemonic from ...
  61         <paste.>: ...to this.
  62
  63 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  64
  65         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
  66
  67 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
  68
  69         * s390-mkopc.c (main): Support alternate arch strings.
  70
  71 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
  72
  73         * s390-opc.txt: Fix kmctr instruction type.
  74
  75 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
  76
  77         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
  78         * i386-init.h: Regenerated.
  79
  80 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
  81
  82         * opcodes/arc-dis.c (print_insn_arc): Changed.
  83
  84 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
  85
  86         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
  87         camellia_fl.
  88
  89 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  90
  91         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
  92         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
  93         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
  94
  95 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
  96
  97         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
  98         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
  99         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 100         PREFIX_MOD_3_0FAE_REG_4.
 101         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 102         PREFIX_MOD_3_0FAE_REG_4.
 103         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 104         (cpu_flags): Add CpuPTWRITE.
 105         * i386-opc.h (CpuPTWRITE): New.
 106         (i386_cpu_flags): Add cpuptwrite.
 107         * i386-opc.tbl: Add ptwrite instruction.
 108         * i386-init.h: Regenerated.
 109         * i386-tbl.h: Likewise.
 110
 111 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 112
 113         * arc-dis.h: Wrap around in extern "C".
 114
 115 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 116
 117         * aarch64-tbl.h (V8_2_INSN): New macro.
 118         (aarch64_opcode_table): Use it.
 119
 120 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 121
 122         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 123         CORE_INSN, __FP_INSN and SIMD_INSN.
 124
 125 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 126
 127         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 128         (aarch64_opcode_table): Update uses accordingly.
 129
 130 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 131         Kwok Cheung Yeung  <kcy@codesourcery.com>
 132
 133         opcodes/
 134         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 135         'e_cmplwi' to 'e_cmpli' instead.
 136         (OPVUPRT, OPVUPRT_MASK): Define.
 137         (powerpc_opcodes): Add E200Z4 insns.
 138         (vle_opcodes): Add context save/restore insns.
 139
 140 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 141
 142         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 143         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 144         "j".
 145
 146 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 147
 148         * arc-nps400-tbl.h: Change block comments to GNU format.
 149         * arc-dis.c: Add new globals addrtypenames,
 150         addrtypenames_max, and addtypeunknown.
 151         (get_addrtype): New function.
 152         (print_insn_arc): Print colons and address types when
 153         required.
 154         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 155         define insert and extract functions for all address types.
 156         (arc_operands): Add operands for colon and all address
 157         types.
 158         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 159         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 160         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 161         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 162         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 163         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 164
 165 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 166
 167         * configure: Regenerated.
 168
 169 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 170
 171         * arc-dis.c (skipclass): New structure.
 172         (decodelist): New variable.
 173         (is_compatible_p): New function.
 174         (new_element): Likewise.
 175         (skip_class_p): Likewise.
 176         (find_format_from_table): Use skip_class_p function.
 177         (find_format): Decode first the extension instructions.
 178         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 179         e_flags.
 180         (parse_option): New function.
 181         (parse_disassembler_options): Likewise.
 182         (print_arc_disassembler_options): Likewise.
 183         (print_insn_arc): Use parse_disassembler_options function.  Proper
 184         select ARCv2 cpu variant.
 185         * disassemble.c (disassembler_usage): Add ARC disassembler
 186         options.
 187
 188 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 189
 190         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 191         annotation from the "nal" entry and reorder it beyond "bltzal".
 192
 193 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 194
 195         * sparc-opc.c (ldtxa): New macro.
 196         (sparc_opcodes): Use the macro defined above to add entries for
 197         the LDTXA instructions.
 198         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 199         instruction.
 200
 201 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 202
 203         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 204         and "jmpc".
 205
 206 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 207
 208         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 209         (movzb): Adjust to cover all permitted suffixes.
 210         (movzw): New.
 211         * i386-tbl.h: Re-generate.
 212
 213 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 214
 215         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 216         (lgdt): Remove Tbyte from non-64-bit variant.
 217         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 218         xsaves64, xsavec64): Remove Disp16.
 219         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 220         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 221         64-bit variants.
 222         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 223         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 224         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 225         64-bit variants.
 226         * i386-tbl.h: Re-generate.
 227
 228 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 229
 230         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 231         * i386-tbl.h: Re-generate.
 232
 233 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 234
 235         * arm-dis.c (print_insn): Fix typo in comment.
 236
 237 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 238
 239         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 240         range of ldst_elemlist operands.
 241         (print_register_list): Use PRIi64 to print the index.
 242         (aarch64_print_operand): Likewise.
 243
 244 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 245
 246         * mcore-opc.h: Remove sentinal.
 247         * mcore-dis.c (print_insn_mcore): Adjust.
 248
 249 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 250
 251         * arc-opc.c: Correct description of availability of NPS400
 252         features.
 253
 254 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 255
 256         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 257         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 258         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 259         xor3>: New mnemonics.
 260         <setb>: Change to a VX form instruction.
 261         (insert_sh6): Add support for rldixor.
 262         (extract_sh6): Likewise.
 263
 264 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 265
 266         * arc-ext.h: Wrap in extern C.
 267
 268 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 269
 270         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 271         Use same method for determining instruction length on ARC700 and
 272         NPS-400.
 273         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 274         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 275         with the NPS400 subclass.
 276         * arc-opc.c: Likewise.
 277
 278 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 279
 280         * sparc-opc.c (rdasr): New macro.
 281         (wrasr): Likewise.
 282         (rdpr): Likewise.
 283         (wrpr): Likewise.
 284         (rdhpr): Likewise.
 285         (wrhpr): Likewise.
 286         (sparc_opcodes): Use the macros above to fix and expand the
 287         definition of read/write instructions from/to
 288         asr/privileged/hyperprivileged instructions.
 289         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 290         %hva_mask_nz.  Prefer softint_set and softint_clear over
 291         set_softint and clear_softint.
 292         (print_insn_sparc): Support %ver in Rd.
 293
 294 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 295
 296         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 297         architecture according to the hardware capabilities they require.
 298
 299 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 300
 301         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 302         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 303         bfd_mach_sparc_v9{c,d,e,v,m}.
 304         * sparc-opc.c (MASK_V9C): Define.
 305         (MASK_V9D): Likewise.
 306         (MASK_V9E): Likewise.
 307         (MASK_V9V): Likewise.
 308         (MASK_V9M): Likewise.
 309         (v6): Add MASK_V9{C,D,E,V,M}.
 310         (v6notlet): Likewise.
 311         (v7): Likewise.
 312         (v8): Likewise.
 313         (v9): Likewise.
 314         (v9andleon): Likewise.
 315         (v9a): Likewise.
 316         (v9b): Likewise.
 317         (v9c): Define.
 318         (v9d): Likewise.
 319         (v9e): Likewise.
 320         (v9v): Likewise.
 321         (v9m): Likewise.
 322         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 323
 324 2016-06-15  Nick Clifton  <nickc@redhat.com>
 325
 326         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 327         constants to match expected behaviour.
 328         (nds32_parse_opcode): Likewise.  Also for whitespace.
 329
 330 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 331
 332         * arc-opc.c (extract_rhv1): Extract value from insn.
 333
 334 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 335
 336         * arc-nps400-tbl.h: Add ldbit instruction.
 337         * arc-opc.c: Add flag classes required for ldbit.
 338
 339 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 340
 341         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 342         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 343         support the above instructions.
 344
 345 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 346
 347         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 348         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 349         csma, cbba, zncv, and hofs.
 350         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 351         support the above instructions.
 352
 353 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 354
 355         * arc-nps400-tbl.h: Add andab and orab instructions.
 356
 357 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 358
 359         * arc-nps400-tbl.h: Add addl-like instructions.
 360
 361 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 362
 363         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 364
 365 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 366
 367         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 368         instructions.
 369
 370 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 371
 372         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 373         variable.
 374         (init_disasm): Handle new command line option "insnlength".
 375         (print_s390_disassembler_options): Mention new option in help
 376         output.
 377         (print_insn_s390): Use the encoded insn length when dumping
 378         unknown instructions.
 379
 380 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 381
 382         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 383          to the address and set as symbol address for LDS/ STS immediate operands.
 384
 385 2016-06-07  Alan Modra  <amodra@gmail.com>
 386
 387         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 388         cpu for "vle" to e500.
 389         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 390         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 391         (PPCNONE): Delete, substitute throughout.
 392         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 393         except for major opcode 4 and 31.
 394         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 395
 396 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 397
 398         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 399         ARM_EXT_RAS in relevant entries.
 400
 401 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 402
 403         PR binutils/20196
 404         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 405         opcodes for E6500.
 406
 407 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 408
 409         PR binutis/18386
 410         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 411         (indir_v_mode): New.
 412         Add comments for '&'.
 413         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 414         (putop): Handle '&'.
 415         (intel_operand_size): Handle indir_v_mode.
 416         (OP_E_register): Likewise.
 417         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 418         64-bit indirect call/jmp for AMD64.
 419         * i386-tbl.h: Regenerated
 420
 421 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 422
 423         * arc-dis.c (struct arc_operand_iterator): New structure.
 424         (find_format_from_table): All the old content from find_format,
 425         with some minor adjustments, and parameter renaming.
 426         (find_format_long_instructions): New function.
 427         (find_format): Rewritten.
 428         (arc_insn_length): Add LSB parameter.
 429         (extract_operand_value): New function.
 430         (operand_iterator_next): New function.
 431         (print_insn_arc): Use new functions to find opcode, and iterator
 432         over operands.
 433         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 434         (extract_nps_3bit_dst_short): New function.
 435         (insert_nps_3bit_src2_short): New function.
 436         (extract_nps_3bit_src2_short): New function.
 437         (insert_nps_bitop1_size): New function.
 438         (extract_nps_bitop1_size): New function.
 439         (insert_nps_bitop2_size): New function.
 440         (extract_nps_bitop2_size): New function.
 441         (insert_nps_bitop_mod4_msb): New function.
 442         (extract_nps_bitop_mod4_msb): New function.
 443         (insert_nps_bitop_mod4_lsb): New function.
 444         (extract_nps_bitop_mod4_lsb): New function.
 445         (insert_nps_bitop_dst_pos3_pos4): New function.
 446         (extract_nps_bitop_dst_pos3_pos4): New function.
 447         (insert_nps_bitop_ins_ext): New function.
 448         (extract_nps_bitop_ins_ext): New function.
 449         (arc_operands): Add new operands.
 450         (arc_long_opcodes): New global array.
 451         (arc_num_long_opcodes): New global.
 452         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 453
 454 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 455
 456         * nds32-asm.h: Add extern "C".
 457         * sh-opc.h: Likewise.
 458
 459 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 460
 461         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 462         0,b,limm to the rflt instruction.
 463
 464 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 465
 466         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 467         constant.
 468
 469 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 470
 471         PR gas/20145
 472         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 473         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 474         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 475         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 476         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 477         * i386-init.h: Regenerated.
 478
 479 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 480
 481         PR gas/20145
 482         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 483         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 484         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 485         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 486         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 487         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 488         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 489         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 490         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 491         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 492         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 493         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 494         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 495         CpuRegMask for AVX512.
 496         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 497         and CpuRegMask.
 498         (set_bitfield_from_cpu_flag_init): New function.
 499         (set_bitfield): Remove const on f.  Call
 500         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 501         * i386-opc.h (CpuRegMMX): New.
 502         (CpuRegXMM): Likewise.
 503         (CpuRegYMM): Likewise.
 504         (CpuRegZMM): Likewise.
 505         (CpuRegMask): Likewise.
 506         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 507         and cpuregmask.
 508         * i386-init.h: Regenerated.
 509         * i386-tbl.h: Likewise.
 510
 511 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 512
 513         PR gas/20154
 514         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 515         (opcode_modifiers): Add AMD64 and Intel64.
 516         (main): Properly verify CpuMax.
 517         * i386-opc.h (CpuAMD64): Removed.
 518         (CpuIntel64): Likewise.
 519         (CpuMax): Set to CpuNo64.
 520         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 521         (AMD64): New.
 522         (Intel64): Likewise.
 523         (i386_opcode_modifier): Add amd64 and intel64.
 524         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 525         on call and jmp.
 526         * i386-init.h: Regenerated.
 527         * i386-tbl.h: Likewise.
 528
 529 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 530
 531         PR gas/20154
 532         * i386-gen.c (main): Fail if CpuMax is incorrect.
 533         * i386-opc.h (CpuMax): Set to CpuIntel64.
 534         * i386-tbl.h: Regenerated.
 535
 536 2016-05-27  Nick Clifton  <nickc@redhat.com>
 537
 538         PR target/20150
 539         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 540         (msp430dis_opcode_unsigned): New function.
 541         (msp430dis_opcode_signed): New function.
 542         (msp430_singleoperand): Use the new opcode reading functions.
 543         Only disassenmble bytes if they were successfully read.
 544         (msp430_doubleoperand): Likewise.
 545         (msp430_branchinstr): Likewise.
 546         (msp430x_callx_instr): Likewise.
 547         (print_insn_msp430): Check that it is safe to read bytes before
 548         attempting disassembly.  Use the new opcode reading functions.
 549
 550 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 551
 552         * ppc-opc.c (CY): New define.  Document it.
 553         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 554
 555 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 556
 557         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 558         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 559         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 560         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 561         CPU_ANY_AVX_FLAGS.
 562         * i386-init.h: Regenerated.
 563
 564 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 565
 566         PR gas/20141
 567         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 568         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 569         * i386-init.h: Regenerated.
 570
 571 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 572
 573         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 574         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 575         * i386-init.h: Regenerated.
 576
 577 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 578
 579         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 580         information.
 581         (print_insn_arc): Set insn_type information.
 582         * arc-opc.c (C_CC): Add F_CLASS_COND.
 583         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 584         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 585         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 586         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 587         (brne, brne_s, jeq_s, jne_s): Likewise.
 588
 589 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 590
 591         * arc-tbl.h (neg): New instruction variant.
 592
 593 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 594
 595         * arc-dis.c (find_format, find_format, get_auxreg)
 596         (print_insn_arc): Changed.
 597         * arc-ext.h (INSERT_XOP): Likewise.
 598
 599 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 600
 601         * tic54x-dis.c (sprint_mmr): Adjust.
 602         * tic54x-opc.c: Likewise.
 603
 604 2016-05-19  Alan Modra  <amodra@gmail.com>
 605
 606         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 607
 608 2016-05-19  Alan Modra  <amodra@gmail.com>
 609
 610         * ppc-opc.c: Formatting.
 611         (NSISIGNOPT): Define.
 612         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 613
 614 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 615
 616         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 617         replacing references to `micromips_ase' throughout.
 618         (_print_insn_mips): Don't use file-level microMIPS annotation to
 619         determine the disassembly mode with the symbol table.
 620
 621 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 622
 623         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 624
 625 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 626
 627         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 628         mips64r6.
 629         * mips-opc.c (D34): New macro.
 630         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 631
 632 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 633
 634         * i386-dis.c (prefix_table): Add RDPID instruction.
 635         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 636         (cpu_flags): Add RDPID bitfield.
 637         * i386-opc.h (enum): Add RDPID element.
 638         (i386_cpu_flags): Add RDPID field.
 639         * i386-opc.tbl: Add RDPID instruction.
 640         * i386-init.h: Regenerate.
 641         * i386-tbl.h: Regenerate.
 642
 643 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 644
 645         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 646         branch type of a symbol.
 647         (print_insn): Likewise.
 648
 649 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 650
 651         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 652         Mainline Security Extensions instructions.
 653         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 654         Extensions instructions.
 655         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 656         instructions.
 657         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 658         special registers.
 659
 660 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 661
 662         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 663
 664 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 665
 666         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 667         (arcExtMap_genOpcode): Likewise.
 668         * arc-opc.c (arg_32bit_rc): Define new variable.
 669         (arg_32bit_u6): Likewise.
 670         (arg_32bit_limm): Likewise.
 671
 672 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 673
 674         * aarch64-gen.c (VERIFIER): Define.
 675         * aarch64-opc.c (VERIFIER): Define.
 676         (verify_ldpsw): Use static linkage.
 677         * aarch64-opc.h (verify_ldpsw): Remove.
 678         * aarch64-tbl.h: Use VERIFIER for verifiers.
 679
 680 2016-04-28  Nick Clifton  <nickc@redhat.com>
 681
 682         PR target/19722
 683         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 684         * aarch64-opc.c (verify_ldpsw): New function.
 685         * aarch64-opc.h (verify_ldpsw): New prototype.
 686         * aarch64-tbl.h: Add initialiser for verifier field.
 687         (LDPSW): Set verifier to verify_ldpsw.
 688
 689 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 690
 691         PR binutils/19983
 692         PR binutils/19984
 693         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 694         smaller than address size.
 695
 696 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 697
 698         * alpha-dis.c: Regenerate.
 699         * crx-dis.c: Likewise.
 700         * disassemble.c: Likewise.
 701         * epiphany-opc.c: Likewise.
 702         * fr30-opc.c: Likewise.
 703         * frv-opc.c: Likewise.
 704         * ip2k-opc.c: Likewise.
 705         * iq2000-opc.c: Likewise.
 706         * lm32-opc.c: Likewise.
 707         * lm32-opinst.c: Likewise.
 708         * m32c-opc.c: Likewise.
 709         * m32r-opc.c: Likewise.
 710         * m32r-opinst.c: Likewise.
 711         * mep-opc.c: Likewise.
 712         * mt-opc.c: Likewise.
 713         * or1k-opc.c: Likewise.
 714         * or1k-opinst.c: Likewise.
 715         * tic80-opc.c: Likewise.
 716         * xc16x-opc.c: Likewise.
 717         * xstormy16-opc.c: Likewise.
 718
 719 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 720
 721         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 722         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 723         calcsd, and calcxd instructions.
 724         * arc-opc.c (insert_nps_bitop_size): Delete.
 725         (extract_nps_bitop_size): Delete.
 726         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 727         (extract_nps_qcmp_m3): Define.
 728         (extract_nps_qcmp_m2): Define.
 729         (extract_nps_qcmp_m1): Define.
 730         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 731         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 732         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 733         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 734         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 735         NPS_QCMP_M3.
 736
 737 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 738
 739         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 740
 741 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 742
 743         * Makefile.in: Regenerated with automake 1.11.6.
 744         * aclocal.m4: Likewise.
 745
 746 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 747
 748         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 749         instructions.
 750         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 751         (extract_nps_cmem_uimm16): New function.
 752         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 753
 754 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 755
 756         * arc-dis.c (arc_insn_length): New function.
 757         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 758         (find_format): Change insnLen parameter to unsigned.
 759
 760 2016-04-13  Nick Clifton  <nickc@redhat.com>
 761
 762         PR target/19937
 763         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 764         the LD.B and LD.BU instructions.
 765
 766 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 767
 768         * arc-dis.c (find_format): Check for extension flags.
 769         (print_flags): New function.
 770         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 771         .extAuxRegister.
 772         * arc-ext.c (arcExtMap_coreRegName): Use
 773         LAST_EXTENSION_CORE_REGISTER.
 774         (arcExtMap_coreReadWrite): Likewise.
 775         (dump_ARC_extmap): Update printing.
 776         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 777         (arc_aux_regs): Add cpu field.
 778         * arc-regs.h: Add cpu field, lower case name aux registers.
 779
 780 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 781
 782         * arc-tbl.h: Add rtsc, sleep with no arguments.
 783
 784 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 785
 786         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 787         Initialize.
 788         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 789         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 790         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 791         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 792         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 793         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 794         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 795         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 796         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 797         (arc_opcode arc_opcodes): Null terminate the array.
 798         (arc_num_opcodes): Remove.
 799         * arc-ext.h (INSERT_XOP): Define.
 800         (extInstruction_t): Likewise.
 801         (arcExtMap_instName): Delete.
 802         (arcExtMap_insn): New function.
 803         (arcExtMap_genOpcode): Likewise.
 804         * arc-ext.c (ExtInstruction): Remove.
 805         (create_map): Zero initialize instruction fields.
 806         (arcExtMap_instName): Remove.
 807         (arcExtMap_insn): New function.
 808         (dump_ARC_extmap): More info while debuging.
 809         (arcExtMap_genOpcode): New function.
 810         * arc-dis.c (find_format): New function.
 811         (print_insn_arc): Use find_format.
 812         (arc_get_disassembler): Enable dump_ARC_extmap only when
 813         debugging.
 814
 815 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 816
 817         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 818         instruction bits out.
 819
 820 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 821
 822         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 823         * arc-opc.c (arc_flag_operands): Add new flags.
 824         (arc_flag_classes): Add new classes.
 825
 826 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 827
 828         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 829
 830 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 831
 832         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 833         encode1, rflt, crc16, and crc32 instructions.
 834         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 835         (arc_flag_classes): Add C_NPS_R.
 836         (insert_nps_bitop_size_2b): New function.
 837         (extract_nps_bitop_size_2b): Likewise.
 838         (insert_nps_bitop_uimm8): Likewise.
 839         (extract_nps_bitop_uimm8): Likewise.
 840         (arc_operands): Add new operand entries.
 841
 842 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 843
 844         * arc-regs.h: Add a new subclass field.  Add double assist
 845         accumulator register values.
 846         * arc-tbl.h: Use DPA subclass to mark the double assist
 847         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 848         * arc-opc.c (RSP): Define instead of SP.
 849         (arc_aux_regs): Add the subclass field.
 850
 851 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 852
 853         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 854
 855 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 856
 857         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 858         NPS_R_SRC1.
 859
 860 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 861
 862         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 863         issues.  No functional changes.
 864
 865 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 866
 867         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 868         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 869         (RTT): Remove duplicate.
 870         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 871         (PCT_CONFIG*): Remove.
 872         (D1L, D1H, D2H, D2L): Define.
 873
 874 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 875
 876         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 877
 878 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 879
 880         * arc-tbl.h (invld07): Remove.
 881         * arc-ext-tbl.h: New file.
 882         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 883         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 884
 885 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 886
 887         Fix -Wstack-usage warnings.
 888         * aarch64-dis.c (print_operands): Substitute size.
 889         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 890
 891 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 892
 893         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 894         to get a proper diagnostic when an invalid ASR register is used.
 895
 896 2016-03-22  Nick Clifton  <nickc@redhat.com>
 897
 898         * configure: Regenerate.
 899
 900 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 901
 902         * arc-nps400-tbl.h: New file.
 903         * arc-opc.c: Add top level comment.
 904         (insert_nps_3bit_dst): New function.
 905         (extract_nps_3bit_dst): New function.
 906         (insert_nps_3bit_src2): New function.
 907         (extract_nps_3bit_src2): New function.
 908         (insert_nps_bitop_size): New function.
 909         (extract_nps_bitop_size): New function.
 910         (arc_flag_operands): Add nps400 entries.
 911         (arc_flag_classes): Add nps400 entries.
 912         (arc_operands): Add nps400 entries.
 913         (arc_opcodes): Add nps400 include.
 914
 915 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 916
 917         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 918         the new class enum values.
 919
 920 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 921
 922         * arc-dis.c (print_insn_arc): Handle nps400.
 923
 924 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 925
 926         * arc-opc.c (BASE): Delete.
 927
 928 2016-03-18  Nick Clifton  <nickc@redhat.com>
 929
 930         PR target/19721
 931         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 932         of MOV insn that aliases an ORR insn.
 933
 934 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 935
 936         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 937
 938 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 939
 940         * mcore-opc.h: Add const qualifiers.
 941         * microblaze-opc.h (struct op_code_struct): Likewise.
 942         * sh-opc.h: Likewise.
 943         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 944         (tic4x_print_op): Likewise.
 945
 946 2016-03-02  Alan Modra  <amodra@gmail.com>
 947
 948         * or1k-desc.h: Regenerate.
 949         * fr30-ibld.c: Regenerate.
 950         * rl78-decode.c: Regenerate.
 951
 952 2016-03-01  Nick Clifton  <nickc@redhat.com>
 953
 954         PR target/19747
 955         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 956
 957 2016-02-24  Renlin Li  <renlin.li@arm.com>
 958
 959         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 960         (print_insn_coprocessor): Support fp16 instructions.
 961
 962 2016-02-24  Renlin Li  <renlin.li@arm.com>
 963
 964         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 965         vminnm, vrint(mpna).
 966
 967 2016-02-24  Renlin Li  <renlin.li@arm.com>
 968
 969         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 970         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 971
 972 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 973
 974         * i386-dis.c (print_insn): Parenthesize expression to prevent
 975         truncated addresses.
 976         (OP_J): Likewise.
 977
 978 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 979             Janek van Oirschot  <jvanoirs@synopsys.com>
 980
 981         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 982         variable.
 983
 984 2016-02-04  Nick Clifton  <nickc@redhat.com>
 985
 986         PR target/19561
 987         * msp430-dis.c (print_insn_msp430): Add a special case for
 988         decoding an RRC instruction with the ZC bit set in the extension
 989         word.
 990
 991 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 992
 993         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 994         * epiphany-ibld.c: Regenerate.
 995         * fr30-ibld.c: Regenerate.
 996         * frv-ibld.c: Regenerate.
 997         * ip2k-ibld.c: Regenerate.
 998         * iq2000-ibld.c: Regenerate.
 999         * lm32-ibld.c: Regenerate.
1000         * m32c-ibld.c: Regenerate.
1001         * m32r-ibld.c: Regenerate.
1002         * mep-ibld.c: Regenerate.
1003         * mt-ibld.c: Regenerate.
1004         * or1k-ibld.c: Regenerate.
1005         * xc16x-ibld.c: Regenerate.
1006         * xstormy16-ibld.c: Regenerate.
1007
1008 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1009
1010         * epiphany-dis.c: Regenerated from latest cpu files.
1011
1012 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1013
1014         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1015         test bit.
1016
1017 2016-01-25  Renlin Li  <renlin.li@arm.com>
1018
1019         * arm-dis.c (mapping_symbol_for_insn): New function.
1020         (find_ifthen_state): Call mapping_symbol_for_insn().
1021
1022 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1023
1024         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1025         of MSR UAO immediate operand.
1026
1027 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1028
1029         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1030         instruction support.
1031
1032 2016-01-17  Alan Modra  <amodra@gmail.com>
1033
1034         * configure: Regenerate.
1035
1036 2016-01-14  Nick Clifton  <nickc@redhat.com>
1037
1038         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1039         instructions that can support stack pointer operations.
1040         * rl78-decode.c: Regenerate.
1041         * rl78-dis.c: Fix display of stack pointer in MOVW based
1042         instructions.
1043
1044 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1045
1046         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1047         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1048         erxtatus_el1 and erxaddr_el1.
1049
1050 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1051
1052         * arm-dis.c (arm_opcodes): Add "esb".
1053         (thumb_opcodes): Likewise.
1054
1055 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1056
1057         * ppc-opc.c <xscmpnedp>: Delete.
1058         <xvcmpnedp>: Likewise.
1059         <xvcmpnedp.>: Likewise.
1060         <xvcmpnesp>: Likewise.
1061         <xvcmpnesp.>: Likewise.
1062
1063 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1064
1065         PR gas/13050
1066         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1067         addition to ISA_A.
1068
1069 2016-01-01  Alan Modra  <amodra@gmail.com>
1070
1071         Update year range in copyright notice of all files.
1072
1073 For older changes see ChangeLog-2015
1074 \f
1075 Copyright (C) 2016 Free Software Foundation, Inc.
1076
1077 Copying and distribution of this file, with or without modification,
1078 are permitted in any medium without royalty provided the copyright
1079 notice and this notice are preserved.
1080
1081 Local Variables:
1082 mode: change-log
1083 left-margin: 8
1084 fill-column: 74
1085 version-control: never
1086 End: