1 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
2 Amit Pawar <amit.pawar@amd.com>
5 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
8 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
10 * configure: Regenerate.
12 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
14 * sparc-opc.c (HWS_V8): Definition moved from
15 gas/config/tc-sparc.c.
25 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
28 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
30 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
33 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
35 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
36 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
37 (aarch64_opcode_table): Add fcmla and fcadd.
38 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
39 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
40 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
41 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
42 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
43 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
44 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
45 (operand_general_constraint_met_p): Rotate and index range check.
46 (aarch64_print_operand): Handle rotate operand.
47 * aarch64-asm-2.c: Regenerate.
48 * aarch64-dis-2.c: Likewise.
49 * aarch64-opc-2.c: Likewise.
51 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
53 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
54 * aarch64-asm-2.c: Regenerate.
55 * aarch64-dis-2.c: Regenerate.
56 * aarch64-opc-2.c: Regenerate.
58 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
60 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
61 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
62 * aarch64-asm-2.c: Regenerate.
63 * aarch64-dis-2.c: Regenerate.
64 * aarch64-opc-2.c: Regenerate.
66 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
68 * aarch64-tbl.h (QL_X1NIL): New.
69 (arch64_opcode_table): Add ldraa, ldrab.
70 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
71 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
72 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
73 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
74 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
75 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
76 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
77 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
78 (aarch64_print_operand): Likewise.
79 * aarch64-asm-2.c: Regenerate.
80 * aarch64-dis-2.c: Regenerate.
81 * aarch64-opc-2.c: Regenerate.
83 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
85 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
86 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
87 * aarch64-asm-2.c: Regenerate.
88 * aarch64-dis-2.c: Regenerate.
89 * aarch64-opc-2.c: Regenerate.
91 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
93 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
94 (AARCH64_OPERANDS): Add Rm_SP.
95 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
96 * aarch64-asm-2.c: Regenerate.
97 * aarch64-dis-2.c: Regenerate.
98 * aarch64-opc-2.c: Regenerate.
100 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
102 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
103 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
104 autdzb, xpaci, xpacd.
105 * aarch64-asm-2.c: Regenerate.
106 * aarch64-dis-2.c: Regenerate.
107 * aarch64-opc-2.c: Regenerate.
109 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
111 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
112 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
113 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
114 (aarch64_sys_reg_supported_p): Add feature test for new registers.
116 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
118 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
119 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
120 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
122 * aarch64-asm-2.c: Regenerate.
123 * aarch64-dis-2.c: Regenerate.
125 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
127 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
129 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
132 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
133 * i386-dis.c (EdqwS): Removed.
134 (dqw_swap_mode): Likewise.
135 (intel_operand_size): Don't check dqw_swap_mode.
136 (OP_E_register): Likewise.
137 (OP_E_memory): Likewise.
140 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
141 * i386-tbl.h: Regerated.
143 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
145 * i386-opc.tbl: Merge AVX512F vmovq.
146 * i386-tbl.h: Regerated.
148 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
151 * i386-dis.c (THREE_BYTE_0F7A): Removed.
152 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
153 (three_byte_table): Remove THREE_BYTE_0F7A.
155 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
158 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
159 (FGRPd9_4): Replace 1 with 2.
160 (FGRPd9_5): Replace 2 with 3.
161 (FGRPd9_6): Replace 3 with 4.
162 (FGRPd9_7): Replace 4 with 5.
163 (FGRPda_5): Replace 5 with 6.
164 (FGRPdb_4): Replace 6 with 7.
165 (FGRPde_3): Replace 7 with 8.
166 (FGRPdf_4): Replace 8 with 9.
167 (fgrps): Add an entry for Bad_Opcode.
169 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
171 * arc-opc.c (arc_flag_operands): Add F_DI14.
172 (arc_flag_classes): Add C_DI14.
173 * arc-nps400-tbl.h: Add new exc instructions.
175 2016-11-03 Graham Markall <graham.markall@embecosm.com>
177 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
179 * arc-nps-400-tbl.h: Add dcmac instruction.
180 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
181 (insert_nps_rbdouble_64): Added.
182 (extract_nps_rbdouble_64): Added.
183 (insert_nps_proto_size): Added.
184 (extract_nps_proto_size): Added.
186 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
188 * arc-dis.c (struct arc_operand_iterator): Remove all fields
189 relating to long instruction processing, add new limm field.
190 (OPCODE): Rename to...
191 (OPCODE_32BIT_INSN): ...this.
193 (skip_this_opcode): Handle different instruction lengths, update
195 (special_flag_p): Update parameter type.
196 (find_format_from_table): Update for more instruction lengths.
197 (find_format_long_instructions): Delete.
198 (find_format): Update for more instruction lengths.
199 (arc_insn_length): Likewise.
200 (extract_operand_value): Update for more instruction lengths.
201 (operand_iterator_next): Remove code relating to long
203 (arc_opcode_to_insn_type): New function.
204 (print_insn_arc):Update for more instructions lengths.
205 * arc-ext.c (extInstruction_t): Change argument type.
206 * arc-ext.h (extInstruction_t): Change argument type.
207 * arc-fxi.h: Change type unsigned to unsigned long long
208 extensively throughout.
209 * arc-nps400-tbl.h: Add long instructions taken from
210 arc_long_opcodes table in arc-opc.c.
211 * arc-opc.c: Update parameter types on insert/extract handlers.
212 (arc_long_opcodes): Delete.
213 (arc_num_long_opcodes): Delete.
214 (arc_opcode_len): Update for more instruction lengths.
216 2016-11-03 Graham Markall <graham.markall@embecosm.com>
218 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
220 2016-11-03 Graham Markall <graham.markall@embecosm.com>
222 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
224 (find_format_long_instructions): Likewise.
225 * arc-opc.c (arc_opcode_len): New function.
227 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
229 * arc-nps400-tbl.h: Fix some instruction masks.
231 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
233 * i386-dis.c (REG_82): Removed.
234 (X86_64_82_REG_0): Likewise.
235 (X86_64_82_REG_1): Likewise.
236 (X86_64_82_REG_2): Likewise.
237 (X86_64_82_REG_3): Likewise.
238 (X86_64_82_REG_4): Likewise.
239 (X86_64_82_REG_5): Likewise.
240 (X86_64_82_REG_6): Likewise.
241 (X86_64_82_REG_7): Likewise.
243 (dis386): Use X86_64_82 instead of REG_82.
244 (reg_table): Remove REG_82.
245 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
246 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
247 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
250 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
253 * i386-dis.c (REG_82): New.
254 (X86_64_82_REG_0): Likewise.
255 (X86_64_82_REG_1): Likewise.
256 (X86_64_82_REG_2): Likewise.
257 (X86_64_82_REG_3): Likewise.
258 (X86_64_82_REG_4): Likewise.
259 (X86_64_82_REG_5): Likewise.
260 (X86_64_82_REG_6): Likewise.
261 (X86_64_82_REG_7): Likewise.
262 (dis386): Use REG_82.
263 (reg_table): Add REG_82.
264 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
265 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
266 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
268 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
270 * i386-dis.c (REG_82): Renamed to ...
273 (reg_table): Likewise.
275 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
277 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
278 * i386-dis-evex.h (evex_table): Updated.
279 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
280 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
281 (cpu_flags): Add CpuAVX512_4VNNIW.
282 * i386-opc.h (enum): (AVX512_4VNNIW): New.
283 (i386_cpu_flags): Add cpuavx512_4vnniw.
284 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
285 * i386-init.h: Regenerate.
288 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
290 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
291 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
292 * i386-dis-evex.h (evex_table): Updated.
293 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
294 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
295 (cpu_flags): Add CpuAVX512_4FMAPS.
296 (opcode_modifiers): Add ImplicitQuadGroup modifier.
297 * i386-opc.h (AVX512_4FMAP): New.
298 (i386_cpu_flags): Add cpuavx512_4fmaps.
299 (ImplicitQuadGroup): New.
300 (i386_opcode_modifier): Add implicitquadgroup.
301 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
302 * i386-init.h: Regenerate.
305 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
306 Andrew Waterman <andrew@sifive.com>
308 Add support for RISC-V architecture.
309 * configure.ac: Add entry for bfd_riscv_arch.
310 * configure: Regenerate.
311 * disassemble.c (disassembler): Add support for riscv.
312 (disassembler_usage): Likewise.
313 * riscv-dis.c: New file.
314 * riscv-opc.c: New file.
316 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
318 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
319 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
320 (rm_table): Update the RM_0FAE_REG_7 entry.
321 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
322 (cpu_flags): Remove CpuPCOMMIT.
323 * i386-opc.h (CpuPCOMMIT): Removed.
324 (i386_cpu_flags): Remove cpupcommit.
325 * i386-opc.tbl: Remove pcommit.
326 * i386-init.h: Regenerated.
327 * i386-tbl.h: Likewise.
329 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
332 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
333 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
334 32-bit mode. Don't check vex.register_specifier in 32-bit
336 (OP_VEX): Check for invalid mask registers.
338 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
341 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
344 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
347 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
349 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
351 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
352 local variable to `index_regno'.
354 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
356 * arc-tbl.h: Removed any "inv.+" instructions from the table.
358 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
360 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
363 2016-10-11 Jiong Wang <jiong.wang@arm.com>
366 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
368 2016-10-07 Jiong Wang <jiong.wang@arm.com>
371 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
374 2016-10-07 Alan Modra <amodra@gmail.com>
376 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
378 2016-10-06 Alan Modra <amodra@gmail.com>
380 * aarch64-opc.c: Spell fall through comments consistently.
381 * i386-dis.c: Likewise.
382 * aarch64-dis.c: Add missing fall through comments.
383 * aarch64-opc.c: Likewise.
384 * arc-dis.c: Likewise.
385 * arm-dis.c: Likewise.
386 * i386-dis.c: Likewise.
387 * m68k-dis.c: Likewise.
388 * mep-asm.c: Likewise.
389 * ns32k-dis.c: Likewise.
390 * sh-dis.c: Likewise.
391 * tic4x-dis.c: Likewise.
392 * tic6x-dis.c: Likewise.
393 * vax-dis.c: Likewise.
395 2016-10-06 Alan Modra <amodra@gmail.com>
397 * arc-ext.c (create_map): Add missing break.
398 * msp430-decode.opc (encode_as): Likewise.
399 * msp430-decode.c: Regenerate.
401 2016-10-06 Alan Modra <amodra@gmail.com>
403 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
404 * crx-dis.c (print_insn_crx): Likewise.
406 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
409 * i386-dis.c (putop): Don't assign alt twice.
411 2016-09-29 Jiong Wang <jiong.wang@arm.com>
414 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
416 2016-09-29 Alan Modra <amodra@gmail.com>
418 * ppc-opc.c (L): Make compulsory.
419 (LOPT): New, optional form of L.
420 (HTM_R): Define as LOPT.
422 (L32OPT): New, optional for 32-bit L.
423 (L2OPT): New, 2-bit L for dcbf.
426 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
427 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
429 <tlbiel, tlbie>: Use LOPT.
430 <wclr, wclrall>: Use L2.
432 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
434 * Makefile.in: Regenerate.
435 * configure: Likewise.
437 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
439 * arc-ext-tbl.h (EXTINSN2OPF): Define.
440 (EXTINSN2OP): Use EXTINSN2OPF.
441 (bspeekm, bspop, modapp): New extension instructions.
442 * arc-opc.c (F_DNZ_ND): Define.
447 * arc-tbl.h (dbnz): New instruction.
448 (prealloc): Allow it for ARC EM.
451 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
453 * aarch64-opc.c (print_immediate_offset_address): Print spaces
454 after commas in addresses.
455 (aarch64_print_operand): Likewise.
457 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
459 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
460 rather than "should be" or "expected to be" in error messages.
462 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
464 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
465 (print_mnemonic_name): ...here.
466 (print_comment): New function.
467 (print_aarch64_insn): Call it.
468 * aarch64-opc.c (aarch64_conds): Add SVE names.
469 (aarch64_print_operand): Print alternative condition names in
472 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
474 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
475 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
476 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
477 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
478 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
479 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
480 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
481 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
482 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
483 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
484 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
485 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
486 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
487 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
488 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
489 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
490 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
491 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
492 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
493 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
494 (OP_SVE_XWU, OP_SVE_XXU): New macros.
495 (aarch64_feature_sve): New variable.
497 (_SVE_INSN): Likewise.
498 (aarch64_opcode_table): Add SVE instructions.
499 * aarch64-opc.h (extract_fields): Declare.
500 * aarch64-opc-2.c: Regenerate.
501 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
502 * aarch64-asm-2.c: Regenerate.
503 * aarch64-dis.c (extract_fields): Make global.
504 (do_misc_decoding): Handle the new SVE aarch64_ops.
505 * aarch64-dis-2.c: Regenerate.
507 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
509 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
510 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
512 * aarch64-opc.c (fields): Add corresponding entries.
513 * aarch64-asm.c (aarch64_get_variant): New function.
514 (aarch64_encode_variant_using_iclass): Likewise.
515 (aarch64_opcode_encode): Call it.
516 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
517 (aarch64_opcode_decode): Call it.
519 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
521 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
522 and FP register operands.
523 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
524 (FLD_SVE_Vn): New aarch64_field_kinds.
525 * aarch64-opc.c (fields): Add corresponding entries.
526 (aarch64_print_operand): Handle the new SVE core and FP register
528 * aarch64-opc-2.c: Regenerate.
529 * aarch64-asm-2.c: Likewise.
530 * aarch64-dis-2.c: Likewise.
532 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
534 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
536 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
537 * aarch64-opc.c (fields): Add corresponding entry.
538 (operand_general_constraint_met_p): Handle the new SVE FP immediate
540 (aarch64_print_operand): Likewise.
541 * aarch64-opc-2.c: Regenerate.
542 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
543 (ins_sve_float_zero_one): New inserters.
544 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
545 (aarch64_ins_sve_float_half_two): Likewise.
546 (aarch64_ins_sve_float_zero_one): Likewise.
547 * aarch64-asm-2.c: Regenerate.
548 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
549 (ext_sve_float_zero_one): New extractors.
550 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
551 (aarch64_ext_sve_float_half_two): Likewise.
552 (aarch64_ext_sve_float_zero_one): Likewise.
553 * aarch64-dis-2.c: Regenerate.
555 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
557 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
558 integer immediate operands.
559 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
560 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
561 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
562 * aarch64-opc.c (fields): Add corresponding entries.
563 (operand_general_constraint_met_p): Handle the new SVE integer
565 (aarch64_print_operand): Likewise.
566 (aarch64_sve_dupm_mov_immediate_p): New function.
567 * aarch64-opc-2.c: Regenerate.
568 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
569 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
570 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
571 (aarch64_ins_limm): ...here.
572 (aarch64_ins_inv_limm): New function.
573 (aarch64_ins_sve_aimm): Likewise.
574 (aarch64_ins_sve_asimm): Likewise.
575 (aarch64_ins_sve_limm_mov): Likewise.
576 (aarch64_ins_sve_shlimm): Likewise.
577 (aarch64_ins_sve_shrimm): Likewise.
578 * aarch64-asm-2.c: Regenerate.
579 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
580 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
581 * aarch64-dis.c (decode_limm): New function, split out from...
582 (aarch64_ext_limm): ...here.
583 (aarch64_ext_inv_limm): New function.
584 (decode_sve_aimm): Likewise.
585 (aarch64_ext_sve_aimm): Likewise.
586 (aarch64_ext_sve_asimm): Likewise.
587 (aarch64_ext_sve_limm_mov): Likewise.
588 (aarch64_top_bit): Likewise.
589 (aarch64_ext_sve_shlimm): Likewise.
590 (aarch64_ext_sve_shrimm): Likewise.
591 * aarch64-dis-2.c: Regenerate.
593 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
595 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
597 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
598 the AARCH64_MOD_MUL_VL entry.
599 (value_aligned_p): Cope with non-power-of-two alignments.
600 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
601 (print_immediate_offset_address): Likewise.
602 (aarch64_print_operand): Likewise.
603 * aarch64-opc-2.c: Regenerate.
604 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
605 (ins_sve_addr_ri_s9xvl): New inserters.
606 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
607 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
608 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
609 * aarch64-asm-2.c: Regenerate.
610 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
611 (ext_sve_addr_ri_s9xvl): New extractors.
612 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
613 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
614 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
615 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
616 * aarch64-dis-2.c: Regenerate.
618 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
620 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
622 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
623 (FLD_SVE_xs_22): New aarch64_field_kinds.
624 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
625 (get_operand_specific_data): New function.
626 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
627 FLD_SVE_xs_14 and FLD_SVE_xs_22.
628 (operand_general_constraint_met_p): Handle the new SVE address
630 (sve_reg): New array.
631 (get_addr_sve_reg_name): New function.
632 (aarch64_print_operand): Handle the new SVE address operands.
633 * aarch64-opc-2.c: Regenerate.
634 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
635 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
636 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
637 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
638 (aarch64_ins_sve_addr_rr_lsl): Likewise.
639 (aarch64_ins_sve_addr_rz_xtw): Likewise.
640 (aarch64_ins_sve_addr_zi_u5): Likewise.
641 (aarch64_ins_sve_addr_zz): Likewise.
642 (aarch64_ins_sve_addr_zz_lsl): Likewise.
643 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
644 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
645 * aarch64-asm-2.c: Regenerate.
646 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
647 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
648 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
649 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
650 (aarch64_ext_sve_addr_ri_u6): Likewise.
651 (aarch64_ext_sve_addr_rr_lsl): Likewise.
652 (aarch64_ext_sve_addr_rz_xtw): Likewise.
653 (aarch64_ext_sve_addr_zi_u5): Likewise.
654 (aarch64_ext_sve_addr_zz): Likewise.
655 (aarch64_ext_sve_addr_zz_lsl): Likewise.
656 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
657 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
658 * aarch64-dis-2.c: Regenerate.
660 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
662 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
663 AARCH64_OPND_SVE_PATTERN_SCALED.
664 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
665 * aarch64-opc.c (fields): Add a corresponding entry.
666 (set_multiplier_out_of_range_error): New function.
667 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
668 (operand_general_constraint_met_p): Handle
669 AARCH64_OPND_SVE_PATTERN_SCALED.
670 (print_register_offset_address): Use PRIi64 to print the
672 (aarch64_print_operand): Likewise. Handle
673 AARCH64_OPND_SVE_PATTERN_SCALED.
674 * aarch64-opc-2.c: Regenerate.
675 * aarch64-asm.h (ins_sve_scale): New inserter.
676 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
677 * aarch64-asm-2.c: Regenerate.
678 * aarch64-dis.h (ext_sve_scale): New inserter.
679 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
680 * aarch64-dis-2.c: Regenerate.
682 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
684 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
685 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
686 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
687 (FLD_SVE_prfop): Likewise.
688 * aarch64-opc.c: Include libiberty.h.
689 (aarch64_sve_pattern_array): New variable.
690 (aarch64_sve_prfop_array): Likewise.
691 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
692 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
693 AARCH64_OPND_SVE_PRFOP.
694 * aarch64-asm-2.c: Regenerate.
695 * aarch64-dis-2.c: Likewise.
696 * aarch64-opc-2.c: Likewise.
698 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
700 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
701 AARCH64_OPND_QLF_P_[ZM].
702 (aarch64_print_operand): Print /z and /m where appropriate.
704 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
706 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
707 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
708 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
709 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
710 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
711 * aarch64-opc.c (fields): Add corresponding entries here.
712 (operand_general_constraint_met_p): Check that SVE register lists
713 have the correct length. Check the ranges of SVE index registers.
714 Check for cases where p8-p15 are used in 3-bit predicate fields.
715 (aarch64_print_operand): Handle the new SVE operands.
716 * aarch64-opc-2.c: Regenerate.
717 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
718 * aarch64-asm.c (aarch64_ins_sve_index): New function.
719 (aarch64_ins_sve_reglist): Likewise.
720 * aarch64-asm-2.c: Regenerate.
721 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
722 * aarch64-dis.c (aarch64_ext_sve_index): New function.
723 (aarch64_ext_sve_reglist): Likewise.
724 * aarch64-dis-2.c: Regenerate.
726 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
728 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
729 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
730 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
731 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
734 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
736 * aarch64-opc.c (get_offset_int_reg_name): New function.
737 (print_immediate_offset_address): Likewise.
738 (print_register_offset_address): Take the base and offset
739 registers as parameters.
740 (aarch64_print_operand): Update caller accordingly. Use
741 print_immediate_offset_address.
743 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
745 * aarch64-opc.c (BANK): New macro.
746 (R32, R64): Take a register number as argument
749 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
751 * aarch64-opc.c (print_register_list): Add a prefix parameter.
752 (aarch64_print_operand): Update accordingly.
754 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
756 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
758 * aarch64-asm.h (ins_fpimm): New inserter.
759 * aarch64-asm.c (aarch64_ins_fpimm): New function.
760 * aarch64-asm-2.c: Regenerate.
761 * aarch64-dis.h (ext_fpimm): New extractor.
762 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
763 (aarch64_ext_fpimm): New function.
764 * aarch64-dis-2.c: Regenerate.
766 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
768 * aarch64-asm.c: Include libiberty.h.
769 (insert_fields): New function.
770 (aarch64_ins_imm): Use it.
771 * aarch64-dis.c (extract_fields): New function.
772 (aarch64_ext_imm): Use it.
774 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
776 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
777 with an esize parameter.
778 (operand_general_constraint_met_p): Update accordingly.
779 Fix misindented code.
780 * aarch64-asm.c (aarch64_ins_limm): Update call to
781 aarch64_logical_immediate_p.
783 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
785 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
787 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
789 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
791 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
793 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
795 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
797 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
798 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
799 xor3>: Delete mnemonics.
800 <cp_abort>: Rename mnemonic from ...
801 <cpabort>: ...to this.
802 <setb>: Change to a X form instruction.
803 <sync>: Change to 1 operand form.
804 <copy>: Delete mnemonic.
805 <copy_first>: Rename mnemonic from ...
807 <paste, paste.>: Delete mnemonics.
808 <paste_last>: Rename mnemonic from ...
809 <paste.>: ...to this.
811 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
813 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
815 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
817 * s390-mkopc.c (main): Support alternate arch strings.
819 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
821 * s390-opc.txt: Fix kmctr instruction type.
823 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
825 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
826 * i386-init.h: Regenerated.
828 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
830 * opcodes/arc-dis.c (print_insn_arc): Changed.
832 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
834 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
837 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
839 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
840 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
841 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
843 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
845 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
846 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
847 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
848 PREFIX_MOD_3_0FAE_REG_4.
849 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
850 PREFIX_MOD_3_0FAE_REG_4.
851 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
852 (cpu_flags): Add CpuPTWRITE.
853 * i386-opc.h (CpuPTWRITE): New.
854 (i386_cpu_flags): Add cpuptwrite.
855 * i386-opc.tbl: Add ptwrite instruction.
856 * i386-init.h: Regenerated.
857 * i386-tbl.h: Likewise.
859 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
861 * arc-dis.h: Wrap around in extern "C".
863 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
865 * aarch64-tbl.h (V8_2_INSN): New macro.
866 (aarch64_opcode_table): Use it.
868 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
870 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
871 CORE_INSN, __FP_INSN and SIMD_INSN.
873 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
875 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
876 (aarch64_opcode_table): Update uses accordingly.
878 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
879 Kwok Cheung Yeung <kcy@codesourcery.com>
882 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
883 'e_cmplwi' to 'e_cmpli' instead.
884 (OPVUPRT, OPVUPRT_MASK): Define.
885 (powerpc_opcodes): Add E200Z4 insns.
886 (vle_opcodes): Add context save/restore insns.
888 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
890 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
891 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
894 2016-07-27 Graham Markall <graham.markall@embecosm.com>
896 * arc-nps400-tbl.h: Change block comments to GNU format.
897 * arc-dis.c: Add new globals addrtypenames,
898 addrtypenames_max, and addtypeunknown.
899 (get_addrtype): New function.
900 (print_insn_arc): Print colons and address types when
902 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
903 define insert and extract functions for all address types.
904 (arc_operands): Add operands for colon and all address
906 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
907 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
908 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
909 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
910 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
911 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
913 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
915 * configure: Regenerated.
917 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
919 * arc-dis.c (skipclass): New structure.
920 (decodelist): New variable.
921 (is_compatible_p): New function.
922 (new_element): Likewise.
923 (skip_class_p): Likewise.
924 (find_format_from_table): Use skip_class_p function.
925 (find_format): Decode first the extension instructions.
926 (print_insn_arc): Select either ARCEM or ARCHS based on elf
928 (parse_option): New function.
929 (parse_disassembler_options): Likewise.
930 (print_arc_disassembler_options): Likewise.
931 (print_insn_arc): Use parse_disassembler_options function. Proper
932 select ARCv2 cpu variant.
933 * disassemble.c (disassembler_usage): Add ARC disassembler
936 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
938 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
939 annotation from the "nal" entry and reorder it beyond "bltzal".
941 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
943 * sparc-opc.c (ldtxa): New macro.
944 (sparc_opcodes): Use the macro defined above to add entries for
945 the LDTXA instructions.
946 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
949 2016-07-07 James Bowman <james.bowman@ftdichip.com>
951 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
954 2016-07-01 Jan Beulich <jbeulich@suse.com>
956 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
957 (movzb): Adjust to cover all permitted suffixes.
959 * i386-tbl.h: Re-generate.
961 2016-07-01 Jan Beulich <jbeulich@suse.com>
963 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
964 (lgdt): Remove Tbyte from non-64-bit variant.
965 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
966 xsaves64, xsavec64): Remove Disp16.
967 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
968 Remove Disp32S from non-64-bit variants. Remove Disp16 from
970 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
971 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
972 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
974 * i386-tbl.h: Re-generate.
976 2016-07-01 Jan Beulich <jbeulich@suse.com>
978 * i386-opc.tbl (xlat): Remove RepPrefixOk.
979 * i386-tbl.h: Re-generate.
981 2016-06-30 Yao Qi <yao.qi@linaro.org>
983 * arm-dis.c (print_insn): Fix typo in comment.
985 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
987 * aarch64-opc.c (operand_general_constraint_met_p): Check the
988 range of ldst_elemlist operands.
989 (print_register_list): Use PRIi64 to print the index.
990 (aarch64_print_operand): Likewise.
992 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
994 * mcore-opc.h: Remove sentinal.
995 * mcore-dis.c (print_insn_mcore): Adjust.
997 2016-06-23 Graham Markall <graham.markall@embecosm.com>
999 * arc-opc.c: Correct description of availability of NPS400
1002 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1004 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1005 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1006 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1007 xor3>: New mnemonics.
1008 <setb>: Change to a VX form instruction.
1009 (insert_sh6): Add support for rldixor.
1010 (extract_sh6): Likewise.
1012 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1014 * arc-ext.h: Wrap in extern C.
1016 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1018 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1019 Use same method for determining instruction length on ARC700 and
1021 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1022 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1023 with the NPS400 subclass.
1024 * arc-opc.c: Likewise.
1026 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1028 * sparc-opc.c (rdasr): New macro.
1034 (sparc_opcodes): Use the macros above to fix and expand the
1035 definition of read/write instructions from/to
1036 asr/privileged/hyperprivileged instructions.
1037 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1038 %hva_mask_nz. Prefer softint_set and softint_clear over
1039 set_softint and clear_softint.
1040 (print_insn_sparc): Support %ver in Rd.
1042 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1044 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1045 architecture according to the hardware capabilities they require.
1047 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1049 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1050 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1051 bfd_mach_sparc_v9{c,d,e,v,m}.
1052 * sparc-opc.c (MASK_V9C): Define.
1053 (MASK_V9D): Likewise.
1054 (MASK_V9E): Likewise.
1055 (MASK_V9V): Likewise.
1056 (MASK_V9M): Likewise.
1057 (v6): Add MASK_V9{C,D,E,V,M}.
1058 (v6notlet): Likewise.
1062 (v9andleon): Likewise.
1070 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1072 2016-06-15 Nick Clifton <nickc@redhat.com>
1074 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1075 constants to match expected behaviour.
1076 (nds32_parse_opcode): Likewise. Also for whitespace.
1078 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1080 * arc-opc.c (extract_rhv1): Extract value from insn.
1082 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1084 * arc-nps400-tbl.h: Add ldbit instruction.
1085 * arc-opc.c: Add flag classes required for ldbit.
1087 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1089 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1090 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1091 support the above instructions.
1093 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1095 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1096 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1097 csma, cbba, zncv, and hofs.
1098 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1099 support the above instructions.
1101 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1103 * arc-nps400-tbl.h: Add andab and orab instructions.
1105 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1107 * arc-nps400-tbl.h: Add addl-like instructions.
1109 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1111 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1113 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1115 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1118 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1120 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1122 (init_disasm): Handle new command line option "insnlength".
1123 (print_s390_disassembler_options): Mention new option in help
1125 (print_insn_s390): Use the encoded insn length when dumping
1126 unknown instructions.
1128 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1130 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1131 to the address and set as symbol address for LDS/ STS immediate operands.
1133 2016-06-07 Alan Modra <amodra@gmail.com>
1135 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1136 cpu for "vle" to e500.
1137 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1138 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1139 (PPCNONE): Delete, substitute throughout.
1140 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1141 except for major opcode 4 and 31.
1142 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1144 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1146 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1147 ARM_EXT_RAS in relevant entries.
1149 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1152 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1155 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1158 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1159 (indir_v_mode): New.
1160 Add comments for '&'.
1161 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1162 (putop): Handle '&'.
1163 (intel_operand_size): Handle indir_v_mode.
1164 (OP_E_register): Likewise.
1165 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1166 64-bit indirect call/jmp for AMD64.
1167 * i386-tbl.h: Regenerated
1169 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1171 * arc-dis.c (struct arc_operand_iterator): New structure.
1172 (find_format_from_table): All the old content from find_format,
1173 with some minor adjustments, and parameter renaming.
1174 (find_format_long_instructions): New function.
1175 (find_format): Rewritten.
1176 (arc_insn_length): Add LSB parameter.
1177 (extract_operand_value): New function.
1178 (operand_iterator_next): New function.
1179 (print_insn_arc): Use new functions to find opcode, and iterator
1181 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1182 (extract_nps_3bit_dst_short): New function.
1183 (insert_nps_3bit_src2_short): New function.
1184 (extract_nps_3bit_src2_short): New function.
1185 (insert_nps_bitop1_size): New function.
1186 (extract_nps_bitop1_size): New function.
1187 (insert_nps_bitop2_size): New function.
1188 (extract_nps_bitop2_size): New function.
1189 (insert_nps_bitop_mod4_msb): New function.
1190 (extract_nps_bitop_mod4_msb): New function.
1191 (insert_nps_bitop_mod4_lsb): New function.
1192 (extract_nps_bitop_mod4_lsb): New function.
1193 (insert_nps_bitop_dst_pos3_pos4): New function.
1194 (extract_nps_bitop_dst_pos3_pos4): New function.
1195 (insert_nps_bitop_ins_ext): New function.
1196 (extract_nps_bitop_ins_ext): New function.
1197 (arc_operands): Add new operands.
1198 (arc_long_opcodes): New global array.
1199 (arc_num_long_opcodes): New global.
1200 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1202 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1204 * nds32-asm.h: Add extern "C".
1205 * sh-opc.h: Likewise.
1207 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1209 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1210 0,b,limm to the rflt instruction.
1212 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1214 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1217 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1220 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1221 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1222 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1223 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1224 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1225 * i386-init.h: Regenerated.
1227 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1230 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1231 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1232 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1233 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1234 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1235 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1236 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1237 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1238 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1239 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1240 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1241 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1242 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1243 CpuRegMask for AVX512.
1244 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1246 (set_bitfield_from_cpu_flag_init): New function.
1247 (set_bitfield): Remove const on f. Call
1248 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1249 * i386-opc.h (CpuRegMMX): New.
1250 (CpuRegXMM): Likewise.
1251 (CpuRegYMM): Likewise.
1252 (CpuRegZMM): Likewise.
1253 (CpuRegMask): Likewise.
1254 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1256 * i386-init.h: Regenerated.
1257 * i386-tbl.h: Likewise.
1259 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1262 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1263 (opcode_modifiers): Add AMD64 and Intel64.
1264 (main): Properly verify CpuMax.
1265 * i386-opc.h (CpuAMD64): Removed.
1266 (CpuIntel64): Likewise.
1267 (CpuMax): Set to CpuNo64.
1268 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1270 (Intel64): Likewise.
1271 (i386_opcode_modifier): Add amd64 and intel64.
1272 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1274 * i386-init.h: Regenerated.
1275 * i386-tbl.h: Likewise.
1277 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1280 * i386-gen.c (main): Fail if CpuMax is incorrect.
1281 * i386-opc.h (CpuMax): Set to CpuIntel64.
1282 * i386-tbl.h: Regenerated.
1284 2016-05-27 Nick Clifton <nickc@redhat.com>
1287 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1288 (msp430dis_opcode_unsigned): New function.
1289 (msp430dis_opcode_signed): New function.
1290 (msp430_singleoperand): Use the new opcode reading functions.
1291 Only disassenmble bytes if they were successfully read.
1292 (msp430_doubleoperand): Likewise.
1293 (msp430_branchinstr): Likewise.
1294 (msp430x_callx_instr): Likewise.
1295 (print_insn_msp430): Check that it is safe to read bytes before
1296 attempting disassembly. Use the new opcode reading functions.
1298 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1300 * ppc-opc.c (CY): New define. Document it.
1301 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1303 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1305 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1306 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1307 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1308 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1310 * i386-init.h: Regenerated.
1312 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1315 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1316 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1317 * i386-init.h: Regenerated.
1319 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1321 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1322 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1323 * i386-init.h: Regenerated.
1325 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1327 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1329 (print_insn_arc): Set insn_type information.
1330 * arc-opc.c (C_CC): Add F_CLASS_COND.
1331 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1332 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1333 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1334 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1335 (brne, brne_s, jeq_s, jne_s): Likewise.
1337 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1339 * arc-tbl.h (neg): New instruction variant.
1341 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1343 * arc-dis.c (find_format, find_format, get_auxreg)
1344 (print_insn_arc): Changed.
1345 * arc-ext.h (INSERT_XOP): Likewise.
1347 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1349 * tic54x-dis.c (sprint_mmr): Adjust.
1350 * tic54x-opc.c: Likewise.
1352 2016-05-19 Alan Modra <amodra@gmail.com>
1354 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1356 2016-05-19 Alan Modra <amodra@gmail.com>
1358 * ppc-opc.c: Formatting.
1359 (NSISIGNOPT): Define.
1360 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1362 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1364 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1365 replacing references to `micromips_ase' throughout.
1366 (_print_insn_mips): Don't use file-level microMIPS annotation to
1367 determine the disassembly mode with the symbol table.
1369 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1371 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1373 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1375 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1377 * mips-opc.c (D34): New macro.
1378 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1380 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1382 * i386-dis.c (prefix_table): Add RDPID instruction.
1383 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1384 (cpu_flags): Add RDPID bitfield.
1385 * i386-opc.h (enum): Add RDPID element.
1386 (i386_cpu_flags): Add RDPID field.
1387 * i386-opc.tbl: Add RDPID instruction.
1388 * i386-init.h: Regenerate.
1389 * i386-tbl.h: Regenerate.
1391 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1393 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1394 branch type of a symbol.
1395 (print_insn): Likewise.
1397 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1399 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1400 Mainline Security Extensions instructions.
1401 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1402 Extensions instructions.
1403 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1405 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1408 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1410 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1412 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1414 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1415 (arcExtMap_genOpcode): Likewise.
1416 * arc-opc.c (arg_32bit_rc): Define new variable.
1417 (arg_32bit_u6): Likewise.
1418 (arg_32bit_limm): Likewise.
1420 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1422 * aarch64-gen.c (VERIFIER): Define.
1423 * aarch64-opc.c (VERIFIER): Define.
1424 (verify_ldpsw): Use static linkage.
1425 * aarch64-opc.h (verify_ldpsw): Remove.
1426 * aarch64-tbl.h: Use VERIFIER for verifiers.
1428 2016-04-28 Nick Clifton <nickc@redhat.com>
1431 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1432 * aarch64-opc.c (verify_ldpsw): New function.
1433 * aarch64-opc.h (verify_ldpsw): New prototype.
1434 * aarch64-tbl.h: Add initialiser for verifier field.
1435 (LDPSW): Set verifier to verify_ldpsw.
1437 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1441 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1442 smaller than address size.
1444 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1446 * alpha-dis.c: Regenerate.
1447 * crx-dis.c: Likewise.
1448 * disassemble.c: Likewise.
1449 * epiphany-opc.c: Likewise.
1450 * fr30-opc.c: Likewise.
1451 * frv-opc.c: Likewise.
1452 * ip2k-opc.c: Likewise.
1453 * iq2000-opc.c: Likewise.
1454 * lm32-opc.c: Likewise.
1455 * lm32-opinst.c: Likewise.
1456 * m32c-opc.c: Likewise.
1457 * m32r-opc.c: Likewise.
1458 * m32r-opinst.c: Likewise.
1459 * mep-opc.c: Likewise.
1460 * mt-opc.c: Likewise.
1461 * or1k-opc.c: Likewise.
1462 * or1k-opinst.c: Likewise.
1463 * tic80-opc.c: Likewise.
1464 * xc16x-opc.c: Likewise.
1465 * xstormy16-opc.c: Likewise.
1467 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1469 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1470 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1471 calcsd, and calcxd instructions.
1472 * arc-opc.c (insert_nps_bitop_size): Delete.
1473 (extract_nps_bitop_size): Delete.
1474 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1475 (extract_nps_qcmp_m3): Define.
1476 (extract_nps_qcmp_m2): Define.
1477 (extract_nps_qcmp_m1): Define.
1478 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1479 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1480 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1481 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1482 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1485 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1487 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1489 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1491 * Makefile.in: Regenerated with automake 1.11.6.
1492 * aclocal.m4: Likewise.
1494 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1496 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1498 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1499 (extract_nps_cmem_uimm16): New function.
1500 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1502 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1504 * arc-dis.c (arc_insn_length): New function.
1505 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1506 (find_format): Change insnLen parameter to unsigned.
1508 2016-04-13 Nick Clifton <nickc@redhat.com>
1511 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1512 the LD.B and LD.BU instructions.
1514 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1516 * arc-dis.c (find_format): Check for extension flags.
1517 (print_flags): New function.
1518 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1520 * arc-ext.c (arcExtMap_coreRegName): Use
1521 LAST_EXTENSION_CORE_REGISTER.
1522 (arcExtMap_coreReadWrite): Likewise.
1523 (dump_ARC_extmap): Update printing.
1524 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1525 (arc_aux_regs): Add cpu field.
1526 * arc-regs.h: Add cpu field, lower case name aux registers.
1528 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1530 * arc-tbl.h: Add rtsc, sleep with no arguments.
1532 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1534 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1536 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1537 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1538 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1539 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1540 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1541 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1542 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1543 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1544 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1545 (arc_opcode arc_opcodes): Null terminate the array.
1546 (arc_num_opcodes): Remove.
1547 * arc-ext.h (INSERT_XOP): Define.
1548 (extInstruction_t): Likewise.
1549 (arcExtMap_instName): Delete.
1550 (arcExtMap_insn): New function.
1551 (arcExtMap_genOpcode): Likewise.
1552 * arc-ext.c (ExtInstruction): Remove.
1553 (create_map): Zero initialize instruction fields.
1554 (arcExtMap_instName): Remove.
1555 (arcExtMap_insn): New function.
1556 (dump_ARC_extmap): More info while debuging.
1557 (arcExtMap_genOpcode): New function.
1558 * arc-dis.c (find_format): New function.
1559 (print_insn_arc): Use find_format.
1560 (arc_get_disassembler): Enable dump_ARC_extmap only when
1563 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1565 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1566 instruction bits out.
1568 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1570 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1571 * arc-opc.c (arc_flag_operands): Add new flags.
1572 (arc_flag_classes): Add new classes.
1574 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1576 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1578 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1580 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1581 encode1, rflt, crc16, and crc32 instructions.
1582 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1583 (arc_flag_classes): Add C_NPS_R.
1584 (insert_nps_bitop_size_2b): New function.
1585 (extract_nps_bitop_size_2b): Likewise.
1586 (insert_nps_bitop_uimm8): Likewise.
1587 (extract_nps_bitop_uimm8): Likewise.
1588 (arc_operands): Add new operand entries.
1590 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1592 * arc-regs.h: Add a new subclass field. Add double assist
1593 accumulator register values.
1594 * arc-tbl.h: Use DPA subclass to mark the double assist
1595 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1596 * arc-opc.c (RSP): Define instead of SP.
1597 (arc_aux_regs): Add the subclass field.
1599 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1601 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1603 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1605 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1608 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1610 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1611 issues. No functional changes.
1613 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1615 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1616 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1617 (RTT): Remove duplicate.
1618 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1619 (PCT_CONFIG*): Remove.
1620 (D1L, D1H, D2H, D2L): Define.
1622 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1624 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1626 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1628 * arc-tbl.h (invld07): Remove.
1629 * arc-ext-tbl.h: New file.
1630 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1631 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1633 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1635 Fix -Wstack-usage warnings.
1636 * aarch64-dis.c (print_operands): Substitute size.
1637 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1639 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1641 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1642 to get a proper diagnostic when an invalid ASR register is used.
1644 2016-03-22 Nick Clifton <nickc@redhat.com>
1646 * configure: Regenerate.
1648 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1650 * arc-nps400-tbl.h: New file.
1651 * arc-opc.c: Add top level comment.
1652 (insert_nps_3bit_dst): New function.
1653 (extract_nps_3bit_dst): New function.
1654 (insert_nps_3bit_src2): New function.
1655 (extract_nps_3bit_src2): New function.
1656 (insert_nps_bitop_size): New function.
1657 (extract_nps_bitop_size): New function.
1658 (arc_flag_operands): Add nps400 entries.
1659 (arc_flag_classes): Add nps400 entries.
1660 (arc_operands): Add nps400 entries.
1661 (arc_opcodes): Add nps400 include.
1663 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1665 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1666 the new class enum values.
1668 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1670 * arc-dis.c (print_insn_arc): Handle nps400.
1672 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1674 * arc-opc.c (BASE): Delete.
1676 2016-03-18 Nick Clifton <nickc@redhat.com>
1679 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1680 of MOV insn that aliases an ORR insn.
1682 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1684 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1686 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1688 * mcore-opc.h: Add const qualifiers.
1689 * microblaze-opc.h (struct op_code_struct): Likewise.
1690 * sh-opc.h: Likewise.
1691 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1692 (tic4x_print_op): Likewise.
1694 2016-03-02 Alan Modra <amodra@gmail.com>
1696 * or1k-desc.h: Regenerate.
1697 * fr30-ibld.c: Regenerate.
1698 * rl78-decode.c: Regenerate.
1700 2016-03-01 Nick Clifton <nickc@redhat.com>
1703 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1705 2016-02-24 Renlin Li <renlin.li@arm.com>
1707 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1708 (print_insn_coprocessor): Support fp16 instructions.
1710 2016-02-24 Renlin Li <renlin.li@arm.com>
1712 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1713 vminnm, vrint(mpna).
1715 2016-02-24 Renlin Li <renlin.li@arm.com>
1717 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1718 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1720 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1722 * i386-dis.c (print_insn): Parenthesize expression to prevent
1723 truncated addresses.
1726 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1727 Janek van Oirschot <jvanoirs@synopsys.com>
1729 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1732 2016-02-04 Nick Clifton <nickc@redhat.com>
1735 * msp430-dis.c (print_insn_msp430): Add a special case for
1736 decoding an RRC instruction with the ZC bit set in the extension
1739 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1741 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1742 * epiphany-ibld.c: Regenerate.
1743 * fr30-ibld.c: Regenerate.
1744 * frv-ibld.c: Regenerate.
1745 * ip2k-ibld.c: Regenerate.
1746 * iq2000-ibld.c: Regenerate.
1747 * lm32-ibld.c: Regenerate.
1748 * m32c-ibld.c: Regenerate.
1749 * m32r-ibld.c: Regenerate.
1750 * mep-ibld.c: Regenerate.
1751 * mt-ibld.c: Regenerate.
1752 * or1k-ibld.c: Regenerate.
1753 * xc16x-ibld.c: Regenerate.
1754 * xstormy16-ibld.c: Regenerate.
1756 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1758 * epiphany-dis.c: Regenerated from latest cpu files.
1760 2016-02-01 Michael McConville <mmcco@mykolab.com>
1762 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1765 2016-01-25 Renlin Li <renlin.li@arm.com>
1767 * arm-dis.c (mapping_symbol_for_insn): New function.
1768 (find_ifthen_state): Call mapping_symbol_for_insn().
1770 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1772 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1773 of MSR UAO immediate operand.
1775 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1777 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1778 instruction support.
1780 2016-01-17 Alan Modra <amodra@gmail.com>
1782 * configure: Regenerate.
1784 2016-01-14 Nick Clifton <nickc@redhat.com>
1786 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1787 instructions that can support stack pointer operations.
1788 * rl78-decode.c: Regenerate.
1789 * rl78-dis.c: Fix display of stack pointer in MOVW based
1792 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1794 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1795 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1796 erxtatus_el1 and erxaddr_el1.
1798 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1800 * arm-dis.c (arm_opcodes): Add "esb".
1801 (thumb_opcodes): Likewise.
1803 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1805 * ppc-opc.c <xscmpnedp>: Delete.
1806 <xvcmpnedp>: Likewise.
1807 <xvcmpnedp.>: Likewise.
1808 <xvcmpnesp>: Likewise.
1809 <xvcmpnesp.>: Likewise.
1811 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1814 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1817 2016-01-01 Alan Modra <amodra@gmail.com>
1819 Update year range in copyright notice of all files.
1821 For older changes see ChangeLog-2015
1823 Copyright (C) 2016 Free Software Foundation, Inc.
1825 Copying and distribution of this file, with or without modification,
1826 are permitted in any medium without royalty provided the copyright
1827 notice and this notice are preserved.
1833 version-control: never