1 2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
3 * configure: Regenerated.
5 2015-07-23 Alan Modra <amodra@gmail.com>
8 * i386-dis.c (get64): Avoid signed integer overflow.
10 2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
13 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
14 "EXEvexHalfBcstXmmq" for the second operand.
15 (EVEX_W_0F79_P_2): Likewise.
16 (EVEX_W_0F7A_P_2): Likewise.
17 (EVEX_W_0F7B_P_2): Likewise.
19 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
21 * arm-dis.c (print_insn_coprocessor): Added support for quarter
22 float bitfield format.
23 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
24 quarter float bitfield format.
26 2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
28 * configure: Regenerated.
30 2015-07-03 Alan Modra <amodra@gmail.com>
32 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
33 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
34 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
36 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
37 Cesar Philippidis <cesar@codesourcery.com>
39 * nios2-dis.c (nios2_extract_opcode): New.
40 (nios2_disassembler_state): New.
41 (nios2_find_opcode_hash): Use mach parameter to select correct
43 (nios2_print_insn_arg): Extend to support new R2 argument letters
45 (print_insn_nios2): Check for 16-bit instruction at end of memory.
46 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
47 (NIOS2_NUM_OPCODES): Rename to...
48 (NIOS2_NUM_R1_OPCODES): This.
49 (nios2_r2_opcodes): New.
50 (NIOS2_NUM_R2_OPCODES): New.
51 (nios2_num_r2_opcodes): New.
52 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
53 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
54 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
55 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
56 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
58 2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
60 * i386-dis.c (OP_Mwaitx): New.
61 (rm_table): Add monitorx/mwaitx.
62 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
63 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
64 (operand_type_init): Add CpuMWAITX.
65 * i386-opc.h (CpuMWAITX): New.
66 (i386_cpu_flags): Add cpumwaitx.
67 * i386-opc.tbl: Add monitorx and mwaitx.
68 * i386-init.h: Regenerated.
69 * i386-tbl.h: Likewise.
71 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
73 * ppc-opc.c (insert_ls): Test for invalid LS operands.
74 (insert_esync): New function.
75 (LS, WC): Use insert_ls.
76 (ESYNC): Use insert_esync.
78 2015-06-22 Nick Clifton <nickc@redhat.com>
80 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
81 requested region lies beyond it.
82 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
83 looking for 32-bit insns.
84 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
86 * sh-dis.c (print_insn_sh): Likewise.
87 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
88 blocks of instructions.
89 * vax-dis.c (print_insn_vax): Check that the requested address
90 does not clash with the stop_vma.
92 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
94 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
95 * ppc-opc.c (FXM4): Add non-zero optional value.
98 (insert_fxm): Handle new default operand value.
99 (extract_fxm): Likewise.
100 (insert_tbr): Likewise.
101 (extract_tbr): Likewise.
103 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
105 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
107 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
109 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
111 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
113 * ppc-opc.c: Add comment accidentally removed by old commit.
116 2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
118 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
120 2015-06-04 Nick Clifton <nickc@redhat.com>
123 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
125 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
127 * arm-dis.c (arm_opcodes): Add "setpan".
128 (thumb_opcodes): Add "setpan".
130 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
132 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
135 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
137 * aarch64-tbl.h (aarch64_feature_rdma): New.
139 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
140 * aarch64-asm-2.c: Regenerate.
141 * aarch64-dis-2.c: Regenerate.
142 * aarch64-opc-2.c: Regenerate.
144 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
146 * aarch64-tbl.h (aarch64_feature_lor): New.
148 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
150 * aarch64-asm-2.c: Regenerate.
151 * aarch64-dis-2.c: Regenerate.
152 * aarch64-opc-2.c: Regenerate.
154 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
156 * aarch64-opc.c (F_ARCHEXT): New.
157 (aarch64_sys_regs): Add "pan".
158 (aarch64_sys_reg_supported_p): New.
159 (aarch64_pstatefields): Add "pan".
160 (aarch64_pstatefield_supported_p): New.
162 2015-06-01 Jan Beulich <jbeulich@suse.com>
164 * i386-tbl.h: Regenerate.
166 2015-06-01 Jan Beulich <jbeulich@suse.com>
168 * i386-dis.c (print_insn): Swap rounding mode specifier and
169 general purpose register in Intel mode.
171 2015-06-01 Jan Beulich <jbeulich@suse.com>
173 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
174 * i386-tbl.h: Regenerate.
176 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
178 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
179 * i386-init.h: Regenerated.
181 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
184 * i386-dis.c: Add comments for '@'.
185 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
186 (enum x86_64_isa): New.
188 (print_i386_disassembler_options): Add amd64 and intel64.
189 (print_insn): Handle amd64 and intel64.
191 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
192 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
193 * i386-opc.h (AMD64): New.
194 (CpuIntel64): Likewise.
195 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
196 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
197 Mark direct call/jmp without Disp16|Disp32 as Intel64.
198 * i386-init.h: Regenerated.
199 * i386-tbl.h: Likewise.
201 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
203 * ppc-opc.c (IH) New define.
204 (powerpc_opcodes) <wait>: Do not enable for POWER7.
205 <tlbie>: Add RS operand for POWER7.
206 <slbia>: Add IH operand for POWER6.
208 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
210 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
213 * i386-tbl.h: Regenerated.
215 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
217 * configure.ac: Support bfd_iamcu_arch.
218 * disassemble.c (disassembler): Support bfd_iamcu_arch.
219 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
220 CPU_IAMCU_COMPAT_FLAGS.
221 (cpu_flags): Add CpuIAMCU.
222 * i386-opc.h (CpuIAMCU): New.
223 (i386_cpu_flags): Add cpuiamcu.
224 * configure: Regenerated.
225 * i386-init.h: Likewise.
226 * i386-tbl.h: Likewise.
228 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
231 * i386-dis.c (X86_64_E8): New.
232 (X86_64_E9): Likewise.
233 Update comments on 'T', 'U', 'V'. Add comments for '^'.
234 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
235 (x86_64_table): Add X86_64_E8 and X86_64_E9.
236 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
238 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
241 2015-04-30 DJ Delorie <dj@redhat.com>
243 * disassemble.c (disassembler): Choose suitable disassembler based
245 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
246 it to decode mul/div insns.
247 * rl78-decode.c: Regenerate.
248 * rl78-dis.c (print_insn_rl78): Rename to...
249 (print_insn_rl78_common): ...this, take ISA parameter.
250 (print_insn_rl78): New.
251 (print_insn_rl78_g10): New.
252 (print_insn_rl78_g13): New.
253 (print_insn_rl78_g14): New.
254 (rl78_get_disassembler): New.
256 2015-04-29 Nick Clifton <nickc@redhat.com>
258 * po/fr.po: Updated French translation.
260 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
262 * ppc-opc.c (DCBT_EO): New define.
263 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
267 <waitrsv>: Do not enable for POWER7 and later.
268 <waitimpl>: Likewise.
269 <dcbt>: Default to the two operand form of the instruction for all
270 "old" cpus. For "new" cpus, use the operand ordering that matches
271 whether the cpu is server or embedded.
274 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
276 * s390-opc.c: New instruction type VV0UU2.
277 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
280 2015-04-23 Jan Beulich <jbeulich@suse.com>
282 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
283 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
284 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
285 (vfpclasspd, vfpclassps): Add %XZ.
287 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
289 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
290 (PREFIX_UD_REPZ): Likewise.
291 (PREFIX_UD_REPNZ): Likewise.
292 (PREFIX_UD_DATA): Likewise.
293 (PREFIX_UD_ADDR): Likewise.
294 (PREFIX_UD_LOCK): Likewise.
296 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
298 * i386-dis.c (prefix_requirement): Removed.
299 (print_insn): Don't set prefix_requirement. Check
300 dp->prefix_requirement instead of prefix_requirement.
302 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
305 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
306 (PREFIX_MOD_0_0FC7_REG_6): This.
307 (PREFIX_MOD_3_0FC7_REG_6): New.
308 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
309 (prefix_table): Replace PREFIX_0FC7_REG_6 with
310 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
311 PREFIX_MOD_3_0FC7_REG_7.
312 (mod_table): Replace PREFIX_0FC7_REG_6 with
313 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
314 PREFIX_MOD_3_0FC7_REG_7.
316 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
318 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
319 (PREFIX_MANDATORY_REPNZ): Likewise.
320 (PREFIX_MANDATORY_DATA): Likewise.
321 (PREFIX_MANDATORY_ADDR): Likewise.
322 (PREFIX_MANDATORY_LOCK): Likewise.
323 (PREFIX_MANDATORY): Likewise.
324 (PREFIX_UD_SHIFT): Set to 8
325 (PREFIX_UD_REPZ): Updated.
326 (PREFIX_UD_REPNZ): Likewise.
327 (PREFIX_UD_DATA): Likewise.
328 (PREFIX_UD_ADDR): Likewise.
329 (PREFIX_UD_LOCK): Likewise.
330 (PREFIX_IGNORED_SHIFT): New.
331 (PREFIX_IGNORED_REPZ): Likewise.
332 (PREFIX_IGNORED_REPNZ): Likewise.
333 (PREFIX_IGNORED_DATA): Likewise.
334 (PREFIX_IGNORED_ADDR): Likewise.
335 (PREFIX_IGNORED_LOCK): Likewise.
336 (PREFIX_OPCODE): Likewise.
337 (PREFIX_IGNORED): Likewise.
338 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
339 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
340 (three_byte_table): Likewise.
341 (mod_table): Likewise.
342 (mandatory_prefix): Renamed to ...
343 (prefix_requirement): This.
344 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
345 Update PREFIX_90 entry.
346 (get_valid_dis386): Check prefix_requirement to see if a prefix
348 (print_insn): Replace mandatory_prefix with prefix_requirement.
350 2015-04-15 Renlin Li <renlin.li@arm.com>
352 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
353 use it for ssat and ssat16.
354 (print_insn_thumb32): Add handle case for 'D' control code.
356 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
357 H.J. Lu <hongjiu.lu@intel.com>
359 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
360 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
361 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
362 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
363 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
364 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
365 Fill prefix_requirement field.
366 (struct dis386): Add prefix_requirement field.
367 (dis386): Fill prefix_requirement field.
368 (dis386_twobyte): Ditto.
369 (twobyte_has_mandatory_prefix_: Remove.
370 (reg_table): Fill prefix_requirement field.
371 (prefix_table): Ditto.
372 (x86_64_table): Ditto.
373 (three_byte_table): Ditto.
376 (vex_len_table): Ditto.
377 (vex_w_table): Ditto.
380 (print_insn): Use prefix_requirement.
381 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
382 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
385 2015-03-30 Mike Frysinger <vapier@gentoo.org>
387 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
389 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
391 * Makefile.in: Regenerated.
393 2015-03-25 Anton Blanchard <anton@samba.org>
395 * ppc-dis.c (disassemble_init_powerpc): Only initialise
396 powerpc_opcd_indices and vle_opcd_indices once.
398 2015-03-25 Anton Blanchard <anton@samba.org>
400 * ppc-opc.c (powerpc_opcodes): Add slbfee.
402 2015-03-24 Terry Guo <terry.guo@arm.com>
404 * arm-dis.c (opcode32): Updated to use new arm feature struct.
405 (opcode16): Likewise.
406 (coprocessor_opcodes): Replace bit with feature struct.
407 (neon_opcodes): Likewise.
408 (arm_opcodes): Likewise.
409 (thumb_opcodes): Likewise.
410 (thumb32_opcodes): Likewise.
411 (print_insn_coprocessor): Likewise.
412 (print_insn_arm): Likewise.
413 (select_arm_features): Follow new feature struct.
415 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
417 * i386-dis.c (rm_table): Add clzero.
418 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
419 Add CPU_CLZERO_FLAGS.
420 (cpu_flags): Add CpuCLZERO.
421 * i386-opc.h: Add CpuCLZERO.
422 * i386-opc.tbl: Add clzero.
423 * i386-init.h: Re-generated.
424 * i386-tbl.h: Re-generated.
426 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
428 * mips-opc.c (decode_mips_operand): Fix constraint issues
429 with u and y operands.
431 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
433 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
435 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
437 * s390-opc.c: Add new IBM z13 instructions.
438 * s390-opc.txt: Likewise.
440 2015-03-10 Renlin Li <renlin.li@arm.com>
442 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
443 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
445 * aarch64-asm-2.c: Regenerate.
446 * aarch64-dis-2.c: Likewise.
447 * aarch64-opc-2.c: Likewise.
449 2015-03-03 Jiong Wang <jiong.wang@arm.com>
451 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
453 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
455 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
457 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
458 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
460 2015-02-23 Vinay <Vinay.G@kpit.com>
462 * rl78-decode.opc (MOV): Added space between two operands for
463 'mov' instruction in index addressing mode.
464 * rl78-decode.c: Regenerate.
466 2015-02-19 Pedro Alves <palves@redhat.com>
468 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
470 2015-02-10 Pedro Alves <palves@redhat.com>
471 Tom Tromey <tromey@redhat.com>
473 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
474 microblaze_and, microblaze_xor.
475 * microblaze-opc.h (opcodes): Adjust.
477 2015-01-28 James Bowman <james.bowman@ftdichip.com>
479 * Makefile.am: Add FT32 files.
480 * configure.ac: Handle FT32.
481 * disassemble.c (disassembler): Call print_insn_ft32.
482 * ft32-dis.c: New file.
483 * ft32-opc.c: New file.
484 * Makefile.in: Regenerate.
485 * configure: Regenerate.
486 * po/POTFILES.in: Regenerate.
488 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
490 * nds32-asm.c (keyword_sr): Add new system registers.
492 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
494 * s390-dis.c (s390_extract_operand): Support vector register
496 (s390_print_insn_with_opcode): Support new operands types and add
497 new handling of optional operands.
498 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
499 and include opcode/s390.h instead.
500 (struct op_struct): New field `flags'.
501 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
502 (dumpTable): Dump flags.
503 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
505 * s390-opc.c: Add new operands types, instruction formats, and
507 (s390_opformats): Add new formats for .insn.
508 * s390-opc.txt: Add new instructions.
510 2015-01-01 Alan Modra <amodra@gmail.com>
512 Update year range in copyright notice of all files.
514 For older changes see ChangeLog-2014
516 Copyright (C) 2015 Free Software Foundation, Inc.
518 Copying and distribution of this file, with or without modification,
519 are permitted in any medium without royalty provided the copyright
520 notice and this notice are preserved.
526 version-control: never