opcodes/ChangeLog

   1 2019-11-08  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (operand_type_init): Add Class= to
   4         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
   5         OPERAND_TYPE_REGZMM entries.
   6         (operand_classes): Add RegMMX and RegSIMD entries.
   7         (operand_types): Drop RegMMX and RegSIMD entries.
   8         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
   9         (RegMMX, RegSIMD): Delete.
  10         (union i386_operand_type): Remove regmmx and regsimd fields.
  11         * i386-opc.tbl (RegMMX): Define.
  12         (RegXMM, RegYMM, RegZMM): Add Class=.
  13         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
  14         Class=RegSIMD.
  15         * i386-init.h, i386-tbl.h: Re-generate.
  16
  17 2019-11-08  Jan Beulich  <jbeulich@suse.com>
  18
  19         * i386-gen.c (operand_type_init): Add Class= to
  20         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
  21         entries.
  22         (operand_classes): Add RegCR, RegDR, and RegTR entries.
  23         (operand_types): Drop Control, Debug, and Test entries.
  24         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
  25         (Control, Debug, Test): Delete.
  26         (union i386_operand_type): Remove control, debug, and test
  27         fields.
  28         * i386-opc.tbl (Control, Debug, Test): Define.
  29         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
  30         Class=RegDR, and Test by Class=RegTR.
  31         * i386-init.h, i386-tbl.h: Re-generate.
  32
  33 2019-11-08  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-gen.c (operand_type_init): Add Class= to
  36         OPERAND_TYPE_SREG entry.
  37         (operand_classes): Add SReg entry.
  38         (operand_types): Drop SReg entry.
  39         * i386-opc.h (enum operand_class): Add SReg.
  40         (SReg): Delete.
  41         (union i386_operand_type): Remove sreg field.
  42         * i386-opc.tbl (SReg): Define.
  43         * i386-reg.tbl: Replace SReg by Class=SReg.
  44         * i386-init.h, i386-tbl.h: Re-generate.
  45
  46 2019-11-08  Jan Beulich  <jbeulich@suse.com>
  47
  48         * i386-gen.c (operand_type_init): Add Class=. New
  49         OPERAND_TYPE_ANYIMM entry.
  50         (operand_classes): New.
  51         (operand_types): Drop Reg entry.
  52         (output_operand_type): New parameter "class". Process it.
  53         (process_i386_operand_type): New local variable "class".
  54         (main): Adjust static assertions.
  55         * i386-opc.h (CLASS_WIDTH): Define.
  56         (enum operand_class): New.
  57         (Reg): Replace by Class. Adjust comment.
  58         (union i386_operand_type): Replace reg by class.
  59         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
  60         Class=.
  61         * i386-reg.tbl: Replace Reg by Class=Reg.
  62         * i386-init.h: Re-generate.
  63
  64 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  65
  66         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
  67         (aarch64_opcode_table): Add data gathering hint mnemonic.
  68         * opcodes/aarch64-dis-2.c: Account for new instruction.
  69
  70 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  71
  72         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
  73
  74
  75 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  76
  77         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
  78         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
  79         aarch64_feature_f64mm): New feature sets.
  80         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
  81         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
  82         instructions.
  83         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
  84         macros.
  85         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
  86         (OP_SVE_QQQ): New qualifier.
  87         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
  88         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
  89         the movprfx constraint.
  90         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
  91         (aarch64_opcode_table): Define new instructions smmla,
  92         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
  93         uzip{1/2}, trn{1/2}.
  94         * aarch64-opc.c (operand_general_constraint_met_p): Handle
  95         AARCH64_OPND_SVE_ADDR_RI_S4x32.
  96         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
  97         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
  98         Account for new instructions.
  99         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 100         S4x32 operand.
 101         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 102
 103 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 104 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 105
 106         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 107         Armv8.6-A.
 108         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 109         (neon_opcodes): Add bfloat SIMD instructions.
 110         (print_insn_coprocessor): Add new control character %b to print
 111         condition code without checking cp_num.
 112         (print_insn_neon): Account for BFloat16 instructions that have no
 113         special top-byte handling.
 114
 115 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 116 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 117
 118         * arm-dis.c (print_insn_coprocessor,
 119         print_insn_generic_coprocessor): Create wrapper functions around
 120         the implementation of the print_insn_coprocessor control codes.
 121         (print_insn_coprocessor_1): Original print_insn_coprocessor
 122         function that now takes which array to look at as an argument.
 123         (print_insn_arm): Use both print_insn_coprocessor and
 124         print_insn_generic_coprocessor.
 125         (print_insn_thumb32): As above.
 126
 127 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 128 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 129
 130         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 131         in reglane special case.
 132         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 133         aarch64_find_next_opcode): Account for new instructions.
 134         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 135         in reglane special case.
 136         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 137         new AARCH64_OPND_QLF_S_2H qualifier.
 138         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 139         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 140         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 141         sets.
 142         (BFLOAT_SVE, BFLOAT): New feature set macros.
 143         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 144         instructions.
 145         (aarch64_opcode_table): Define new instructions bfdot,
 146         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 147         bfcvtn2, bfcvt.
 148
 149 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 150 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 151
 152         * aarch64-tbl.h (ARMV8_6): New macro.
 153
 154 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-dis.c (prefix_table): Add mcommit.
 157         (rm_table): Add rdpru.
 158         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 159         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 160         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 161         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 162         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 163         * i386-opc.tbl (mcommit, rdpru): New.
 164         * i386-init.h, i386-tbl.h: Re-generate.
 165
 166 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 169         "names32" instead.
 170         (OP_Monitor): Drop local variable "op1_names", re-purpose
 171         "names" for it instead, and replace former "names" uses by
 172         "names32" ones.
 173
 174 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 175
 176         PR/gas 25167
 177         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 178         operand-less forms.
 179         * opcodes/i386-tbl.h: Re-generate.
 180
 181 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 182
 183         * i386-dis.c (OP_Mwaitx): Delete.
 184         (prefix_table): Use OP_Mwait for mwaitx entry.
 185         (OP_Mwait): Also handle mwaitx.
 186
 187 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 188
 189         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 190         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 191         (prefix_table): Add respective entries.
 192         (rm_table): Link to those entries.
 193
 194 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 195
 196         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 197         (REG_0F1C_P_0_MOD_0): ... this.
 198         (REG_0F1E_MOD_3): Rename to ...
 199         (REG_0F1E_P_1_MOD_3): ... this.
 200         (RM_0F01_REG_5): Rename to ...
 201         (RM_0F01_REG_5_MOD_3): ... this.
 202         (RM_0F01_REG_7): Rename to ...
 203         (RM_0F01_REG_7_MOD_3): ... this.
 204         (RM_0F1E_MOD_3_REG_7): Rename to ...
 205         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 206         (RM_0FAE_REG_6): Rename to ...
 207         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 208         (RM_0FAE_REG_7): Rename to ...
 209         (RM_0FAE_REG_7_MOD_3): ... this.
 210         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 211         (PREFIX_0F01_REG_5_MOD_0): ... this.
 212         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 213         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 214         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 215         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 216         (PREFIX_0FAE_REG_0): Rename to ...
 217         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 218         (PREFIX_0FAE_REG_1): Rename to ...
 219         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 220         (PREFIX_0FAE_REG_2): Rename to ...
 221         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 222         (PREFIX_0FAE_REG_3): Rename to ...
 223         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 224         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 225         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 226         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 227         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 228         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 229         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 230         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 231         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 232         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 233         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 234         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 235         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 236         (PREFIX_0FAE_REG_7): Rename to ...
 237         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 238         (PREFIX_MOD_0_0FC3): Rename to ...
 239         (PREFIX_0FC3_MOD_0): ... this.
 240         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 241         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 242         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 243         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 244         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 245         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 246         (reg_table, prefix_table, mod_table, rm_table): Adjust
 247         accordingly.
 248
 249 2019-11-04  Nick Clifton  <nickc@redhat.com>
 250
 251         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 252         of a v850 system register.  Move the v850_sreg_names array into
 253         this function.
 254         (get_v850_reg_name): Likewise for ordinary register names.
 255         (get_v850_vreg_name): Likewise for vector register names.
 256         (get_v850_cc_name): Likewise for condition codes.
 257         * get_v850_float_cc_name): Likewise for floating point condition
 258         codes.
 259         (get_v850_cacheop_name): Likewise for cache-ops.
 260         (get_v850_prefop_name): Likewise for pref-ops.
 261         (disassemble): Use the new accessor functions.
 262
 263 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 264
 265         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 266         immediate for the writeback form of ldraa/ldrab if it is 0.
 267         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 268         * aarch64-opc-2.c: Regenerated.
 269
 270 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 271
 272         * i386-gen.c (operand_type_shorthands): Delete.
 273         (operand_type_init): Expand previous shorthands.
 274         (set_bitfield_from_shorthand): Rename back to ...
 275         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 276         of operand_type_init[].
 277         (set_bitfield): Adjust call to the above function.
 278         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 279         RegXMM, RegYMM, RegZMM): Define.
 280         * i386-reg.tbl: Expand prior shorthands.
 281
 282 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 283
 284         * i386-gen.c (output_i386_opcode): Change order of fields
 285         emitted to output.
 286         * i386-opc.h (struct insn_template): Move operands field.
 287         Convert extension_opcode field to unsigned short.
 288         * i386-tbl.h: Re-generate.
 289
 290 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 291
 292         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 293         of W.
 294         * i386-opc.h (W): Extend comment.
 295         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 296         general purpose variants not allowing for byte operands.
 297         * i386-tbl.h: Re-generate.
 298
 299 2019-10-29  Nick Clifton  <nickc@redhat.com>
 300
 301         * tic30-dis.c (print_branch): Correct size of operand array.
 302
 303 2019-10-29  Nick Clifton  <nickc@redhat.com>
 304
 305         * d30v-dis.c (print_insn): Check that operand index is valid
 306         before attempting to access the operands array.
 307
 308 2019-10-29  Nick Clifton  <nickc@redhat.com>
 309
 310         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 311         locating the bit to be tested.
 312
 313 2019-10-29  Nick Clifton  <nickc@redhat.com>
 314
 315         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 316         values.
 317         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 318         (print_insn_s12z):  Check for illegal size values.
 319
 320 2019-10-28  Nick Clifton  <nickc@redhat.com>
 321
 322         * csky-dis.c (csky_chars_to_number): Check for a negative
 323         count. Use an unsigned integer to construct the return value.
 324
 325 2019-10-28  Nick Clifton  <nickc@redhat.com>
 326
 327         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 328         operand buffer.  Set value to 15 not 13.
 329         (get_register_operand): Use OPERAND_BUFFER_LEN.
 330         (get_indirect_operand): Likewise.
 331         (print_two_operand): Likewise.
 332         (print_three_operand): Likewise.
 333         (print_oar_insn): Likewise.
 334
 335 2019-10-28  Nick Clifton  <nickc@redhat.com>
 336
 337         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 338         (bit_extract_simple): Likewise.
 339         (bit_copy): Likewise.
 340         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 341         index_offset array are not accessed.
 342
 343 2019-10-28  Nick Clifton  <nickc@redhat.com>
 344
 345         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 346         operand.
 347
 348 2019-10-25  Nick Clifton  <nickc@redhat.com>
 349
 350         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 351         access to opcodes.op array element.
 352
 353 2019-10-23  Nick Clifton  <nickc@redhat.com>
 354
 355         * rx-dis.c (get_register_name): Fix spelling typo in error
 356         message.
 357         (get_condition_name, get_flag_name, get_double_register_name)
 358         (get_double_register_high_name, get_double_register_low_name)
 359         (get_double_control_register_name, get_double_condition_name)
 360         (get_opsize_name, get_size_name): Likewise.
 361
 362 2019-10-22  Nick Clifton  <nickc@redhat.com>
 363
 364         * rx-dis.c (get_size_name): New function.  Provides safe
 365         access to name array.
 366         (get_opsize_name): Likewise.
 367         (print_insn_rx): Use the accessor functions.
 368
 369 2019-10-16  Nick Clifton  <nickc@redhat.com>
 370
 371         * rx-dis.c (get_register_name): New function.  Provides safe
 372         access to name array.
 373         (get_condition_name, get_flag_name, get_double_register_name)
 374         (get_double_register_high_name, get_double_register_low_name)
 375         (get_double_control_register_name, get_double_condition_name):
 376         Likewise.
 377         (print_insn_rx): Use the accessor functions.
 378
 379 2019-10-09  Nick Clifton  <nickc@redhat.com>
 380
 381         PR 25041
 382         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 383         instructions.
 384
 385 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 386
 387         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 388         (cmpsd): Likewise. Move EsSeg to other operand.
 389         * opcodes/i386-tbl.h: Re-generate.
 390
 391 2019-09-23  Alan Modra  <amodra@gmail.com>
 392
 393         * m68k-dis.c: Include cpu-m68k.h
 394
 395 2019-09-23  Alan Modra  <amodra@gmail.com>
 396
 397         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 398         "elf/mips.h" earlier.
 399
 400 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 401
 402         PR gas/25012
 403         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 404         with SReg operand.
 405         * i386-tbl.h: Re-generate.
 406
 407 2019-09-18  Alan Modra  <amodra@gmail.com>
 408
 409         * arc-ext.c: Update throughout for bfd section macro changes.
 410
 411 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 412
 413         * Makefile.in: Re-generate.
 414         * configure: Re-generate.
 415
 416 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 417
 418         * riscv-opc.c (riscv_opcodes): Change subset field
 419         to insn_class field for all instructions.
 420         (riscv_insn_types): Likewise.
 421
 422 2019-09-16  Phil Blundell  <pb@pbcl.net>
 423
 424         * configure: Regenerated.
 425
 426 2019-09-10  Miod Vallat  <miod@online.fr>
 427
 428         PR 24982
 429         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 430
 431 2019-09-09  Phil Blundell  <pb@pbcl.net>
 432
 433         binutils 2.33 branch created.
 434
 435 2019-09-03  Nick Clifton  <nickc@redhat.com>
 436
 437         PR 24961
 438         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 439         greater than zero before indexing via (bufcnt -1).
 440
 441 2019-09-03  Nick Clifton  <nickc@redhat.com>
 442
 443         PR 24958
 444         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 445         (MAX_SPEC_REG_NAME_LEN): Define.
 446         (struct mmix_dis_info): Use defined constants for array lengths.
 447         (get_reg_name): New function.
 448         (get_sprec_reg_name): New function.
 449         (print_insn_mmix): Use new functions.
 450
 451 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 452
 453         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 454         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 455         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 456
 457 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 458
 459         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 460         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 461         (aarch64_sys_reg_supported_p): Update checks for the above.
 462
 463 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 464
 465         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 466         cases MVE_SQRSHRL and MVE_UQRSHLL.
 467         (print_insn_mve): Add case for specifier 'k' to check
 468         specific bit of the instruction.
 469
 470 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 471
 472         PR 24854
 473         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 474         encountering an unknown machine type.
 475         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 476         cases return -1 rather than calling abort.
 477
 478 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 479
 480         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 481         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 482         IgnoreSize.
 483         * i386-tbl.h: Re-generate.
 484
 485 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 486
 487         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 488         instructions.
 489
 490 2019-07-30  Mel Chen <mel.chen@sifive.com>
 491
 492         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 493         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 494
 495         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 496         fscsr.
 497
 498 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 499
 500         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 501         and MPY class instructions.
 502         (parse_option): Add nps400 option.
 503         (print_arc_disassembler_options): Add nps400 info.
 504
 505 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 506
 507         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 508         (bspop): Likewise.
 509         (modapp): Likewise.
 510         * arc-opc.c (RAD_CHK): Add.
 511         * arc-tbl.h: Regenerate.
 512
 513 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 514
 515         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 516         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 517
 518 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 519
 520         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 521         instructions as UNPREDICTABLE.
 522
 523 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 524
 525         * bpf-desc.c: Regenerated.
 526
 527 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 528
 529         * i386-gen.c (static_assert): Define.
 530         (main): Use it.
 531         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 532         (Opcode_Modifier_Num): ... this.
 533         (Mem): Delete.
 534
 535 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 536
 537         * i386-gen.c (operand_types): Move RegMem ...
 538         (opcode_modifiers): ... here.
 539         * i386-opc.h (RegMem): Move to opcode modifer enum.
 540         (union i386_operand_type): Move regmem field ...
 541         (struct i386_opcode_modifier): ... here.
 542         * i386-opc.tbl (RegMem): Define.
 543         (mov, movq): Move RegMem on segment, control, debug, and test
 544         register flavors.
 545         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 546         to non-SSE2AVX flavor.
 547         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 548         Move RegMem on register only flavors. Drop IgnoreSize from
 549         legacy encoding flavors.
 550         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 551         flavors.
 552         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 553         register only flavors.
 554         (vmovd): Move RegMem and drop IgnoreSize on register only
 555         flavor. Change opcode and operand order to store form.
 556         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 557
 558 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 559
 560         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 561         entries.
 562         * i386-opc.h (SReg2, SReg3): Replace by ...
 563         (SReg): ... this.
 564         (union i386_operand_type): Replace sreg fields.
 565         * i386-opc.tbl (mov, ): Use SReg.
 566         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 567         register flavors.
 568         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 569         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 570
 571 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 572
 573         * bpf-desc.c: Regenerate.
 574         * bpf-opc.c: Likewise.
 575         * bpf-opc.h: Likewise.
 576
 577 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 578
 579         * bpf-desc.c: Regenerate.
 580         * bpf-opc.c: Likewise.
 581
 582 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 583
 584         * arm-dis.c (print_insn_coprocessor): Rename index to
 585         index_operand.
 586
 587 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 588
 589         * riscv-opc.c (riscv_insn_types): Add r4 type.
 590
 591         * riscv-opc.c (riscv_insn_types): Add b and j type.
 592
 593         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 594         format for sb type and correct s type.
 595
 596 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 597
 598         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 599         SVE FMOV alias of FCPY.
 600
 601 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 602
 603         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 604         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 605
 606 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 607
 608         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 609         registers in an instruction prefixed by MOVPRFX.
 610
 611 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 612
 613         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 614         sve_size_13 icode to account for variant behaviour of
 615         pmull{t,b}.
 616         * aarch64-dis-2.c: Regenerate.
 617         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 618         sve_size_13 icode to account for variant behaviour of
 619         pmull{t,b}.
 620         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 621         (OP_SVE_VVV_Q_D): Add new qualifier.
 622         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 623         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 624         AES and those not.
 625
 626 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 627
 628         * opcodes/i386-gen.c (operand_type_init): Remove
 629         OPERAND_TYPE_VEC_IMM4 entry.
 630         (operand_types): Remove Vec_Imm4.
 631         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 632         (union i386_operand_type): Remove vec_imm4.
 633         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 634         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 635
 636 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 637
 638         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 639         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 640         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 641         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 642         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 643         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 644         * i386-tbl.h: Re-generate.
 645
 646 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 647
 648         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 649         register operands.
 650         * i386-tbl.h: Re-generate.
 651
 652 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 653
 654         * i386-opc.tbl (C): New.
 655         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 656         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 657         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 658         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 659         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 660         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 661         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 662         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 663         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 664         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 665         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 666         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 667         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 668         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 669         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 670         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 671         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 672         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 673         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 674         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 675         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 676         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 677         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 678         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 679         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 680         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 681         flavors.
 682         * i386-tbl.h: Re-generate.
 683
 684 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 685
 686         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 687         register operands.
 688         * i386-tbl.h: Re-generate.
 689
 690 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 691
 692         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 693         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 694         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 695         * i386-tbl.h: Re-generate.
 696
 697 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 698
 699         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 700         Disp8MemShift from register only templates.
 701         * i386-tbl.h: Re-generate.
 702
 703 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 704
 705         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 706         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 707         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 708         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 709         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 710         EVEX_W_0F11_P_3_M_1): Delete.
 711         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 712         EVEX_W_0F11_P_3): New.
 713         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 714         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 715         MOD_EVEX_0F11_PREFIX_3 table entries.
 716         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 717         PREFIX_EVEX_0F11 table entries.
 718         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 719         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 720         EVEX_W_0F11_P_3_M_{0,1} table entries.
 721
 722 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 723
 724         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 725         Delete.
 726
 727 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 728
 729         PR binutils/24719
 730         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 731         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 732         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 733         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 734         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 735         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 736         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 737         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 738         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 739         PREFIX_EVEX_0F38C6_REG_6 entries.
 740         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 741         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 742         EVEX_W_0F38C7_R_6_P_2 entries.
 743         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 744         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 745         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 746         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 747         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 748         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 749         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 750
 751 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 752
 753         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 754         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 755         VEX_LEN_0F2D_P_3): Delete.
 756         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 757         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 758         (prefix_table): ... here.
 759
 760 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 761
 762         * i386-dis.c (Iq): Delete.
 763         (Id): New.
 764         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 765         TBM insns.
 766         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 767         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 768         (OP_E_memory): Also honor needindex when deciding whether an
 769         address size prefix needs printing.
 770         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 771
 772 2019-06-26  Jim Wilson  <jimw@sifive.com>
 773
 774         PR binutils/24739
 775         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 776         Set info->display_endian to info->endian_code.
 777
 778 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 779
 780         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 781         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 782         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 783         OPERAND_TYPE_ACC64 entries.
 784         * i386-init.h: Re-generate.
 785
 786 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 787
 788         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 789         Delete.
 790         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 791         of dqa_mode.
 792         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 793         entries here.
 794         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 795         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 796
 797 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 798
 799         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 800         variables.
 801
 802 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 803
 804         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 805         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 806         movnti.
 807         * i386-opc.tbl (movnti): Add IgnoreSize.
 808         * i386-tbl.h: Re-generate.
 809
 810 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 811
 812         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 813         * i386-tbl.h: Re-generate.
 814
 815 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 816
 817         * i386-dis-evex.h: Break into ...
 818         * i386-dis-evex-len.h: New file.
 819         * i386-dis-evex-mod.h: Likewise.
 820         * i386-dis-evex-prefix.h: Likewise.
 821         * i386-dis-evex-reg.h: Likewise.
 822         * i386-dis-evex-w.h: Likewise.
 823         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 824         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 825         i386-dis-evex-mod.h.
 826
 827 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 828
 829         PR binutils/24700
 830         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 831         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 832         EVEX_W_0F385B_P_2.
 833         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 834         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 835         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 836         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 837         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 838         EVEX_LEN_0F385B_P_2_W_1.
 839         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 840         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 841         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 842         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 843         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 844         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 845         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 846         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 847         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 848         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 849
 850 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 851
 852         PR binutils/24691
 853         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 854         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 855         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 856         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 857         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 858         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 859         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 860         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 861         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 862         EVEX_LEN_0F3A43_P_2_W_1.
 863         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 864         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 865         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 866         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 867         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 868         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 869         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 870         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 871         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 872         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 873         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 874         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 875
 876 2019-06-14  Nick Clifton  <nickc@redhat.com>
 877
 878         * po/fr.po; Updated French translation.
 879
 880 2019-06-13  Stafford Horne  <shorne@gmail.com>
 881
 882         * or1k-asm.c: Regenerated.
 883         * or1k-desc.c: Regenerated.
 884         * or1k-desc.h: Regenerated.
 885         * or1k-dis.c: Regenerated.
 886         * or1k-ibld.c: Regenerated.
 887         * or1k-opc.c: Regenerated.
 888         * or1k-opc.h: Regenerated.
 889         * or1k-opinst.c: Regenerated.
 890
 891 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 892
 893         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 894
 895 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 896
 897         PR binutils/24633
 898         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 899         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 900         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 901         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 902         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 903         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 904         EVEX_LEN_0F3A1B_P_2_W_1.
 905         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 906         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 907         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 908         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 909         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 910         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 911         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 912         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 913
 914 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 915
 916         PR binutils/24626
 917         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 918         EVEX.vvvv when disassembling VEX and EVEX instructions.
 919         (OP_VEX): Set vex.register_specifier to 0 after readding
 920         vex.register_specifier.
 921         (OP_Vex_2src_1): Likewise.
 922         (OP_Vex_2src_2): Likewise.
 923         (OP_LWP_E): Likewise.
 924         (OP_EX_Vex): Don't check vex.register_specifier.
 925         (OP_XMM_Vex): Likewise.
 926
 927 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 928             Lili Cui  <lili.cui@intel.com>
 929
 930         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 931         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 932         instructions.
 933         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 934         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 935         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 936         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 937         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 938         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 939         * i386-init.h: Regenerated.
 940         * i386-tbl.h: Likewise.
 941
 942 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 943             Lili Cui  <lili.cui@intel.com>
 944
 945         * doc/c-i386.texi: Document enqcmd.
 946         * testsuite/gas/i386/enqcmd-intel.d: New file.
 947         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 948         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 949         * testsuite/gas/i386/enqcmd.d: Likewise.
 950         * testsuite/gas/i386/enqcmd.s: Likewise.
 951         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 952         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 953         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 954         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 955         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 956         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 957         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 958         and x86-64-enqcmd.
 959
 960 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 961
 962         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 963
 964 2019-06-03  Alan Modra  <amodra@gmail.com>
 965
 966         * ppc-dis.c (prefix_opcd_indices): Correct size.
 967
 968 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 969
 970         PR gas/24625
 971         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 972         Disp8ShiftVL.
 973         * i386-tbl.h: Regenerated.
 974
 975 2019-05-24  Alan Modra  <amodra@gmail.com>
 976
 977         * po/POTFILES.in: Regenerate.
 978
 979 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 980             Alan Modra  <amodra@gmail.com>
 981
 982         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 983         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 984         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 985         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 986         XTOP>): Define and add entries.
 987         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 988         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 989         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 990         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 991
 992 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 993             Alan Modra  <amodra@gmail.com>
 994
 995         * ppc-dis.c (ppc_opts): Add "future" entry.
 996         (PREFIX_OPCD_SEGS): Define.
 997         (prefix_opcd_indices): New array.
 998         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 999         (lookup_prefix): New function.
1000         (print_insn_powerpc): Handle 64-bit prefix instructions.
1001         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1002         (PMRR, POWERXX): Define.
1003         (prefix_opcodes): New instruction table.
1004         (prefix_num_opcodes): New constant.
1005
1006 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1007
1008         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1009         * configure: Regenerated.
1010         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1011         and cpu/bpf.opc.
1012         (HFILES): Add bpf-desc.h and bpf-opc.h.
1013         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1014         bpf-ibld.c and bpf-opc.c.
1015         (BPF_DEPS): Define.
1016         * Makefile.in: Regenerated.
1017         * disassemble.c (ARCH_bpf): Define.
1018         (disassembler): Add case for bfd_arch_bpf.
1019         (disassemble_init_for_target): Likewise.
1020         (enum epbf_isa_attr): Define.
1021         * disassemble.h: extern print_insn_bpf.
1022         * bpf-asm.c: Generated.
1023         * bpf-opc.h: Likewise.
1024         * bpf-opc.c: Likewise.
1025         * bpf-ibld.c: Likewise.
1026         * bpf-dis.c: Likewise.
1027         * bpf-desc.h: Likewise.
1028         * bpf-desc.c: Likewise.
1029
1030 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1031
1032         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1033         and VMSR with the new operands.
1034
1035 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1036
1037         * arm-dis.c (enum mve_instructions): New enum
1038         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1039         and cneg.
1040         (mve_opcodes): New instructions as above.
1041         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1042         csneg and csel.
1043         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1044
1045 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1046
1047         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1048         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1049         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1050         uqshl, urshrl and urshr.
1051         (is_mve_okay_in_it): Add new instructions to TRUE list.
1052         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1053         (print_insn_mve): Updated to accept new %j,
1054         %<bitfield>m and %<bitfield>n patterns.
1055
1056 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1057
1058         * mips-opc.c (mips_builtin_opcodes): Change source register
1059         constraint for DAUI.
1060
1061 2019-05-20  Nick Clifton  <nickc@redhat.com>
1062
1063         * po/fr.po: Updated French translation.
1064
1065 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1066             Michael Collison <michael.collison@arm.com>
1067
1068         * arm-dis.c (thumb32_opcodes): Add new instructions.
1069         (enum mve_instructions): Likewise.
1070         (enum mve_undefined): Add new reasons.
1071         (is_mve_encoding_conflict): Handle new instructions.
1072         (is_mve_undefined): Likewise.
1073         (is_mve_unpredictable): Likewise.
1074         (print_mve_undefined): Likewise.
1075         (print_mve_size): Likewise.
1076
1077 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1078             Michael Collison <michael.collison@arm.com>
1079
1080         * arm-dis.c (thumb32_opcodes): Add new instructions.
1081         (enum mve_instructions): Likewise.
1082         (is_mve_encoding_conflict): Handle new instructions.
1083         (is_mve_undefined): Likewise.
1084         (is_mve_unpredictable): Likewise.
1085         (print_mve_size): Likewise.
1086
1087 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1088             Michael Collison <michael.collison@arm.com>
1089
1090         * arm-dis.c (thumb32_opcodes): Add new instructions.
1091         (enum mve_instructions): Likewise.
1092         (is_mve_encoding_conflict): Likewise.
1093         (is_mve_unpredictable): Likewise.
1094         (print_mve_size): Likewise.
1095
1096 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1097             Michael Collison <michael.collison@arm.com>
1098
1099         * arm-dis.c (thumb32_opcodes): Add new instructions.
1100         (enum mve_instructions): Likewise.
1101         (is_mve_encoding_conflict): Handle new instructions.
1102         (is_mve_undefined): Likewise.
1103         (is_mve_unpredictable): Likewise.
1104         (print_mve_size): Likewise.
1105
1106 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1107             Michael Collison <michael.collison@arm.com>
1108
1109         * arm-dis.c (thumb32_opcodes): Add new instructions.
1110         (enum mve_instructions): Likewise.
1111         (is_mve_encoding_conflict): Handle new instructions.
1112         (is_mve_undefined): Likewise.
1113         (is_mve_unpredictable): Likewise.
1114         (print_mve_size): Likewise.
1115         (print_insn_mve): Likewise.
1116
1117 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1118             Michael Collison <michael.collison@arm.com>
1119
1120         * arm-dis.c (thumb32_opcodes): Add new instructions.
1121         (print_insn_thumb32): Handle new instructions.
1122
1123 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1124             Michael Collison <michael.collison@arm.com>
1125
1126         * arm-dis.c (enum mve_instructions): Add new instructions.
1127         (enum mve_undefined): Add new reasons.
1128         (is_mve_encoding_conflict): Handle new instructions.
1129         (is_mve_undefined): Likewise.
1130         (is_mve_unpredictable): Likewise.
1131         (print_mve_undefined): Likewise.
1132         (print_mve_size): Likewise.
1133         (print_mve_shift_n): Likewise.
1134         (print_insn_mve): Likewise.
1135
1136 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1137             Michael Collison <michael.collison@arm.com>
1138
1139         * arm-dis.c (enum mve_instructions): Add new instructions.
1140         (is_mve_encoding_conflict): Handle new instructions.
1141         (is_mve_unpredictable): Likewise.
1142         (print_mve_rotate): Likewise.
1143         (print_mve_size): Likewise.
1144         (print_insn_mve): Likewise.
1145
1146 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1147             Michael Collison <michael.collison@arm.com>
1148
1149         * arm-dis.c (enum mve_instructions): Add new instructions.
1150         (is_mve_encoding_conflict): Handle new instructions.
1151         (is_mve_unpredictable): Likewise.
1152         (print_mve_size): Likewise.
1153         (print_insn_mve): Likewise.
1154
1155 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1156             Michael Collison <michael.collison@arm.com>
1157
1158         * arm-dis.c (enum mve_instructions): Add new instructions.
1159         (enum mve_undefined): Add new reasons.
1160         (is_mve_encoding_conflict): Handle new instructions.
1161         (is_mve_undefined): Likewise.
1162         (is_mve_unpredictable): Likewise.
1163         (print_mve_undefined): Likewise.
1164         (print_mve_size): Likewise.
1165         (print_insn_mve): Likewise.
1166
1167 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1168             Michael Collison <michael.collison@arm.com>
1169
1170         * arm-dis.c (enum mve_instructions): Add new instructions.
1171         (is_mve_encoding_conflict): Handle new instructions.
1172         (is_mve_undefined): Likewise.
1173         (is_mve_unpredictable): Likewise.
1174         (print_mve_size): Likewise.
1175         (print_insn_mve): Likewise.
1176
1177 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1178             Michael Collison <michael.collison@arm.com>
1179
1180         * arm-dis.c (enum mve_instructions): Add new instructions.
1181         (enum mve_unpredictable): Add new reasons.
1182         (enum mve_undefined): Likewise.
1183         (is_mve_okay_in_it): Handle new isntructions.
1184         (is_mve_encoding_conflict): Likewise.
1185         (is_mve_undefined): Likewise.
1186         (is_mve_unpredictable): Likewise.
1187         (print_mve_vmov_index): Likewise.
1188         (print_simd_imm8): Likewise.
1189         (print_mve_undefined): Likewise.
1190         (print_mve_unpredictable): Likewise.
1191         (print_mve_size): Likewise.
1192         (print_insn_mve): Likewise.
1193
1194 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1195             Michael Collison <michael.collison@arm.com>
1196
1197         * arm-dis.c (enum mve_instructions): Add new instructions.
1198         (enum mve_unpredictable): Add new reasons.
1199         (enum mve_undefined): Likewise.
1200         (is_mve_encoding_conflict): Handle new instructions.
1201         (is_mve_undefined): Likewise.
1202         (is_mve_unpredictable): Likewise.
1203         (print_mve_undefined): Likewise.
1204         (print_mve_unpredictable): Likewise.
1205         (print_mve_rounding_mode): Likewise.
1206         (print_mve_vcvt_size): Likewise.
1207         (print_mve_size): Likewise.
1208         (print_insn_mve): Likewise.
1209
1210 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1211             Michael Collison <michael.collison@arm.com>
1212
1213         * arm-dis.c (enum mve_instructions): Add new instructions.
1214         (enum mve_unpredictable): Add new reasons.
1215         (enum mve_undefined): Likewise.
1216         (is_mve_undefined): Handle new instructions.
1217         (is_mve_unpredictable): Likewise.
1218         (print_mve_undefined): Likewise.
1219         (print_mve_unpredictable): Likewise.
1220         (print_mve_size): Likewise.
1221         (print_insn_mve): Likewise.
1222
1223 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1224             Michael Collison <michael.collison@arm.com>
1225
1226         * arm-dis.c (enum mve_instructions): Add new instructions.
1227         (enum mve_undefined): Add new reasons.
1228         (insns): Add new instructions.
1229         (is_mve_encoding_conflict):
1230         (print_mve_vld_str_addr): New print function.
1231         (is_mve_undefined): Handle new instructions.
1232         (is_mve_unpredictable): Likewise.
1233         (print_mve_undefined): Likewise.
1234         (print_mve_size): Likewise.
1235         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1236         (print_insn_mve):  Handle new operands.
1237
1238 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1239             Michael Collison <michael.collison@arm.com>
1240
1241         * arm-dis.c (enum mve_instructions): Add new instructions.
1242         (enum mve_unpredictable): Add new reasons.
1243         (is_mve_encoding_conflict): Handle new instructions.
1244         (is_mve_unpredictable): Likewise.
1245         (mve_opcodes): Add new instructions.
1246         (print_mve_unpredictable): Handle new reasons.
1247         (print_mve_register_blocks): New print function.
1248         (print_mve_size): Handle new instructions.
1249         (print_insn_mve): Likewise.
1250
1251 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1252             Michael Collison <michael.collison@arm.com>
1253
1254         * arm-dis.c (enum mve_instructions): Add new instructions.
1255         (enum mve_unpredictable): Add new reasons.
1256         (enum mve_undefined): Likewise.
1257         (is_mve_encoding_conflict): Handle new instructions.
1258         (is_mve_undefined): Likewise.
1259         (is_mve_unpredictable): Likewise.
1260         (coprocessor_opcodes): Move NEON VDUP from here...
1261         (neon_opcodes): ... to here.
1262         (mve_opcodes): Add new instructions.
1263         (print_mve_undefined):  Handle new reasons.
1264         (print_mve_unpredictable): Likewise.
1265         (print_mve_size): Handle new instructions.
1266         (print_insn_neon): Handle vdup.
1267         (print_insn_mve): Handle new operands.
1268
1269 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1270             Michael Collison <michael.collison@arm.com>
1271
1272         * arm-dis.c (enum mve_instructions): Add new instructions.
1273         (enum mve_unpredictable): Add new values.
1274         (mve_opcodes): Add new instructions.
1275         (vec_condnames): New array with vector conditions.
1276         (mve_predicatenames): New array with predicate suffixes.
1277         (mve_vec_sizename): New array with vector sizes.
1278         (enum vpt_pred_state): New enum with vector predication states.
1279         (struct vpt_block): New struct type for vpt blocks.
1280         (vpt_block_state): Global struct to keep track of state.
1281         (mve_extract_pred_mask): New helper function.
1282         (num_instructions_vpt_block): Likewise.
1283         (mark_outside_vpt_block): Likewise.
1284         (mark_inside_vpt_block): Likewise.
1285         (invert_next_predicate_state): Likewise.
1286         (update_next_predicate_state): Likewise.
1287         (update_vpt_block_state): Likewise.
1288         (is_vpt_instruction): Likewise.
1289         (is_mve_encoding_conflict): Add entries for new instructions.
1290         (is_mve_unpredictable): Likewise.
1291         (print_mve_unpredictable): Handle new cases.
1292         (print_instruction_predicate): Likewise.
1293         (print_mve_size): New function.
1294         (print_vec_condition): New function.
1295         (print_insn_mve): Handle vpt blocks and new print operands.
1296
1297 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1298
1299         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1300         8, 14 and 15 for Armv8.1-M Mainline.
1301
1302 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1303             Michael Collison <michael.collison@arm.com>
1304
1305         * arm-dis.c (enum mve_instructions): New enum.
1306         (enum mve_unpredictable): Likewise.
1307         (enum mve_undefined): Likewise.
1308         (struct mopcode32): New struct.
1309         (is_mve_okay_in_it): New function.
1310         (is_mve_architecture): Likewise.
1311         (arm_decode_field): Likewise.
1312         (arm_decode_field_multiple): Likewise.
1313         (is_mve_encoding_conflict): Likewise.
1314         (is_mve_undefined): Likewise.
1315         (is_mve_unpredictable): Likewise.
1316         (print_mve_undefined): Likewise.
1317         (print_mve_unpredictable): Likewise.
1318         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1319         (print_insn_mve): New function.
1320         (print_insn_thumb32): Handle MVE architecture.
1321         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1322
1323 2019-05-10  Nick Clifton  <nickc@redhat.com>
1324
1325         PR 24538
1326         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1327         end of the table prematurely.
1328
1329 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1330
1331         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1332         macros for R6.
1333
1334 2019-05-11  Alan Modra  <amodra@gmail.com>
1335
1336         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1337         when -Mraw is in effect.
1338
1339 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1340
1341         * aarch64-dis-2.c: Regenerate.
1342         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1343         (OP_SVE_BBB): New variant set.
1344         (OP_SVE_DDDD): New variant set.
1345         (OP_SVE_HHH): New variant set.
1346         (OP_SVE_HHHU): New variant set.
1347         (OP_SVE_SSS): New variant set.
1348         (OP_SVE_SSSU): New variant set.
1349         (OP_SVE_SHH): New variant set.
1350         (OP_SVE_SBBU): New variant set.
1351         (OP_SVE_DSS): New variant set.
1352         (OP_SVE_DHHU): New variant set.
1353         (OP_SVE_VMV_HSD_BHS): New variant set.
1354         (OP_SVE_VVU_HSD_BHS): New variant set.
1355         (OP_SVE_VVVU_SD_BH): New variant set.
1356         (OP_SVE_VVVU_BHSD): New variant set.
1357         (OP_SVE_VVV_QHD_DBS): New variant set.
1358         (OP_SVE_VVV_HSD_BHS): New variant set.
1359         (OP_SVE_VVV_HSD_BHS2): New variant set.
1360         (OP_SVE_VVV_BHS_HSD): New variant set.
1361         (OP_SVE_VV_BHS_HSD): New variant set.
1362         (OP_SVE_VVV_SD): New variant set.
1363         (OP_SVE_VVU_BHS_HSD): New variant set.
1364         (OP_SVE_VZVV_SD): New variant set.
1365         (OP_SVE_VZVV_BH): New variant set.
1366         (OP_SVE_VZV_SD): New variant set.
1367         (aarch64_opcode_table): Add sve2 instructions.
1368
1369 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1370
1371         * aarch64-asm-2.c: Regenerated.
1372         * aarch64-dis-2.c: Regenerated.
1373         * aarch64-opc-2.c: Regenerated.
1374         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1375         for SVE_SHLIMM_UNPRED_22.
1376         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1377         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1378         operand.
1379
1380 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1381
1382         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1383         sve_size_tsz_bhs iclass encode.
1384         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1385         sve_size_tsz_bhs iclass decode.
1386
1387 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1388
1389         * aarch64-asm-2.c: Regenerated.
1390         * aarch64-dis-2.c: Regenerated.
1391         * aarch64-opc-2.c: Regenerated.
1392         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1393         for SVE_Zm4_11_INDEX.
1394         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1395         (fields): Handle SVE_i2h field.
1396         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1397         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1398
1399 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1400
1401         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1402         sve_shift_tsz_bhsd iclass encode.
1403         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1404         sve_shift_tsz_bhsd iclass decode.
1405
1406 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1407
1408         * aarch64-asm-2.c: Regenerated.
1409         * aarch64-dis-2.c: Regenerated.
1410         * aarch64-opc-2.c: Regenerated.
1411         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1412         (aarch64_encode_variant_using_iclass): Handle
1413         sve_shift_tsz_hsd iclass encode.
1414         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1415         sve_shift_tsz_hsd iclass decode.
1416         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1417         for SVE_SHRIMM_UNPRED_22.
1418         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1419         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1420         operand.
1421
1422 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1423
1424         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1425         sve_size_013 iclass encode.
1426         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1427         sve_size_013 iclass decode.
1428
1429 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1430
1431         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1432         sve_size_bh iclass encode.
1433         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1434         sve_size_bh iclass decode.
1435
1436 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1437
1438         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1439         sve_size_sd2 iclass encode.
1440         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1441         sve_size_sd2 iclass decode.
1442         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1443         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1444
1445 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1446
1447         * aarch64-asm-2.c: Regenerated.
1448         * aarch64-dis-2.c: Regenerated.
1449         * aarch64-opc-2.c: Regenerated.
1450         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1451         for SVE_ADDR_ZX.
1452         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1453         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1454
1455 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1456
1457         * aarch64-asm-2.c: Regenerated.
1458         * aarch64-dis-2.c: Regenerated.
1459         * aarch64-opc-2.c: Regenerated.
1460         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1461         for SVE_Zm3_11_INDEX.
1462         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1463         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1464         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1465         fields.
1466         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1467
1468 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1469
1470         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1471         sve_size_hsd2 iclass encode.
1472         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1473         sve_size_hsd2 iclass decode.
1474         * aarch64-opc.c (fields): Handle SVE_size field.
1475         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1476
1477 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1478
1479         * aarch64-asm-2.c: Regenerated.
1480         * aarch64-dis-2.c: Regenerated.
1481         * aarch64-opc-2.c: Regenerated.
1482         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1483         for SVE_IMM_ROT3.
1484         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1485         (fields): Handle SVE_rot3 field.
1486         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1487         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1488
1489 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1490
1491         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1492         instructions.
1493
1494 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1495
1496         * aarch64-tbl.h
1497         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1498         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1499         aarch64_feature_sve2bitperm): New feature sets.
1500         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1501         for feature set addresses.
1502         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1503         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1504
1505 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1506             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1507
1508         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1509         argument and set ASE_EVA_R6 appropriately.
1510         (set_default_mips_dis_options): Pass ISA to above.
1511         (parse_mips_dis_option): Likewise.
1512         * mips-opc.c (EVAR6): New macro.
1513         (mips_builtin_opcodes): Add llwpe, scwpe.
1514
1515 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1516
1517         * aarch64-asm-2.c: Regenerated.
1518         * aarch64-dis-2.c: Regenerated.
1519         * aarch64-opc-2.c: Regenerated.
1520         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1521         AARCH64_OPND_TME_UIMM16.
1522         (aarch64_print_operand): Likewise.
1523         * aarch64-tbl.h (QL_IMM_NIL): New.
1524         (TME): New.
1525         (_TME_INSN): New.
1526         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1527
1528 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1529
1530         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1531
1532 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1533             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1534
1535         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1536
1537 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1538
1539         * s12z-opc.h: Add extern "C" bracketing to help
1540         users who wish to use this interface in c++ code.
1541
1542 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1543
1544         * s12z-opc.c (bm_decode): Handle bit map operations with the
1545         "reserved0" mode.
1546
1547 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1548
1549         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1550         specifier.  Add entries for VLDR and VSTR of system registers.
1551         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1552         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1553         of %J and %K format specifier.
1554
1555 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1556
1557         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1558         Add new entries for VSCCLRM instruction.
1559         (print_insn_coprocessor): Handle new %C format control code.
1560
1561 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1562
1563         * arm-dis.c (enum isa): New enum.
1564         (struct sopcode32): New structure.
1565         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1566         set isa field of all current entries to ANY.
1567         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1568         Only match an entry if its isa field allows the current mode.
1569
1570 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1571
1572         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1573         CLRM.
1574         (print_insn_thumb32): Add logic to print %n CLRM register list.
1575
1576 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1577
1578         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1579         and %Q patterns.
1580
1581 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1582
1583         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1584         (print_insn_thumb32): Edit the switch case for %Z.
1585
1586 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1587
1588         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1589
1590 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1591
1592         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1593
1594 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1595
1596         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1597
1598 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1599
1600         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1601         Arm register with r13 and r15 unpredictable.
1602         (thumb32_opcodes): New instructions for bfx and bflx.
1603
1604 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1605
1606         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1607
1608 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1609
1610         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1611
1612 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1613
1614         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1615
1616 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1617
1618         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1619
1620 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1621
1622         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1623         "optr". ("operator" is a reserved word in c++).
1624
1625 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1626
1627         * aarch64-opc.c (aarch64_print_operand): Add case for
1628         AARCH64_OPND_Rt_SP.
1629         (verify_constraints): Likewise.
1630         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1631         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1632         to accept Rt|SP as first operand.
1633         (AARCH64_OPERANDS): Add new Rt_SP.
1634         * aarch64-asm-2.c: Regenerated.
1635         * aarch64-dis-2.c: Regenerated.
1636         * aarch64-opc-2.c: Regenerated.
1637
1638 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1639
1640         * aarch64-asm-2.c: Regenerated.
1641         * aarch64-dis-2.c: Likewise.
1642         * aarch64-opc-2.c: Likewise.
1643         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1644
1645 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1646
1647         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1648
1649 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1650
1651         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1652         * i386-init.h: Regenerated.
1653
1654 2019-04-07  Alan Modra  <amodra@gmail.com>
1655
1656         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1657         op_separator to control printing of spaces, comma and parens
1658         rather than need_comma, need_paren and spaces vars.
1659
1660 2019-04-07  Alan Modra  <amodra@gmail.com>
1661
1662         PR 24421
1663         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1664         (print_insn_neon, print_insn_arm): Likewise.
1665
1666 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1667
1668         * i386-dis-evex.h (evex_table): Updated to support BF16
1669         instructions.
1670         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1671         and EVEX_W_0F3872_P_3.
1672         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1673         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1674         * i386-opc.h (enum): Add CpuAVX512_BF16.
1675         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1676         * i386-opc.tbl: Add AVX512 BF16 instructions.
1677         * i386-init.h: Regenerated.
1678         * i386-tbl.h: Likewise.
1679
1680 2019-04-05  Alan Modra  <amodra@gmail.com>
1681
1682         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1683         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1684         to favour printing of "-" branch hint when using the "y" bit.
1685         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1686
1687 2019-04-05  Alan Modra  <amodra@gmail.com>
1688
1689         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1690         opcode until first operand is output.
1691
1692 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1693
1694         PR gas/24349
1695         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1696         (valid_bo_post_v2): Add support for 'at' branch hints.
1697         (insert_bo): Only error on branch on ctr.
1698         (get_bo_hint_mask): New function.
1699         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1700         for inserting 'at' branch hints.
1701         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1702         for extracting 'at' branch hints.
1703         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1704         (BOE): Delete operand.
1705         (BOM, BOP): New operands.
1706         (RM): Update value.
1707         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1708         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1709         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1710         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1711         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1712         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1713         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1714         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1715         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1716         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1717         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1718         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1719         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1720         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1721         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1722         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1723         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1724         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1725         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1726         bttarl+>: New extended mnemonics.
1727
1728 2019-03-28  Alan Modra  <amodra@gmail.com>
1729
1730         PR 24390
1731         * ppc-opc.c (BTF): Define.
1732         (powerpc_opcodes): Use for mtfsb*.
1733         * ppc-dis.c (print_insn_powerpc): Print fields with both
1734         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1735
1736 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1737
1738         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1739         (mapping_symbol_for_insn): Implement new algorithm.
1740         (print_insn): Remove duplicate code.
1741
1742 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1743
1744         * aarch64-dis.c (print_insn_aarch64):
1745         Implement override.
1746
1747 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1748
1749         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1750         order.
1751
1752 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1753
1754         * aarch64-dis.c (last_stop_offset): New.
1755         (print_insn_aarch64): Use stop_offset.
1756
1757 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1758
1759         PR gas/24359
1760         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1761         CPU_ANY_AVX2_FLAGS.
1762         * i386-init.h: Regenerated.
1763
1764 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1765
1766         PR gas/24348
1767         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1768         vmovdqu16, vmovdqu32 and vmovdqu64.
1769         * i386-tbl.h: Regenerated.
1770
1771 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1772
1773         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1774         from vstrszb, vstrszh, and vstrszf.
1775
1776 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1777
1778         * s390-opc.txt: Add instruction descriptions.
1779
1780 2019-02-08  Jim Wilson  <jimw@sifive.com>
1781
1782         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1783         <bne>: Likewise.
1784
1785 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1786
1787         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1788
1789 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1790
1791         PR binutils/23212
1792         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1793         * aarch64-opc.c (verify_elem_sd): New.
1794         (fields): Add FLD_sz entr.
1795         * aarch64-tbl.h (_SIMD_INSN): New.
1796         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1797         fmulx scalar and vector by element isns.
1798
1799 2019-02-07  Nick Clifton  <nickc@redhat.com>
1800
1801         * po/sv.po: Updated Swedish translation.
1802
1803 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1804
1805         * s390-mkopc.c (main): Accept arch13 as cpu string.
1806         * s390-opc.c: Add new instruction formats and instruction opcode
1807         masks.
1808         * s390-opc.txt: Add new arch13 instructions.
1809
1810 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1811
1812         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1813         (aarch64_opcode): Change encoding for stg, stzg
1814         st2g and st2zg.
1815         * aarch64-asm-2.c: Regenerated.
1816         * aarch64-dis-2.c: Regenerated.
1817         * aarch64-opc-2.c: Regenerated.
1818
1819 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1820
1821         * aarch64-asm-2.c: Regenerated.
1822         * aarch64-dis-2.c: Likewise.
1823         * aarch64-opc-2.c: Likewise.
1824         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1825
1826 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1827             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1828
1829         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1830         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1831         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1832         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1833         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1834         case for ldstgv_indexed.
1835         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1836         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1837         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1838         * aarch64-asm-2.c: Regenerated.
1839         * aarch64-dis-2.c: Regenerated.
1840         * aarch64-opc-2.c: Regenerated.
1841
1842 2019-01-23  Nick Clifton  <nickc@redhat.com>
1843
1844         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1845
1846 2019-01-21  Nick Clifton  <nickc@redhat.com>
1847
1848         * po/de.po: Updated German translation.
1849         * po/uk.po: Updated Ukranian translation.
1850
1851 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1852         * mips-dis.c (mips_arch_choices): Fix typo in
1853         gs464, gs464e and gs264e descriptors.
1854
1855 2019-01-19  Nick Clifton  <nickc@redhat.com>
1856
1857         * configure: Regenerate.
1858         * po/opcodes.pot: Regenerate.
1859
1860 2018-06-24  Nick Clifton  <nickc@redhat.com>
1861
1862         2.32 branch created.
1863
1864 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1865
1866         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1867         if it is null.
1868         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1869         zero.
1870
1871 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1872
1873         * configure: Regenerate.
1874
1875 2019-01-07  Alan Modra  <amodra@gmail.com>
1876
1877         * configure: Regenerate.
1878         * po/POTFILES.in: Regenerate.
1879
1880 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1881
1882         * s12z-opc.c: New file.
1883         * s12z-opc.h: New file.
1884         * s12z-dis.c: Removed all code not directly related to display
1885         of instructions.  Used the interface provided by the new files
1886         instead.
1887         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1888         * Makefile.in: Regenerate.
1889         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1890         * configure: Regenerate.
1891
1892 2019-01-01  Alan Modra  <amodra@gmail.com>
1893
1894         Update year range in copyright notice of all files.
1895
1896 For older changes see ChangeLog-2018
1897 \f
1898 Copyright (C) 2019 Free Software Foundation, Inc.
1899
1900 Copying and distribution of this file, with or without modification,
1901 are permitted in any medium without royalty provided the copyright
1902 notice and this notice are preserved.
1903
1904 Local Variables:
1905 mode: change-log
1906 left-margin: 8
1907 fill-column: 74
1908 version-control: never
1909 End: