1 2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
4 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
5 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
6 * i386-opc.tbl: Likewise.
8 * i386-opc.h (CpuCLMUL): Renamed to ...
11 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
13 * i386-init.h: Regenerated.
15 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
17 * i386-dis.c (OP_E_register): New.
18 (OP_E_memory): Likewise.
20 (OP_EX_Vex): Likewise.
21 (OP_EX_VexW): Likewise.
22 (OP_XMM_Vex): Likewise.
23 (OP_XMM_VexW): Likewise.
24 (OP_REG_VexI4): Likewise.
25 (PCLMUL_Fixup): Likewise.
26 (VEXI4_Fixup): Likewise.
27 (VZERO_Fixup): Likewise.
28 (VCMP_Fixup): Likewise.
29 (VPERMIL2_Fixup): Likewise.
30 (rex_original): Likewise.
31 (rex_ignored): Likewise.
54 (xmmq_mode): Likewise.
55 (ymmq_mode): Likewise.
57 (vex128_mode): Likewise.
58 (vex256_mode): Likewise.
59 (USE_VEX_C4_TABLE): Likewise.
60 (USE_VEX_C5_TABLE): Likewise.
61 (USE_VEX_LEN_TABLE): Likewise.
62 (VEX_C4_TABLE): Likewise.
63 (VEX_C5_TABLE): Likewise.
64 (VEX_LEN_TABLE): Likewise.
65 (REG_VEX_XX): Likewise.
66 (MOD_VEX_XXX): Likewise.
67 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
68 (PREFIX_0F3A44): Likewise.
69 (PREFIX_0F3ADF): Likewise.
70 (PREFIX_VEX_XXX): Likewise.
74 (VEX_LEN_XXX): Likewise.
77 (need_vex_reg): Likewise.
78 (vex_i4_done): Likewise.
79 (vex_table): Likewise.
80 (vex_len_table): Likewise.
81 (OP_REG_VexI4): Likewise.
82 (vex_cmp_op): Likewise.
83 (pclmul_op): Likewise.
84 (vpermil2_op): Likewise.
87 (PREFIX_0F38F0): Likewise.
88 (PREFIX_0F3A60): Likewise.
89 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
90 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
91 and PREFIX_VEX_XXX entries.
92 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
93 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
95 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
96 Add MOD_VEX_XXX entries.
97 (ckprefix): Initialize rex_original and rex_ignored. Store the
98 REX byte in rex_original.
99 (get_valid_dis386): Handle the implicit prefix in VEX prefix
100 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
101 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
102 calling get_valid_dis386. Use rex_original and rex_ignored when
104 (putop): Handle "XY".
105 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
107 (OP_E_extended): Updated to use OP_E_register and
109 (OP_XMM): Handle VEX.
111 (XMM_Fixup): Likewise.
112 (CMP_Fixup): Use ARRAY_SIZE.
114 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
115 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
116 (operand_type_init): Add OPERAND_TYPE_REGYMM and
117 OPERAND_TYPE_VEX_IMM4.
118 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
119 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
120 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
121 VexImmExt and SSE2AVX.
122 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
124 * i386-opc.h (CpuAVX): New.
126 (CpuCLMUL): Likewise.
137 (Vex3Sources): Likewise.
138 (VexImmExt): Likewise.
142 (Vex_Imm4): Likewise.
143 (Implicit1stXmm0): Likewise.
146 (ByteOkIntel): Likewise.
149 (Unspecified): Likewise.
151 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
152 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
153 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
154 vex3sources, veximmext and sse2avx.
155 (i386_operand_type): Add regymm, ymmword and vex_imm4.
157 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
159 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
161 * i386-init.h: Regenerated.
162 * i386-tbl.h: Likewise.
164 2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
166 From Robin Getz <robin.getz@analog.com>
167 * bfin-dis.c (bu32): Typedef.
168 (enum const_forms_t): Add c_uimm32 and c_huimm32.
169 (constant_formats[]): Add uimm32 and huimm16.
174 (luimm16_val): Define.
175 (struct saved_state): Define.
176 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
177 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
178 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
180 (decode_LDIMMhalf_0): Print out the whole register value.
182 From Jie Zhang <jie.zhang@analog.com>
183 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
184 multiply and multiply-accumulate to data register instruction.
186 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
187 c_imm32, c_huimm32e): Define.
188 (constant_formats): Add flags for printing decimal, leading spaces, and
190 (comment, parallel): Add global flags in all disassembly.
191 (fmtconst): Take advantage of new flags, and print default in hex.
192 (fmtconst_val): Likewise.
193 (decode_macfunc): Be consistant with spaces, tabs, comments,
194 capitalization in disassembly, fix minor coding style issues.
195 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
196 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
197 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
198 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
199 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
200 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
201 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
202 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
203 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
204 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
205 _print_insn_bfin, print_insn_bfin): Likewise.
207 2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
209 * aclocal.m4: Regenerate.
210 * configure: Likewise.
211 * Makefile.in: Likewise.
213 2008-03-13 Alan Modra <amodra@bigpond.net.au>
215 * Makefile.am: Run "make dep-am".
216 * Makefile.in: Regenerate.
217 * configure: Regenerate.
219 2008-03-07 Alan Modra <amodra@bigpond.net.au>
221 * ppc-opc.c (powerpc_opcodes): Order and format.
223 2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
225 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
226 * i386-tbl.h: Regenerated.
228 2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
230 * i386-opc.tbl: Disallow 16-bit near indirect branches for
232 * i386-tbl.h: Regenerated.
234 2008-02-21 Jan Beulich <jbeulich@novell.com>
236 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
237 and Fword for far indirect jmp. Allow Reg16 and Word for near
238 indirect jmp on x86-64. Disallow Fword for lcall.
239 * i386-tbl.h: Re-generate.
241 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
243 * cr16-opc.c (cr16_num_optab): Defined
245 2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
247 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
248 * i386-init.h: Regenerated.
250 2008-02-14 Nick Clifton <nickc@redhat.com>
253 * configure.in (SHARED_LIBADD): Select the correct host specific
254 file extension for shared libraries.
255 * configure: Regenerate.
257 2008-02-13 Jan Beulich <jbeulich@novell.com>
259 * i386-opc.h (RegFlat): New.
260 * i386-reg.tbl (flat): Add.
261 * i386-tbl.h: Re-generate.
263 2008-02-13 Jan Beulich <jbeulich@novell.com>
265 * i386-dis.c (a_mode): New.
266 (cond_jump_mode): Adjust.
267 (Ma): Change to a_mode.
268 (intel_operand_size): Handle a_mode.
269 * i386-opc.tbl: Allow Dword and Qword for bound.
270 * i386-tbl.h: Re-generate.
272 2008-02-13 Jan Beulich <jbeulich@novell.com>
274 * i386-gen.c (process_i386_registers): Process new fields.
275 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
276 unsigned char. Add dw2_regnum and Dw2Inval.
277 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
279 * i386-tbl.h: Re-generate.
281 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
283 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
284 * i386-init.h: Updated.
286 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
288 * i386-gen.c (cpu_flags): Add CpuXsave.
290 * i386-opc.h (CpuXsave): New.
292 (i386_cpu_flags): Add cpuxsave.
294 * i386-dis.c (MOD_0FAE_REG_4): New.
295 (RM_0F01_REG_2): Likewise.
296 (MOD_0FAE_REG_5): Updated.
297 (RM_0F01_REG_3): Likewise.
298 (reg_table): Use MOD_0FAE_REG_4.
299 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
301 (rm_table): Add RM_0F01_REG_2.
303 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
304 * i386-init.h: Regenerated.
305 * i386-tbl.h: Likewise.
307 2008-02-11 Jan Beulich <jbeulich@novell.com>
309 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
310 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
311 * i386-tbl.h: Re-generate.
313 2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
316 * configure: Regenerated.
318 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
320 * mips-dis.c: Update copyright.
321 (mips_arch_choices): Add Octeon.
322 * mips-opc.c: Update copyright.
324 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
326 2008-01-29 Alan Modra <amodra@bigpond.net.au>
328 * ppc-opc.c: Support optional L form mtmsr.
330 2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
332 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
334 2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
336 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
337 * i386-init.h: Regenerated.
339 2008-01-23 Tristan Gingold <gingold@adacore.com>
341 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
342 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
344 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
346 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
347 (cpu_flags): Likewise.
349 * i386-opc.h (CpuMMX2): Removed.
352 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
353 * i386-init.h: Regenerated.
354 * i386-tbl.h: Likewise.
356 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
358 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
360 * i386-init.h: Regenerated.
362 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
364 * i386-opc.tbl: Use Qword on movddup.
365 * i386-tbl.h: Regenerated.
367 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
369 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
370 * i386-tbl.h: Regenerated.
372 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
374 * i386-dis.c (Mx): New.
375 (PREFIX_0FC3): Likewise.
376 (PREFIX_0FC7_REG_6): Updated.
377 (dis386_twobyte): Use PREFIX_0FC3.
378 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
379 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
382 2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
384 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
385 (operand_types): Add Mem.
387 * i386-opc.h (IntelSyntax): New.
388 * i386-opc.h (Mem): New.
390 (Opcode_Modifier_Max): Updated.
391 (i386_opcode_modifier): Add intelsyntax.
392 (i386_operand_type): Add mem.
394 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
397 * i386-reg.tbl: Add size for accumulator.
399 * i386-init.h: Regenerated.
400 * i386-tbl.h: Likewise.
402 2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
404 * i386-opc.h (Byte): Fix a typo.
406 2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
409 * i386-gen.c (operand_type_init): Add Dword to
410 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
411 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
413 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
414 Xmmword, Unspecified and Anysize.
415 (set_bitfield): Make Mmword an alias of Qword. Make Oword
418 * i386-opc.h (CheckSize): Removed.
426 (i386_opcode_modifier): Remove checksize, byte, word, dword,
430 (Unspecified): Likewise.
432 (i386_operand_type): Add byte, word, dword, fword, qword,
433 tbyte xmmword, unspecified and anysize.
435 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
436 Tbyte, Xmmword, Unspecified and Anysize.
438 * i386-reg.tbl: Add size for accumulator.
440 * i386-init.h: Regenerated.
441 * i386-tbl.h: Likewise.
443 2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
445 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
447 (reg_table): Updated.
448 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
449 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
451 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
453 * i386-gen.c (set_bitfield): Use fail () on error.
455 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
457 * i386-gen.c (lineno): New.
458 (filename): Likewise.
459 (set_bitfield): Report filename and line numer on error.
460 (process_i386_opcodes): Set filename and update lineno.
461 (process_i386_registers): Likewise.
463 2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
465 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
468 * i386-opc.h (IntelMnemonic): Renamed to ..
470 (Opcode_Modifier_Max): Updated.
471 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
474 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
475 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
476 * i386-tbl.h: Regenerated.
478 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
480 * i386-gen.c: Update copyright to 2008.
481 * i386-opc.h: Likewise.
482 * i386-opc.tbl: Likewise.
484 * i386-init.h: Regenerated.
485 * i386-tbl.h: Likewise.
487 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
489 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
490 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
491 * i386-tbl.h: Regenerated.
493 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
495 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
497 (cpu_flags): Likewise.
499 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
500 (CpuSSE4_2_Or_ABM): Likewise.
502 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
504 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
505 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
506 and CpuPadLock, respectively.
507 * i386-init.h: Regenerated.
508 * i386-tbl.h: Likewise.
510 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
512 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
514 * i386-opc.h (No_xSuf): Removed.
515 (CheckSize): Updated.
517 * i386-tbl.h: Regenerated.
519 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
521 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
522 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
524 (cpu_flags): Add CpuSSE4_2_Or_ABM.
526 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
528 (i386_cpu_flags): Add cpusse4_2_or_abm.
530 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
531 CpuABM|CpuSSE4_2 on popcnt.
532 * i386-init.h: Regenerated.
533 * i386-tbl.h: Likewise.
535 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
537 * i386-opc.h: Update comments.
539 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
541 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
542 * i386-opc.h: Likewise.
543 * i386-opc.tbl: Likewise.
545 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
548 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
549 Byte, Word, Dword, QWord and Xmmword.
551 * i386-opc.h (No_xSuf): New.
552 (CheckSize): Likewise.
559 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
560 Dword, QWord and Xmmword.
562 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
564 * i386-tbl.h: Regenerated.
566 2008-01-02 Mark Kettenis <kettenis@gnu.org>
568 * m88k-dis.c (instructions): Fix fcvt.* instructions.
571 For older changes see ChangeLog-2007
577 version-control: never