opcodes/ChangeLog

   1 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
   2
   3         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
   4         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
   5         * aarch64-asm.c (convert_xtl_to_shll): New function.
   6         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
   7         calling convert_xtl_to_shll.
   8         * aarch64-dis.c (convert_shll_to_xtl): New function.
   9         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
  10         calling convert_shll_to_xtl.
  11         * aarch64-gen.c: Update copyright year.
  12         * aarch64-asm-2.c: Re-generate.
  13         * aarch64-dis-2.c: Re-generate.
  14         * aarch64-opc-2.c: Re-generate.
  15
  16 2013-01-24  Nick Clifton  <nickc@redhat.com>
  17
  18         * v850-dis.c: Add support for e3v5 architecture.
  19         * v850-opc.c: Likewise.
  20
  21 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
  22
  23         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
  24         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
  25         * aarch64-opc.c (operand_general_constraint_met_p): For
  26         AARCH64_MOD_LSL, move the range check on the shift amount before the
  27         alignment check; change to call set_sft_amount_out_of_range_error
  28         instead of set_imm_out_of_range_error.
  29         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
  30         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
  31         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
  32         SIMD_IMM_SFT.
  33
  34 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
  35
  36         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
  37
  38         * i386-init.h: Regenerated.
  39         * i386-tbl.h: Likewise.
  40
  41 2013-01-15  Nick Clifton  <nickc@redhat.com>
  42
  43         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
  44         values.
  45         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
  46
  47 2013-01-14  Will Newton <will.newton@imgtec.com>
  48
  49         * metag-dis.c (REG_WIDTH): Increase to 64.
  50
  51 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
  52
  53         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
  54         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
  55         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
  56         (SH6): Update.
  57         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
  58         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
  59         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
  60         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
  61
  62 2013-01-10  Will Newton <will.newton@imgtec.com>
  63
  64         * Makefile.am: Add Meta.
  65         * configure.in: Add Meta.
  66         * disassemble.c: Add Meta support.
  67         * metag-dis.c: New file.
  68         * Makefile.in: Regenerate.
  69         * configure: Regenerate.
  70
  71 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
  72
  73         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
  74         (match_opcode): Rename to cr16_match_opcode.
  75
  76 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
  77
  78         * mips-dis.c: Add names for CP0 registers of r5900.
  79         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
  80         instructions sq and lq.
  81         Add support for MIPS r5900 CPU.
  82         Add support for 128 bit MMI (Multimedia Instructions).
  83         Add support for EE instructions (Emotion Engine).
  84         Disable unsupported floating point instructions (64 bit and
  85         undefined compare operations).
  86         Enable instructions of MIPS ISA IV which are supported by r5900.
  87         Disable 64 bit co processor instructions.
  88         Disable 64 bit multiplication and division instructions.
  89         Disable instructions for co-processor 2 and 3, because these are
  90         not supported (preparation for later VU0 support (Vector Unit)).
  91         Disable cvt.w.s because this behaves like trunc.w.s and the
  92         correct execution can't be ensured on r5900.
  93         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
  94         will confuse less developers and compilers.
  95
  96 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
  97
  98         * aarch64-opc.c (aarch64_print_operand): Change to print
  99         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 100         in comment.
 101         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 102         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 103         OP_MOV_IMM_WIDE.
 104
 105 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 106
 107         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 108         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 109
 110 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 111
 112         * i386-gen.c (process_copyright): Update copyright year to 2013.
 113
 114 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 115
 116         * cr16-dis.c (match_opcode,make_instruction): Remove static
 117         declaration.
 118         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 119         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 120
 121 For older changes see ChangeLog-2012
 122 \f
 123 Copyright (C) 2013 Free Software Foundation, Inc.
 124
 125 Copying and distribution of this file, with or without modification,
 126 are permitted in any medium without royalty provided the copyright
 127 notice and this notice are preserved.
 128
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 130 mode: change-log
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 134 End: