opcodes/ChangeLog

   1 2017-07-05  Borislav Petkov  <bp@suse.de>
   2
   3         * i386-dis.c: Enable ModRM.reg /6 aliases.
   4
   5 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
   6
   7         * opcodes/arm-dis.c: Support MVFR2 in disassembly
   8         with vmrs and vmsr.
   9
  10 2017-07-04  Tristan Gingold  <gingold@adacore.com>
  11
  12         * configure: Regenerate.
  13
  14 2017-07-03  Tristan Gingold  <gingold@adacore.com>
  15
  16         * po/opcodes.pot: Regenerate.
  17
  18 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
  19
  20         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
  21         entries to the MSA ASE instruction block.
  22
  23 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
  24             Maciej W. Rozycki  <macro@imgtec.com>
  25
  26         * micromips-opc.c (XPA, XPAVZ): New macros.
  27         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
  28         "mthgc0".
  29
  30 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
  31             Maciej W. Rozycki  <macro@imgtec.com>
  32
  33         * micromips-opc.c (I36): New macro.
  34         (micromips_opcodes): Add "eretnc".
  35
  36 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
  37             Andrew Bennett  <andrew.bennett@imgtec.com>
  38
  39         * mips-dis.c (mips_calculate_combination_ases): Handle the
  40         ASE_XPA_VIRT flag.
  41         (parse_mips_ase_option): New function.
  42         (parse_mips_dis_option): Factor out ASE option handling to the
  43         new function.  Call `mips_calculate_combination_ases'.
  44         * mips-opc.c (XPAVZ): New macro.
  45         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
  46         "mfhgc0", "mthc0" and "mthgc0".
  47
  48 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
  49
  50         * mips-dis.c (mips_calculate_combination_ases): New function.
  51         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
  52         calculation to the new function.
  53         (set_default_mips_dis_options): Call the new function.
  54
  55 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  56
  57         * arc-dis.c (parse_disassembler_options): Use
  58         FOR_EACH_DISASSEMBLER_OPTION.
  59
  60 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  61
  62         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
  63         disassembler option strings.
  64         (parse_cpu_option): Likewise.
  65
  66 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
  67
  68         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
  69         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
  70         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
  71         (aarch64_feature_dotprod, DOT_INSN): New.
  72         (udot, sdot): New.
  73         * aarch64-dis-2.c: Regenerated.
  74
  75 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
  76
  77         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
  78
  79 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
  80             Matthew Fortune  <matthew.fortune@imgtec.com>
  81             Andrew Bennett  <andrew.bennett@imgtec.com>
  82
  83         * mips-formats.h (INT_BIAS): New macro.
  84         (INT_ADJ): Redefine in INT_BIAS terms.
  85         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
  86         (mips_print_save_restore): New function.
  87         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
  88         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
  89         call.
  90         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
  91         (print_mips16_insn_arg): Call `mips_print_save_restore' for
  92         OP_SAVE_RESTORE_LIST handling, factored out from here.
  93         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
  94         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
  95         (mips_builtin_opcodes): Add "restore" and "save" entries.
  96         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
  97         (IAMR2): New macro.
  98         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
  99
 100 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 101
 102         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 103         alias; do not mark SLTI instruction as an alias.
 104
 105 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 106
 107         * i386-dis.c (RM_0FAE_REG_5): Removed.
 108         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 109         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 110         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 111         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 112         PREFIX_MOD_3_0F01_REG_5_RM_0.
 113         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 114         PREFIX_MOD_3_0FAE_REG_5.
 115         (mod_table): Update MOD_0FAE_REG_5.
 116         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 117         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 118         * i386-tbl.h: Regenerated.
 119
 120 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 121
 122         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 123         * i386-opc.tbl: Likewise.
 124         * i386-tbl.h: Regenerated.
 125
 126 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 127
 128         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 129         and "jmp{&|}".
 130         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 131         prefix.
 132
 133 2017-06-19  Nick Clifton  <nickc@redhat.com>
 134
 135         PR binutils/21614
 136         * score-dis.c (score_opcodes): Add sentinel.
 137
 138 2017-06-16  Alan Modra  <amodra@gmail.com>
 139
 140         * rx-decode.c: Regenerate.
 141
 142 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 143
 144         PR binutils/21594
 145         * i386-dis.c (OP_E_register): Check valid bnd register.
 146         (OP_G): Likewise.
 147
 148 2017-06-15  Nick Clifton  <nickc@redhat.com>
 149
 150         PR binutils/21595
 151         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 152         range value.
 153
 154 2017-06-15  Nick Clifton  <nickc@redhat.com>
 155
 156         PR binutils/21588
 157         * rl78-decode.opc (OP_BUF_LEN): Define.
 158         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 159         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 160         array.
 161         * rl78-decode.c: Regenerate.
 162
 163 2017-06-15  Nick Clifton  <nickc@redhat.com>
 164
 165         PR binutils/21586
 166         * bfin-dis.c (gregs): Clip index to prevent overflow.
 167         (regs): Likewise.
 168         (regs_lo): Likewise.
 169         (regs_hi): Likewise.
 170
 171 2017-06-14  Nick Clifton  <nickc@redhat.com>
 172
 173         PR binutils/21576
 174         * score7-dis.c (score_opcodes): Add sentinel.
 175
 176 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 177
 178         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 179         * arm-dis.c: Likewise.
 180         * ia64-dis.c: Likewise.
 181         * mips-dis.c: Likewise.
 182         * spu-dis.c: Likewise.
 183         * disassemble.h (print_insn_aarch64): New declaration, moved from
 184         include/dis-asm.h.
 185         (print_insn_big_arm, print_insn_big_mips): Likewise.
 186         (print_insn_i386, print_insn_ia64): Likewise.
 187         (print_insn_little_arm, print_insn_little_mips): Likewise.
 188
 189 2017-06-14  Nick Clifton  <nickc@redhat.com>
 190
 191         PR binutils/21587
 192         * rx-decode.opc: Include libiberty.h
 193         (GET_SCALE): New macro - validates access to SCALE array.
 194         (GET_PSCALE): New macro - validates access to PSCALE array.
 195         (DIs, SIs, S2Is, rx_disp): Use new macros.
 196         * rx-decode.c: Regenerate.
 197
 198 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 199
 200         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 201
 202 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 203
 204         * arc-dis.c (enforced_isa_mask): Declare.
 205         (cpu_types): Likewise.
 206         (parse_cpu_option): New function.
 207         (parse_disassembler_options): Use it.
 208         (print_insn_arc): Use enforced_isa_mask.
 209         (print_arc_disassembler_options): Document new options.
 210
 211 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 212
 213         * alpha-dis.c: Include disassemble.h, don't include
 214         dis-asm.h.
 215         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 216         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 217         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 218         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 219         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 220         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 221         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 222         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 223         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 224         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 225         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 226         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 227         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 228         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 229         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 230         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 231         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 232         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 233         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 234         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 235         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 236         * z80-dis.c, z8k-dis.c: Likewise.
 237         * disassemble.h: New file.
 238
 239 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 240
 241         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 242         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 243
 244 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 245
 246         * disassemble.c (disassembler): Add arguments a, big and mach.
 247         Use them.
 248
 249 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 250
 251         * i386-dis.c (NOTRACK_Fixup): New.
 252         (NOTRACK): Likewise.
 253         (NOTRACK_PREFIX): Likewise.
 254         (last_active_prefix): Likewise.
 255         (reg_table): Use NOTRACK on indirect call and jmp.
 256         (ckprefix): Set last_active_prefix.
 257         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 258         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 259         * i386-opc.h (NoTrackPrefixOk): New.
 260         (i386_opcode_modifier): Add notrackprefixok.
 261         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 262         Add notrack.
 263         * i386-tbl.h: Regenerated.
 264
 265 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 266
 267         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 268         (X_IMM2): Define.
 269         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 270         bfd_mach_sparc_v9m8.
 271         (print_insn_sparc): Handle new operand types.
 272         * sparc-opc.c (MASK_M8): Define.
 273         (v6): Add MASK_M8.
 274         (v6notlet): Likewise.
 275         (v7): Likewise.
 276         (v8): Likewise.
 277         (v9): Likewise.
 278         (v9a): Likewise.
 279         (v9b): Likewise.
 280         (v9c): Likewise.
 281         (v9d): Likewise.
 282         (v9e): Likewise.
 283         (v9v): Likewise.
 284         (v9m): Likewise.
 285         (v9andleon): Likewise.
 286         (m8): Define.
 287         (HWS_VM8): Define.
 288         (HWS2_VM8): Likewise.
 289         (sparc_opcode_archs): Add entry for "m8".
 290         (sparc_opcodes): Add OSA2017 and M8 instructions
 291         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 292         fpx{ll,ra,rl}64x,
 293         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 294         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 295         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 296         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 297         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 298         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 299         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 300         ASI_CORE_SELECT_COMMIT_NHT.
 301
 302 2017-05-18  Alan Modra  <amodra@gmail.com>
 303
 304         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 305         * aarch64-dis.c: Likewise.
 306         * aarch64-gen.c: Likewise.
 307         * aarch64-opc.c: Likewise.
 308
 309 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 310             Matthew Fortune  <matthew.fortune@imgtec.com>
 311
 312         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 313         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 314         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 315         (print_insn_arg) <OP_REG28>: Add handler.
 316         (validate_insn_args) <OP_REG28>: Handle.
 317         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 318         32-bit encoding and 9-bit immediates.
 319         (print_insn_mips16): Handle MIPS16 instructions that require
 320         32-bit encoding and MFC0/MTC0 operand decoding.
 321         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 322         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 323         (RD_C0, WR_C0, E2, E2MT): New macros.
 324         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 325         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 326         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 327         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 328         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 329         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 330         instructions, "swl", "swr", "sync" and its "sync_acquire",
 331         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 332         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 333         regular/extended entries for original MIPS16 ISA revision
 334         instructions whose extended forms are subdecoded in the MIPS16e2
 335         ISA revision: "li", "sll" and "srl".
 336
 337 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 338
 339         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 340         reference in CP0 move operand decoding.
 341
 342 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 343
 344         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 345         type to hexadecimal.
 346         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 347
 348 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 349
 350         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 351         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 352         "sync_rmb" and "sync_wmb" as aliases.
 353         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 354         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 355
 356 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 357
 358         * arc-dis.c (parse_option): Update quarkse_em option..
 359         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 360         QUARKSE1.
 361         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 362
 363 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 364
 365         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 366
 367 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 368
 369         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 370         register.
 371
 372 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 373
 374         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 375         and branches and not synthetic data instructions.
 376
 377 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 378
 379         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 380
 381 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 382
 383         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 384         * arc-opc.c (insert_r13el): New function.
 385         (R13_EL): Define.
 386         * arc-tbl.h: Add new enter/leave variants.
 387
 388 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 389
 390         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 391
 392 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 393
 394         * mips-dis.c (print_mips_disassembler_options): Add
 395         `no-aliases'.
 396
 397 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 398
 399         * mips16-opc.c (AL): New macro.
 400         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 401         of "ld" and "lw" as aliases.
 402
 403 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 404
 405         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 406         arguments.
 407
 408 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 409             Alan Modra  <amodra@gmail.com>
 410
 411         * ppc-opc.c (ELEV): Define.
 412         (vle_opcodes): Add se_rfgi and e_sc.
 413         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 414         for E200Z4.
 415
 416 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 417
 418         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 419
 420 2017-04-21  Nick Clifton  <nickc@redhat.com>
 421
 422         PR binutils/21380
 423         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 424         LD3R and LD4R.
 425
 426 2017-04-13  Alan Modra  <amodra@gmail.com>
 427
 428         * epiphany-desc.c: Regenerate.
 429         * fr30-desc.c: Regenerate.
 430         * frv-desc.c: Regenerate.
 431         * ip2k-desc.c: Regenerate.
 432         * iq2000-desc.c: Regenerate.
 433         * lm32-desc.c: Regenerate.
 434         * m32c-desc.c: Regenerate.
 435         * m32r-desc.c: Regenerate.
 436         * mep-desc.c: Regenerate.
 437         * mt-desc.c: Regenerate.
 438         * or1k-desc.c: Regenerate.
 439         * xc16x-desc.c: Regenerate.
 440         * xstormy16-desc.c: Regenerate.
 441
 442 2017-04-11  Alan Modra  <amodra@gmail.com>
 443
 444         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 445         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 446         PPC_OPCODE_TMR for e6500.
 447         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 448         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 449         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 450         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 451         (PPCHTM): Define as PPC_OPCODE_POWER8.
 452         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 453
 454 2017-04-10  Alan Modra  <amodra@gmail.com>
 455
 456         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 457         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 458         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 459         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 460
 461 2017-04-09  Pip Cet  <pipcet@gmail.com>
 462
 463         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 464         appropriate floating-point precision directly.
 465
 466 2017-04-07  Alan Modra  <amodra@gmail.com>
 467
 468         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 469         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 470         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 471         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 472         vector instructions with E6500 not PPCVEC2.
 473
 474 2017-04-06  Pip Cet  <pipcet@gmail.com>
 475
 476         * Makefile.am: Add wasm32-dis.c.
 477         * configure.ac: Add wasm32-dis.c to wasm32 target.
 478         * disassemble.c: Add wasm32 disassembler code.
 479         * wasm32-dis.c: New file.
 480         * Makefile.in: Regenerate.
 481         * configure: Regenerate.
 482         * po/POTFILES.in: Regenerate.
 483         * po/opcodes.pot: Regenerate.
 484
 485 2017-04-05  Pedro Alves  <palves@redhat.com>
 486
 487         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 488         * arm-dis.c (parse_arm_disassembler_options): Constify.
 489         * ppc-dis.c (powerpc_init_dialect): Constify local.
 490         * vax-dis.c (parse_disassembler_options): Constify.
 491
 492 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 493
 494         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 495         RISCV_GP_SYMBOL.
 496
 497 2017-03-30  Pip Cet  <pipcet@gmail.com>
 498
 499         * configure.ac: Add (empty) bfd_wasm32_arch target.
 500         * configure: Regenerate
 501         * po/opcodes.pot: Regenerate.
 502
 503 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 504
 505         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 506         OSA2015.
 507         * opcodes/sparc-opc.c (asi_table): New ASIs.
 508
 509 2017-03-29  Alan Modra  <amodra@gmail.com>
 510
 511         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 512         "raw" option.
 513         (lookup_powerpc): Don't special case -1 dialect.  Handle
 514         PPC_OPCODE_RAW.
 515         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 516         lookup_powerpc call, pass it on second.
 517
 518 2017-03-27  Alan Modra  <amodra@gmail.com>
 519
 520         PR 21303
 521         * ppc-dis.c (struct ppc_mopt): Comment.
 522         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 523
 524 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 525
 526         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 527         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 528         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 529         (insert_nps_misc_imm_offset): New function.
 530         (extract_nps_misc imm_offset): New function.
 531         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 532         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 533
 534 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 535
 536         * s390-mkopc.c (main): Remove vx2 check.
 537         * s390-opc.txt: Remove vx2 instruction flags.
 538
 539 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 540
 541         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 542         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 543         (insert_nps_imm_offset): New function.
 544         (extract_nps_imm_offset): New function.
 545         (insert_nps_imm_entry): New function.
 546         (extract_nps_imm_entry): New function.
 547
 548 2017-03-17  Alan Modra  <amodra@gmail.com>
 549
 550         PR 21248
 551         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 552         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 553         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 554
 555 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 556
 557         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 558         <c.andi>: Likewise.
 559         <c.addiw> Likewise.
 560
 561 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 562
 563         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 564
 565 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 566
 567         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 568         <srl> Likewise.
 569         <srai> Likewise.
 570         <sra> Likewise.
 571
 572 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 573
 574         * i386-gen.c (opcode_modifiers): Replace S with Load.
 575         * i386-opc.h (S): Removed.
 576         (Load): New.
 577         (i386_opcode_modifier): Replace s with load.
 578         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 579         and {evex}.  Replace S with Load.
 580         * i386-tbl.h: Regenerated.
 581
 582 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 583
 584         * i386-opc.tbl: Use CpuCET on rdsspq.
 585         * i386-tbl.h: Regenerated.
 586
 587 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 588
 589         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 590         <vsx>: Do not use PPC_OPCODE_VSX3;
 591
 592 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 593
 594         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 595
 596 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 597
 598         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 599         (MOD_0F1E_PREFIX_1): Likewise.
 600         (MOD_0F38F5_PREFIX_2): Likewise.
 601         (MOD_0F38F6_PREFIX_0): Likewise.
 602         (RM_0F1E_MOD_3_REG_7): Likewise.
 603         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 604         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 605         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 606         (PREFIX_0F1E): Likewise.
 607         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 608         (PREFIX_0F38F5): Likewise.
 609         (dis386_twobyte): Use PREFIX_0F1E.
 610         (reg_table): Add REG_0F1E_MOD_3.
 611         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 612         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 613         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 614         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 615         (three_byte_table): Use PREFIX_0F38F5.
 616         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 617         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 618         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 619         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 620         PREFIX_MOD_3_0F01_REG_5_RM_2.
 621         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 622         (cpu_flags): Add CpuCET.
 623         * i386-opc.h (CpuCET): New enum.
 624         (CpuUnused): Commented out.
 625         (i386_cpu_flags): Add cpucet.
 626         * i386-opc.tbl: Add Intel CET instructions.
 627         * i386-init.h: Regenerated.
 628         * i386-tbl.h: Likewise.
 629
 630 2017-03-06  Alan Modra  <amodra@gmail.com>
 631
 632         PR 21124
 633         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 634         (extract_raq, extract_ras, extract_rbx): New functions.
 635         (powerpc_operands): Use opposite corresponding insert function.
 636         (Q_MASK): Define.
 637         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 638         register restriction.
 639
 640 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 641
 642         * disassemble.c Include "safe-ctype.h".
 643         (disassemble_init_for_target): Handle s390 init.
 644         (remove_whitespace_and_extra_commas): New function.
 645         (disassembler_options_cmp): Likewise.
 646         * arm-dis.c: Include "libiberty.h".
 647         (NUM_ELEM): Delete.
 648         (regnames): Use long disassembler style names.
 649         Add force-thumb and no-force-thumb options.
 650         (NUM_ARM_REGNAMES): Rename from this...
 651         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 652         (get_arm_regname_num_options): Delete.
 653         (set_arm_regname_option): Likewise.
 654         (get_arm_regnames): Likewise.
 655         (parse_disassembler_options): Likewise.
 656         (parse_arm_disassembler_option): Rename from this...
 657         (parse_arm_disassembler_options): ...to this.  Make static.
 658         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 659         (print_insn): Use parse_arm_disassembler_options.
 660         (disassembler_options_arm): New function.
 661         (print_arm_disassembler_options): Handle updated regnames.
 662         * ppc-dis.c: Include "libiberty.h".
 663         (ppc_opts): Add "32" and "64" entries.
 664         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 665         (powerpc_init_dialect): Add break to switch statement.
 666         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 667         (disassembler_options_powerpc): New function.
 668         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 669         Remove printing of "32" and "64".
 670         * s390-dis.c: Include "libiberty.h".
 671         (init_flag): Remove unneeded variable.
 672         (struct s390_options_t): New structure type.
 673         (options): New structure.
 674         (init_disasm): Rename from this...
 675         (disassemble_init_s390): ...to this.  Add initializations for
 676         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 677         (print_insn_s390): Delete call to init_disasm.
 678         (disassembler_options_s390): New function.
 679         (print_s390_disassembler_options): Print using information from
 680         struct 'options'.
 681         * po/opcodes.pot: Regenerate.
 682
 683 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 684
 685         * i386-dis.c (PCMPESTR_Fixup): New.
 686         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 687         (prefix_table): Use PCMPESTR_Fixup.
 688         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 689         PCMPESTR_Fixup.
 690         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 691         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 692         Split 64-bit and non-64-bit variants.
 693         * opcodes/i386-tbl.h: Re-generate.
 694
 695 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 696
 697         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 698         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 699         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 700         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 701         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 702         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 703         (OP_SVE_V_HSD): New macros.
 704         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 705         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 706         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 707         (aarch64_opcode_table): Add new SVE instructions.
 708         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 709         for rotation operands.  Add new SVE operands.
 710         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 711         (ins_sve_quad_index): Likewise.
 712         (ins_imm_rotate): Split into...
 713         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 714         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 715         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 716         functions.
 717         (aarch64_ins_sve_addr_ri_s4): New function.
 718         (aarch64_ins_sve_quad_index): Likewise.
 719         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 720         * aarch64-asm-2.c: Regenerate.
 721         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 722         (ext_sve_quad_index): Likewise.
 723         (ext_imm_rotate): Split into...
 724         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 725         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 726         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 727         functions.
 728         (aarch64_ext_sve_addr_ri_s4): New function.
 729         (aarch64_ext_sve_quad_index): Likewise.
 730         (aarch64_ext_sve_index): Allow quad indices.
 731         (do_misc_decoding): Likewise.
 732         * aarch64-dis-2.c: Regenerate.
 733         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 734         aarch64_field_kinds.
 735         (OPD_F_OD_MASK): Widen by one bit.
 736         (OPD_F_NO_ZR): Bump accordingly.
 737         (get_operand_field_width): New function.
 738         * aarch64-opc.c (fields): Add new SVE fields.
 739         (operand_general_constraint_met_p): Handle new SVE operands.
 740         (aarch64_print_operand): Likewise.
 741         * aarch64-opc-2.c: Regenerate.
 742
 743 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 744
 745         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 746         (aarch64_feature_compnum): ...this.
 747         (SIMD_V8_3): Replace with...
 748         (COMPNUM): ...this.
 749         (CNUM_INSN): New macro.
 750         (aarch64_opcode_table): Use it for the complex number instructions.
 751
 752 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 753
 754         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 755
 756 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 757
 758         Add support for associating SPARC ASIs with an architecture level.
 759         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 760         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 761         decoding of SPARC ASIs.
 762
 763 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 764
 765         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 766         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 767
 768 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 769
 770         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 771         1 (instead of to itself). Correct typo.
 772
 773 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 774
 775         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 776         pseudoinstructions.
 777
 778 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 779
 780         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 781         (aarch64_sys_reg_supported_p): Handle them.
 782
 783 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 784
 785         * arc-opc.c (UIMM6_20R): Define.
 786         (SIMM12_20): Use above.
 787         (SIMM12_20R): Define.
 788         (SIMM3_5_S): Use above.
 789         (UIMM7_A32_11R_S): Define.
 790         (UIMM7_9_S): Use above.
 791         (UIMM3_13R_S): Define.
 792         (SIMM11_A32_7_S): Use above.
 793         (SIMM9_8R): Define.
 794         (UIMM10_A32_8_S): Use above.
 795         (UIMM8_8R_S): Define.
 796         (W6): Use above.
 797         (arc_relax_opcodes): Use all above defines.
 798
 799 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 800
 801         * arc-regs.h: Distinguish some of the registers different on
 802         ARC700 and HS38 cpus.
 803
 804 2017-02-14  Alan Modra  <amodra@gmail.com>
 805
 806         PR 21118
 807         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 808         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 809
 810 2017-02-11  Stafford Horne  <shorne@gmail.com>
 811             Alan Modra  <amodra@gmail.com>
 812
 813         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 814         Use insn_bytes_value and insn_int_value directly instead.  Don't
 815         free allocated memory until function exit.
 816
 817 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 818
 819         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 820
 821 2017-02-03  Nick Clifton  <nickc@redhat.com>
 822
 823         PR 21096
 824         * aarch64-opc.c (print_register_list): Ensure that the register
 825         list index will fir into the tb buffer.
 826         (print_register_offset_address): Likewise.
 827         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 828
 829 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 830
 831         PR 21056
 832         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 833         instructions when the previous fetch packet ends with a 32-bit
 834         instruction.
 835
 836 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 837
 838         * pru-opc.c: Remove vague reference to a future GDB port.
 839
 840 2017-01-20  Nick Clifton  <nickc@redhat.com>
 841
 842         * po/ga.po: Updated Irish translation.
 843
 844 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 845
 846         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 847
 848 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 849
 850         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 851         if FETCH_DATA returns 0.
 852         (m68k_scan_mask): Likewise.
 853         (print_insn_m68k): Update code to handle -1 return value.
 854
 855 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 856
 857         * m68k-dis.c (enum print_insn_arg_error): New.
 858         (NEXTBYTE): Replace -3 with
 859         PRINT_INSN_ARG_MEMORY_ERROR.
 860         (NEXTULONG): Likewise.
 861         (NEXTSINGLE): Likewise.
 862         (NEXTDOUBLE): Likewise.
 863         (NEXTDOUBLE): Likewise.
 864         (NEXTPACKED): Likewise.
 865         (FETCH_ARG): Likewise.
 866         (FETCH_DATA): Update comments.
 867         (print_insn_arg): Update comments. Replace magic numbers with
 868         enum.
 869         (match_insn_m68k): Likewise.
 870
 871 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 872
 873         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 874         * i386-dis-evex.h (evex_table): Updated.
 875         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 876         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 877         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 878         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 879         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 880         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 881         * i386-init.h: Regenerate.
 882         * i386-tbl.h: Ditto.
 883
 884 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 885
 886         * msp430-dis.c (msp430_singleoperand): Return -1 if
 887         msp430dis_opcode_signed returns false.
 888         (msp430_doubleoperand): Likewise.
 889         (msp430_branchinstr): Return -1 if
 890         msp430dis_opcode_unsigned returns false.
 891         (msp430x_calla_instr): Likewise.
 892         (print_insn_msp430): Likewise.
 893
 894 2017-01-05  Nick Clifton  <nickc@redhat.com>
 895
 896         PR 20946
 897         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 898         could not be matched.
 899         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 900         NULL.
 901
 902 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 903
 904         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 905         (aarch64_opcode_table): Use RCPC_INSN.
 906
 907 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 908
 909         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 910         extension.
 911         * riscv-opcodes/all-opcodes: Likewise.
 912
 913 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 914
 915         * riscv-dis.c (print_insn_args): Add fall through comment.
 916
 917 2017-01-03  Nick Clifton  <nickc@redhat.com>
 918
 919         * po/sr.po: New Serbian translation.
 920         * configure.ac (ALL_LINGUAS): Add sr.
 921         * configure: Regenerate.
 922
 923 2017-01-02  Alan Modra  <amodra@gmail.com>
 924
 925         * epiphany-desc.h: Regenerate.
 926         * epiphany-opc.h: Regenerate.
 927         * fr30-desc.h: Regenerate.
 928         * fr30-opc.h: Regenerate.
 929         * frv-desc.h: Regenerate.
 930         * frv-opc.h: Regenerate.
 931         * ip2k-desc.h: Regenerate.
 932         * ip2k-opc.h: Regenerate.
 933         * iq2000-desc.h: Regenerate.
 934         * iq2000-opc.h: Regenerate.
 935         * lm32-desc.h: Regenerate.
 936         * lm32-opc.h: Regenerate.
 937         * m32c-desc.h: Regenerate.
 938         * m32c-opc.h: Regenerate.
 939         * m32r-desc.h: Regenerate.
 940         * m32r-opc.h: Regenerate.
 941         * mep-desc.h: Regenerate.
 942         * mep-opc.h: Regenerate.
 943         * mt-desc.h: Regenerate.
 944         * mt-opc.h: Regenerate.
 945         * or1k-desc.h: Regenerate.
 946         * or1k-opc.h: Regenerate.
 947         * xc16x-desc.h: Regenerate.
 948         * xc16x-opc.h: Regenerate.
 949         * xstormy16-desc.h: Regenerate.
 950         * xstormy16-opc.h: Regenerate.
 951
 952 2017-01-02  Alan Modra  <amodra@gmail.com>
 953
 954         Update year range in copyright notice of all files.
 955
 956 For older changes see ChangeLog-2016
 957 \f
 958 Copyright (C) 2017 Free Software Foundation, Inc.
 959
 960 Copying and distribution of this file, with or without modification,
 961 are permitted in any medium without royalty provided the copyright
 962 notice and this notice are preserved.
 963
 964 Local Variables:
 965 mode: change-log
 966 left-margin: 8
 967 fill-column: 74
 968 version-control: never
 969 End: