opcodes/ChangeLog

   1 2018-07-19  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl: Fold AVX512CD templates into their respective
   4         AVX512VL counterparts where possible, using Disp8ShiftVL and
   5         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
   6         IgnoreSize) as appropriate.
   7         * i386-tbl.h: Re-generate.
   8
   9 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  10
  11         * i386-opc.h (DISP8_SHIFT_VL): New.
  12         * i386-opc.tbl (Disp8ShiftVL):  Define.
  13         (various): Fold AVX512VL templates into their respective
  14         AVX512F counterparts where possible, using Disp8ShiftVL and
  15         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  16         IgnoreSize) as appropriate.
  17         * i386-tbl.h: Re-generate.
  18
  19 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  20
  21         * Makefile.am: Change dependencies and rule for
  22         $(srcdir)/i386-init.h.
  23         * Makefile.in: Re-generate.
  24         * i386-gen.c (process_i386_opcodes): New local variable
  25         "marker". Drop opening of input file. Recognize marker and line
  26         number directives.
  27         * i386-opc.tbl (OPCODE_I386_H): Define.
  28         (i386-opc.h): Include it.
  29         (None): Undefine.
  30
  31 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  32
  33         PR gas/23418
  34         * i386-opc.h (Byte): Update comments.
  35         (Word): Likewise.
  36         (Dword): Likewise.
  37         (Fword): Likewise.
  38         (Qword): Likewise.
  39         (Tbyte): Likewise.
  40         (Xmmword): Likewise.
  41         (Ymmword): Likewise.
  42         (Zmmword): Likewise.
  43         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
  44         vcvttps2uqq.
  45         * i386-tbl.h: Regenerated.
  46
  47 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
  48
  49         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
  50         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
  51         * aarch64-asm-2.c: Regenerate.
  52         * aarch64-dis-2.c: Regenerate.
  53         * aarch64-opc-2.c: Regenerate.
  54
  55 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
  56
  57         PR binutils/23192
  58         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
  59         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
  60         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
  61         sqdmulh, sqrdmulh): Use Em16.
  62
  63 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
  64
  65         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
  66         csdb together with them.
  67         (thumb32_opcodes): Likewise.
  68
  69 2018-07-11  Jan Beulich  <jbeulich@suse.com>
  70
  71         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
  72         requiring 32-bit registers as operands 2 and 3. Improve
  73         comments.
  74         (mwait, mwaitx): Fold templates. Improve comments.
  75         OPERAND_TYPE_INOUTPORTREG.
  76         * i386-tbl.h: Re-generate.
  77
  78 2018-07-11  Jan Beulich  <jbeulich@suse.com>
  79
  80         * i386-gen.c (operand_type_init): Remove
  81         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
  82         OPERAND_TYPE_INOUTPORTREG.
  83         * i386-init.h: Re-generate.
  84
  85 2018-07-11  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-opc.tbl (wrssd, wrussd): Add Dword.
  88         (wrssq, wrussq): Add Qword.
  89         * i386-tbl.h: Re-generate.
  90
  91 2018-07-11  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-opc.h: Rename OTMax to OTNum.
  94         (OTNumOfUints): Adjust calculation.
  95         (OTUnused): Directly alias to OTNum.
  96
  97 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
  98
  99         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 100         `reg_xys'.
 101         (lea_reg_xys): Likewise.
 102         (print_insn_loop_primitive): Rename `reg' local variable to
 103         `reg_dxy'.
 104
 105 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 106
 107         PR binutils/23242
 108         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 109
 110 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 111
 112         PR binutils/23369
 113         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 114         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 115
 116 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 117
 118         PR tdep/8282
 119         * mips-dis.c (mips_option_arg_t): New enumeration.
 120         (mips_options): New variable.
 121         (disassembler_options_mips): New function.
 122         (print_mips_disassembler_options): Reimplement in terms of
 123         `disassembler_options_mips'.
 124         * arm-dis.c (disassembler_options_arm): Adapt to using the
 125         `disasm_options_and_args_t' structure.
 126         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 127         * s390-dis.c (disassembler_options_s390): Likewise.
 128
 129 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 130
 131         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 132         expected result.
 133         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 134         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 135         * testsuite/ld-arm/tls-longplt.d: Likewise.
 136
 137 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 138
 139         PR binutils/23192
 140         * aarch64-asm-2.c: Regenerate.
 141         * aarch64-dis-2.c: Likewise.
 142         * aarch64-opc-2.c: Likewise.
 143         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 144         * aarch64-opc.c (operand_general_constraint_met_p,
 145         aarch64_print_operand): Likewise.
 146         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 147         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 148         fmlal2, fmlsl2.
 149         (AARCH64_OPERANDS): Add Em2.
 150
 151 2018-06-26  Nick Clifton  <nickc@redhat.com>
 152
 153         * po/uk.po: Updated Ukranian translation.
 154         * po/de.po: Updated German translation.
 155         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 156
 157 2018-06-26  Nick Clifton  <nickc@redhat.com>
 158
 159         * nfp-dis.c: Fix spelling mistake.
 160
 161 2018-06-24  Nick Clifton  <nickc@redhat.com>
 162
 163         * configure: Regenerate.
 164         * po/opcodes.pot: Regenerate.
 165
 166 2018-06-24  Nick Clifton  <nickc@redhat.com>
 167
 168         2.31 branch created.
 169
 170 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 171
 172         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 173         * aarch64-asm-2.c: Regenerate.
 174         * aarch64-dis-2.c: Likewise.
 175
 176 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 177
 178         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 179         `-M ginv' option description.
 180
 181 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 182
 183         PR gas/23305
 184         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 185         la and lla.
 186
 187 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 188
 189         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 190         * configure.ac: Remove AC_PREREQ.
 191         * Makefile.in: Re-generate.
 192         * aclocal.m4: Re-generate.
 193         * configure: Re-generate.
 194
 195 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 196
 197         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 198         mips64r6 descriptors.
 199         (parse_mips_ase_option): Handle -Mginv option.
 200         (print_mips_disassembler_options): Document -Mginv.
 201         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 202         (GINV): New macro.
 203         (mips_opcodes): Define ginvi and ginvt.
 204
 205 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 206             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 207
 208         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 209         * mips-opc.c (CRC, CRC64): New macros.
 210         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 211         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 212         crc32cd for CRC64.
 213
 214 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 215
 216         PR 20319
 217         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 218         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 219
 220 2018-06-06  Alan Modra  <amodra@gmail.com>
 221
 222         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 223         setjmp.  Move init for some other vars later too.
 224
 225 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 226
 227         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 228         (dis_private): Add new fields for property section tracking.
 229         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 230         (xtensa_instruction_fits): New functions.
 231         (fetch_data): Bump minimal fetch size to 4.
 232         (print_insn_xtensa): Make struct dis_private static.
 233         Load and prepare property table on section change.
 234         Don't disassemble literals. Don't disassemble instructions that
 235         cross property table boundaries.
 236
 237 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 238
 239         * configure: Regenerated.
 240
 241 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 242
 243         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 244         * i386-tbl.h: Re-generate.
 245
 246 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 247
 248         * i386-opc.tbl (sldt, str): Add NoRex64.
 249         * i386-tbl.h: Re-generate.
 250
 251 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-opc.tbl (invpcid): Add Oword.
 254         * i386-tbl.h: Re-generate.
 255
 256 2018-06-01  Alan Modra  <amodra@gmail.com>
 257
 258         * sysdep.h (_bfd_error_handler): Don't declare.
 259         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 260         * rl78-decode.opc: Likewise.
 261         * msp430-decode.c: Regenerate.
 262         * rl78-decode.c: Regenerate.
 263
 264 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 265
 266         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 267         * i386-init.h : Regenerated.
 268
 269 2018-05-25  Alan Modra  <amodra@gmail.com>
 270
 271         * Makefile.in: Regenerate.
 272         * po/POTFILES.in: Regenerate.
 273
 274 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 275
 276         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 277         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 278         (insert_bab, extract_bab, insert_btab, extract_btab,
 279         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 280         (BAT, BBA VBA RBS XB6S): Delete macros.
 281         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 282         (BB, BD, RBX, XC6): Update for new macros.
 283         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 284         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 285         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 286         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 287
 288 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 289
 290         * Makefile.am: Add support for s12z architecture.
 291         * configure.ac: Likewise.
 292         * disassemble.c: Likewise.
 293         * disassemble.h: Likewise.
 294         * Makefile.in: Regenerate.
 295         * configure: Regenerate.
 296         * s12z-dis.c: New file.
 297         * s12z.h: New file.
 298
 299 2018-05-18  Alan Modra  <amodra@gmail.com>
 300
 301         * nfp-dis.c: Don't #include libbfd.h.
 302         (init_nfp3200_priv): Use bfd_get_section_contents.
 303         (nit_nfp6000_mecsr_sec): Likewise.
 304
 305 2018-05-17  Nick Clifton  <nickc@redhat.com>
 306
 307         * po/zh_CN.po: Updated simplified Chinese translation.
 308
 309 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 310
 311         PR binutils/23109
 312         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 313         * aarch64-dis-2.c: Regenerate.
 314
 315 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 316
 317         PR binutils/21446
 318         * aarch64-asm.c (opintl.h): Include.
 319         (aarch64_ins_sysreg): Enforce read/write constraints.
 320         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 321         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 322         (F_REG_READ, F_REG_WRITE): New.
 323         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 324         AARCH64_OPND_SYSREG.
 325         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 326         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 327         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 328         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 329         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 330         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 331         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 332         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 333         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 334         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 335         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 336         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 337         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 338         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 339         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 340         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 341         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 342
 343 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 344
 345         PR binutils/21446
 346         * aarch64-dis.c (no_notes: New.
 347         (parse_aarch64_dis_option): Support notes.
 348         (aarch64_decode_insn, print_operands): Likewise.
 349         (print_aarch64_disassembler_options): Document notes.
 350         * aarch64-opc.c (aarch64_print_operand): Support notes.
 351
 352 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 353
 354         PR binutils/21446
 355         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 356         and take error struct.
 357         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 358         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 359         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 360         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 361         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 362         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 363         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 364         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 365         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 366         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 367         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 368         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 369         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 370         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 371         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 372         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 373         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 374         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 375         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 376         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 377         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 378         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 379         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 380         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 381         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 382         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 383         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 384         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 385         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 386         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 387         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 388         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 389         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 390         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 391         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 392         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 393         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 394         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 395         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 396         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 397         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 398         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 399         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 400         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 401         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 402         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 403         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 404         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 405         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 406         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 407         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 408         (determine_disassembling_preference, aarch64_decode_insn,
 409         print_insn_aarch64_word, print_insn_data): Take errors struct.
 410         (print_insn_aarch64): Use errors.
 411         * aarch64-asm-2.c: Regenerate.
 412         * aarch64-dis-2.c: Regenerate.
 413         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 414         boolean in aarch64_insert_operan.
 415         (print_operand_extractor): Likewise.
 416         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 417
 418 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 419
 420         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 421
 422 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 423
 424         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 425
 426 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 427
 428         * cr16-opc.c (cr16_instruction): Comment typo fix.
 429         * hppa-dis.c (print_insn_hppa): Likewise.
 430
 431 2018-05-08  Jim Wilson  <jimw@sifive.com>
 432
 433         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 434         (match_c_slli64, match_srxi_as_c_srxi): New.
 435         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 436         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 437         <c.slli, c.srli, c.srai>: Use match_s_slli.
 438         <c.slli64, c.srli64, c.srai64>: New.
 439
 440 2018-05-08  Alan Modra  <amodra@gmail.com>
 441
 442         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 443         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 444         partition opcode space for index lookup.
 445
 446 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 447
 448         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 449         <insn_length>: ...with this.  Update usage.
 450         Remove duplicate call to *info->memory_error_func.
 451
 452 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 453             H.J. Lu  <hongjiu.lu@intel.com>
 454
 455         * i386-dis.c (Gva): New.
 456         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 457         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 458         (prefix_table): New instructions (see prefix above).
 459         (mod_table): New instructions (see prefix above).
 460         (OP_G): Handle va_mode.
 461         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 462         CPU_MOVDIR64B_FLAGS.
 463         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 464         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 465         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 466         * i386-opc.tbl: Add movidir{i,64b}.
 467         * i386-init.h: Regenerated.
 468         * i386-tbl.h: Likewise.
 469
 470 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 471
 472         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 473         AddrPrefixOpReg.
 474         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 475         (AddrPrefixOpReg): This.
 476         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 477         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 478
 479 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 480
 481         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 482         (vle_num_opcodes): Likewise.
 483         (spe2_num_opcodes): Likewise.
 484         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 485         initialization loop.
 486         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 487         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 488         only once.
 489
 490 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 491
 492         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 493
 494 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 495
 496         Makefile.am: Added nfp-dis.c.
 497         configure.ac: Added bfd_nfp_arch.
 498         disassemble.h: Added print_insn_nfp prototype.
 499         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 500         nfp-dis.c: New, for NFP support.
 501         po/POTFILES.in: Added nfp-dis.c to the list.
 502         Makefile.in: Regenerate.
 503         configure: Regenerate.
 504
 505 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 506
 507         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 508         templates into their base ones.
 509         * i386-tlb.h: Re-generate.
 510
 511 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 512
 513         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 514         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 515         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 516         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 517         * i386-init.h: Re-generate.
 518
 519 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 520
 521         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 522         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 523         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 524         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 525         comment.
 526         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 527         and CpuRegMask.
 528         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 529         CpuRegMask: Delete.
 530         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 531         cpuregzmm, and cpuregmask.
 532         * i386-init.h: Re-generate.
 533         * i386-tbl.h: Re-generate.
 534
 535 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 536
 537         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 538         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 539         * i386-init.h: Re-generate.
 540
 541 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 542
 543         * i386-gen.c (VexImmExt): Delete.
 544         * i386-opc.h (VexImmExt, veximmext): Delete.
 545         * i386-opc.tbl: Drop all VexImmExt uses.
 546         * i386-tlb.h: Re-generate.
 547
 548 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 549
 550         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 551         register-only forms.
 552         * i386-tlb.h: Re-generate.
 553
 554 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 555
 556         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 557
 558 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 559
 560         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 561         PREFIX_0F1C.
 562         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 563         (cpu_flags): Add CpuCLDEMOTE.
 564         * i386-init.h: Regenerate.
 565         * i386-opc.h (enum): Add CpuCLDEMOTE,
 566         (i386_cpu_flags): Add cpucldemote.
 567         * i386-opc.tbl: Add cldemote.
 568         * i386-tbl.h: Regenerate.
 569
 570 2018-04-16  Alan Modra  <amodra@gmail.com>
 571
 572         * Makefile.am: Remove sh5 and sh64 support.
 573         * configure.ac: Likewise.
 574         * disassemble.c: Likewise.
 575         * disassemble.h: Likewise.
 576         * sh-dis.c: Likewise.
 577         * sh64-dis.c: Delete.
 578         * sh64-opc.c: Delete.
 579         * sh64-opc.h: Delete.
 580         * Makefile.in: Regenerate.
 581         * configure: Regenerate.
 582         * po/POTFILES.in: Regenerate.
 583
 584 2018-04-16  Alan Modra  <amodra@gmail.com>
 585
 586         * Makefile.am: Remove w65 support.
 587         * configure.ac: Likewise.
 588         * disassemble.c: Likewise.
 589         * disassemble.h: Likewise.
 590         * w65-dis.c: Delete.
 591         * w65-opc.h: Delete.
 592         * Makefile.in: Regenerate.
 593         * configure: Regenerate.
 594         * po/POTFILES.in: Regenerate.
 595
 596 2018-04-16  Alan Modra  <amodra@gmail.com>
 597
 598         * configure.ac: Remove we32k support.
 599         * configure: Regenerate.
 600
 601 2018-04-16  Alan Modra  <amodra@gmail.com>
 602
 603         * Makefile.am: Remove m88k support.
 604         * configure.ac: Likewise.
 605         * disassemble.c: Likewise.
 606         * disassemble.h: Likewise.
 607         * m88k-dis.c: Delete.
 608         * Makefile.in: Regenerate.
 609         * configure: Regenerate.
 610         * po/POTFILES.in: Regenerate.
 611
 612 2018-04-16  Alan Modra  <amodra@gmail.com>
 613
 614         * Makefile.am: Remove i370 support.
 615         * configure.ac: Likewise.
 616         * disassemble.c: Likewise.
 617         * disassemble.h: Likewise.
 618         * i370-dis.c: Delete.
 619         * i370-opc.c: Delete.
 620         * Makefile.in: Regenerate.
 621         * configure: Regenerate.
 622         * po/POTFILES.in: Regenerate.
 623
 624 2018-04-16  Alan Modra  <amodra@gmail.com>
 625
 626         * Makefile.am: Remove h8500 support.
 627         * configure.ac: Likewise.
 628         * disassemble.c: Likewise.
 629         * disassemble.h: Likewise.
 630         * h8500-dis.c: Delete.
 631         * h8500-opc.h: Delete.
 632         * Makefile.in: Regenerate.
 633         * configure: Regenerate.
 634         * po/POTFILES.in: Regenerate.
 635
 636 2018-04-16  Alan Modra  <amodra@gmail.com>
 637
 638         * configure.ac: Remove tahoe support.
 639         * configure: Regenerate.
 640
 641 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 642
 643         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 644         umwait.
 645         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 646         64-bit mode.
 647         * i386-tbl.h: Regenerated.
 648
 649 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 650
 651         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 652         PREFIX_MOD_1_0FAE_REG_6.
 653         (va_mode): New.
 654         (OP_E_register): Use va_mode.
 655         * i386-dis-evex.h (prefix_table):
 656         New instructions (see prefixes above).
 657         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 658         (cpu_flags): Likewise.
 659         * i386-opc.h (enum): Likewise.
 660         (i386_cpu_flags): Likewise.
 661         * i386-opc.tbl: Add umonitor, umwait, tpause.
 662         * i386-init.h: Regenerate.
 663         * i386-tbl.h: Likewise.
 664
 665 2018-04-11  Alan Modra  <amodra@gmail.com>
 666
 667         * opcodes/i860-dis.c: Delete.
 668         * opcodes/i960-dis.c: Delete.
 669         * Makefile.am: Remove i860 and i960 support.
 670         * configure.ac: Likewise.
 671         * disassemble.c: Likewise.
 672         * disassemble.h: Likewise.
 673         * Makefile.in: Regenerate.
 674         * configure: Regenerate.
 675         * po/POTFILES.in: Regenerate.
 676
 677 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 678
 679         PR binutils/23025
 680         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 681         to 0.
 682         (print_insn): Clear vex instead of vex.evex.
 683
 684 2018-04-04  Nick Clifton  <nickc@redhat.com>
 685
 686         * po/es.po: Updated Spanish translation.
 687
 688 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 689
 690         * i386-gen.c (opcode_modifiers): Delete VecESize.
 691         * i386-opc.h (VecESize): Delete.
 692         (struct i386_opcode_modifier): Delete vecesize.
 693         * i386-opc.tbl: Drop VecESize.
 694         * i386-tlb.h: Re-generate.
 695
 696 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 697
 698         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 699         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 700         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 701         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 702         * i386-tlb.h: Re-generate.
 703
 704 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 705
 706         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 707         Fold AVX512 forms
 708         * i386-tlb.h: Re-generate.
 709
 710 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 711
 712         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 713         (vex_len_table): Drop Y for vcvt*2si.
 714         (putop): Replace plain 'Y' handling by abort().
 715
 716 2018-03-28  Nick Clifton  <nickc@redhat.com>
 717
 718         PR 22988
 719         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 720         instructions with only a base address register.
 721         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 722         handle AARHC64_OPND_SVE_ADDR_R.
 723         (aarch64_print_operand): Likewise.
 724         * aarch64-asm-2.c: Regenerate.
 725         * aarch64_dis-2.c: Regenerate.
 726         * aarch64-opc-2.c: Regenerate.
 727
 728 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 729
 730         * i386-opc.tbl: Drop VecESize from register only insn forms and
 731         memory forms not allowing broadcast.
 732         * i386-tlb.h: Re-generate.
 733
 734 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 735
 736         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 737         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 738         sha256*): Drop Disp<N>.
 739
 740 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 741
 742         * i386-dis.c (EbndS, bnd_swap_mode): New.
 743         (prefix_table): Use EbndS.
 744         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 745         * i386-opc.tbl (bndmov): Move misplaced Load.
 746         * i386-tlb.h: Re-generate.
 747
 748 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 749
 750         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 751         templates allowing memory operands and folded ones for register
 752         only flavors.
 753         * i386-tlb.h: Re-generate.
 754
 755 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 756
 757         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 758         256-bit templates. Drop redundant leftover Disp<N>.
 759         * i386-tlb.h: Re-generate.
 760
 761 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 762
 763         * riscv-opc.c (riscv_insn_types): New.
 764
 765 2018-03-13  Nick Clifton  <nickc@redhat.com>
 766
 767         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 768
 769 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 770
 771         * i386-opc.tbl: Add Optimize to clr.
 772         * i386-tbl.h: Regenerated.
 773
 774 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 775
 776         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 777         * i386-opc.h (OldGcc): Removed.
 778         (i386_opcode_modifier): Remove oldgcc.
 779         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 780         instructions for old (<= 2.8.1) versions of gcc.
 781         * i386-tbl.h: Regenerated.
 782
 783 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 784
 785         * i386-opc.h (EVEXDYN): New.
 786         * i386-opc.tbl: Fold various AVX512VL templates.
 787         * i386-tlb.h: Re-generate.
 788
 789 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 790
 791         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 792         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 793         vpexpandd, vpexpandq): Fold AFX512VF templates.
 794         * i386-tlb.h: Re-generate.
 795
 796 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 797
 798         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 799         Fold 128- and 256-bit VEX-encoded templates.
 800         * i386-tlb.h: Re-generate.
 801
 802 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 803
 804         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 805         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 806         vpexpandd, vpexpandq): Fold AVX512F templates.
 807         * i386-tlb.h: Re-generate.
 808
 809 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 810
 811         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 812         64-bit templates. Drop Disp<N>.
 813         * i386-tlb.h: Re-generate.
 814
 815 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 816
 817         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 818         and 256-bit templates.
 819         * i386-tlb.h: Re-generate.
 820
 821 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 822
 823         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 824         * i386-tlb.h: Re-generate.
 825
 826 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 827
 828         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 829         Drop NoAVX.
 830         * i386-tlb.h: Re-generate.
 831
 832 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 833
 834         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 835         * i386-tlb.h: Re-generate.
 836
 837 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 838
 839         * i386-gen.c (opcode_modifiers): Delete FloatD.
 840         * i386-opc.h (FloatD): Delete.
 841         (struct i386_opcode_modifier): Delete floatd.
 842         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 843         FloatD by D.
 844         * i386-tlb.h: Re-generate.
 845
 846 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 847
 848         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 849
 850 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 851
 852         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 853         * i386-tlb.h: Re-generate.
 854
 855 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 856
 857         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 858         forms.
 859         * i386-tlb.h: Re-generate.
 860
 861 2018-03-07  Alan Modra  <amodra@gmail.com>
 862
 863         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 864         bfd_arch_rs6000.
 865         * disassemble.h (print_insn_rs6000): Delete.
 866         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 867         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 868         (print_insn_rs6000): Delete.
 869
 870 2018-03-03  Alan Modra  <amodra@gmail.com>
 871
 872         * sysdep.h (opcodes_error_handler): Define.
 873         (_bfd_error_handler): Declare.
 874         * Makefile.am: Remove stray #.
 875         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 876         EDIT" comment.
 877         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 878         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 879         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 880         opcodes_error_handler to print errors.  Standardize error messages.
 881         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 882         and include opintl.h.
 883         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 884         * i386-gen.c: Standardize error messages.
 885         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 886         * Makefile.in: Regenerate.
 887         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 888         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 889         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 890         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 891         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 892         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 893         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 894         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 895         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 896         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 897         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 898         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 899         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 900
 901 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 902
 903         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 904         vpsub[bwdq] instructions.
 905         * i386-tbl.h: Regenerated.
 906
 907 2018-03-01  Alan Modra  <amodra@gmail.com>
 908
 909         * configure.ac (ALL_LINGUAS): Sort.
 910         * configure: Regenerate.
 911
 912 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 913
 914         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 915         macro by assignements.
 916
 917 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 918
 919         PR gas/22871
 920         * i386-gen.c (opcode_modifiers): Add Optimize.
 921         * i386-opc.h (Optimize): New enum.
 922         (i386_opcode_modifier): Add optimize.
 923         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 924         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 925         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 926         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 927         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 928         vpxord and vpxorq.
 929         * i386-tbl.h: Regenerated.
 930
 931 2018-02-26  Alan Modra  <amodra@gmail.com>
 932
 933         * crx-dis.c (getregliststring): Allocate a large enough buffer
 934         to silence false positive gcc8 warning.
 935
 936 2018-02-22  Shea Levy <shea@shealevy.com>
 937
 938         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 939
 940 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 941
 942         * i386-opc.tbl: Add {rex},
 943         * i386-tbl.h: Regenerated.
 944
 945 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 946
 947         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 948         (mips16_opcodes): Replace `M' with `m' for "restore".
 949
 950 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 951
 952         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 953
 954 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 955
 956         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 957         variable to `function_index'.
 958
 959 2018-02-13  Nick Clifton  <nickc@redhat.com>
 960
 961         PR 22823
 962         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 963         about truncation of printing.
 964
 965 2018-02-12  Henry Wong <henry@stuffedcow.net>
 966
 967         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 968
 969 2018-02-05  Nick Clifton  <nickc@redhat.com>
 970
 971         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 972
 973 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 974
 975         * i386-dis.c (enum): Add pconfig.
 976         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 977         (cpu_flags): Add CpuPCONFIG.
 978         * i386-opc.h (enum): Add CpuPCONFIG.
 979         (i386_cpu_flags): Add cpupconfig.
 980         * i386-opc.tbl: Add PCONFIG instruction.
 981         * i386-init.h: Regenerate.
 982         * i386-tbl.h: Likewise.
 983
 984 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 985
 986         * i386-dis.c (enum): Add PREFIX_0F09.
 987         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 988         (cpu_flags): Add CpuWBNOINVD.
 989         * i386-opc.h (enum): Add CpuWBNOINVD.
 990         (i386_cpu_flags): Add cpuwbnoinvd.
 991         * i386-opc.tbl: Add WBNOINVD instruction.
 992         * i386-init.h: Regenerate.
 993         * i386-tbl.h: Likewise.
 994
 995 2018-01-17  Jim Wilson  <jimw@sifive.com>
 996
 997         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 998
 999 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1000
1001         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1002         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1003         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1004         (cpu_flags): Add CpuIBT, CpuSHSTK.
1005         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1006         (i386_cpu_flags): Add cpuibt, cpushstk.
1007         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1008         * i386-init.h: Regenerate.
1009         * i386-tbl.h: Likewise.
1010
1011 2018-01-16  Nick Clifton  <nickc@redhat.com>
1012
1013         * po/pt_BR.po: Updated Brazilian Portugese translation.
1014         * po/de.po: Updated German translation.
1015
1016 2018-01-15  Jim Wilson  <jimw@sifive.com>
1017
1018         * riscv-opc.c (match_c_nop): New.
1019         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1020
1021 2018-01-15  Nick Clifton  <nickc@redhat.com>
1022
1023         * po/uk.po: Updated Ukranian translation.
1024
1025 2018-01-13  Nick Clifton  <nickc@redhat.com>
1026
1027         * po/opcodes.pot: Regenerated.
1028
1029 2018-01-13  Nick Clifton  <nickc@redhat.com>
1030
1031         * configure: Regenerate.
1032
1033 2018-01-13  Nick Clifton  <nickc@redhat.com>
1034
1035         2.30 branch created.
1036
1037 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1038
1039         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1040         * i386-tbl.h: Regenerate.
1041
1042 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1043
1044         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1045         * i386-tbl.h: Re-generate.
1046
1047 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1048
1049         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1050         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1051         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1052         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1053         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1054         Disp8MemShift of AVX512VL forms.
1055         * i386-tbl.h: Re-generate.
1056
1057 2018-01-09  Jim Wilson  <jimw@sifive.com>
1058
1059         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1060         then the hi_addr value is zero.
1061
1062 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1063
1064         * arm-dis.c (arm_opcodes): Add csdb.
1065         (thumb32_opcodes): Add csdb.
1066
1067 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1068
1069         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1070         * aarch64-asm-2.c: Regenerate.
1071         * aarch64-dis-2.c: Regenerate.
1072         * aarch64-opc-2.c: Regenerate.
1073
1074 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1075
1076         PR gas/22681
1077         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1078         Remove AVX512 vmovd with 64-bit operands.
1079         * i386-tbl.h: Regenerated.
1080
1081 2018-01-05  Jim Wilson  <jimw@sifive.com>
1082
1083         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1084         jalr.
1085
1086 2018-01-03  Alan Modra  <amodra@gmail.com>
1087
1088         Update year range in copyright notice of all files.
1089
1090 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1091
1092         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1093         and OPERAND_TYPE_REGZMM entries.
1094
1095 For older changes see ChangeLog-2017
1096 \f
1097 Copyright (C) 2018 Free Software Foundation, Inc.
1098
1099 Copying and distribution of this file, with or without modification,
1100 are permitted in any medium without royalty provided the copyright
1101 notice and this notice are preserved.
1102
1103 Local Variables:
1104 mode: change-log
1105 left-margin: 8
1106 fill-column: 74
1107 version-control: never
1108 End: