opcodes/ChangeLog

   1 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
   2
   3         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
   4         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
   5         PREFIX_0F3ACC.
   6         (prefix_table): Updated.
   7         (three_byte_table): Likewise.
   8         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
   9         (cpu_flags): Add CpuSHA.
  10         (i386_cpu_flags): Add cpusha.
  11         * i386-init.h: Regenerate.
  12         * i386-opc.h (CpuSHA): New.
  13         (CpuUnused): Restored.
  14         (i386_cpu_flags): Add cpusha.
  15         * i386-opc.tbl: Add SHA instructions.
  16         * i386-tbl.h: Regenerate.
  17
  18 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
  19             Kirill Yukhin  <kirill.yukhin@intel.com>
  20             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
  21
  22         * i386-dis.c (BND_Fixup): New.
  23         (Ebnd): New.
  24         (Ev_bnd): New.
  25         (Gbnd): New.
  26         (BND): New.
  27         (v_bnd_mode): New.
  28         (bnd_mode): New.
  29         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
  30         MOD_0F1B_PREFIX_1.
  31         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
  32         (dis tables): Replace XX with BND for near branch and call
  33         instructions.
  34         (prefix_table): Add new entries.
  35         (mod_table): Likewise.
  36         (names_bnd): New.
  37         (intel_names_bnd): New.
  38         (att_names_bnd): New.
  39         (BND_PREFIX): New.
  40         (prefix_name): Handle BND_PREFIX.
  41         (print_insn): Initialize names_bnd.
  42         (intel_operand_size): Handle new modes.
  43         (OP_E_register): Likewise.
  44         (OP_E_memory): Likewise.
  45         (OP_G): Likewise.
  46         * i386-gen.c (cpu_flag_init): Add CpuMPX.
  47         (cpu_flags): Add CpuMPX.
  48         (operand_type_init): Add RegBND.
  49         (opcode_modifiers): Add BNDPrefixOk.
  50         (operand_types): Add RegBND.
  51         * i386-init.h: Regenerate.
  52         * i386-opc.h (CpuMPX): New.
  53         (CpuUnused): Comment out.
  54         (i386_cpu_flags): Add cpumpx.
  55         (BNDPrefixOk): New.
  56         (i386_opcode_modifier): Add bndprefixok.
  57         (RegBND): New.
  58         (i386_operand_type): Add regbnd.
  59         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
  60         Add MPX instructions and bnd prefix.
  61         * i386-reg.tbl: Add bnd0-bnd3 registers.
  62         * i386-tbl.h: Regenerate.
  63
  64 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
  65
  66         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
  67         ATTRIBUTE_UNUSED.
  68
  69 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
  70
  71         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
  72         special rules.
  73         * Makefile.in: Regenerate.
  74         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
  75         all fields.  Reformat.
  76
  77 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
  78
  79         * mips16-opc.c: Include mips-formats.h.
  80         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
  81         static arrays.
  82         (decode_mips16_operand): New function.
  83         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
  84         (print_insn_arg): Handle OP_ENTRY_EXIT list.
  85         Abort for OP_SAVE_RESTORE_LIST.
  86         (print_mips16_insn_arg): Change interface.  Use mips_operand
  87         structures.  Delete GET_OP_S.  Move GET_OP definition to...
  88         (print_insn_mips16): ...here.  Call init_print_arg_state.
  89         Update the call to print_mips16_insn_arg.
  90
  91 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
  92
  93         * mips-formats.h: New file.
  94         * mips-opc.c: Include mips-formats.h.
  95         (reg_0_map): New static array.
  96         (decode_mips_operand): New function.
  97         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
  98         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
  99         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 100         (int_c_map): New static arrays.
 101         (decode_micromips_operand): New function.
 102         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 103         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 104         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 105         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 106         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 107         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 108         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 109         (print_reg): New function.
 110         (mips_print_arg_state): New structure.
 111         (init_print_arg_state, print_insn_arg): New functions.
 112         (print_insn_args): Change interface and use mips_operand structures.
 113         Delete GET_OP_S.  Move GET_OP definition to...
 114         (print_insn_mips): ...here.  Update the call to print_insn_args.
 115         (print_insn_micromips): Use print_insn_args.
 116
 117 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 118
 119         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 120         in macros.
 121
 122 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 123
 124         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 125         ADDA.S, MULA.S and SUBA.S.
 126
 127 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 128
 129         PR gas/13572
 130         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 131         * i386-tbl.h: Regenerated.
 132
 133 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 134
 135         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 136         and SD A(B) macros up.
 137         * micromips-opc.c (micromips_opcodes): Likewise.
 138
 139 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 140
 141         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 142         instructions.
 143
 144 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 145
 146         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 147         MDMX-like instructions.
 148         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 149         printing "Q" operands for INSN_5400 instructions.
 150
 151 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 152
 153         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 154         "+S" for "cins".
 155         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 156         Combine cases.
 157
 158 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 159
 160         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 161         "jalx".
 162         * mips16-opc.c (mips16_opcodes): Likewise.
 163         * micromips-opc.c (micromips_opcodes): Likewise.
 164         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 165         (print_insn_mips16): Handle "+i".
 166         (print_insn_micromips): Likewise.  Conditionally preserve the
 167         ISA bit for "a" but not for "+i".
 168
 169 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 170
 171         * micromips-opc.c (WR_mhi): Rename to..
 172         (WR_mh): ...this.
 173         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 174         "mh,mi" with "mh".
 175         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 176         (micromips_to_32_reg_h_map1): ...this.
 177         (micromips_to_32_reg_i_map): Rename to...
 178         (micromips_to_32_reg_h_map2): ...this.
 179         (print_micromips_insn): Remove "mi" case.  Print both registers
 180         in the pair for "mh".
 181
 182 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 183
 184         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 185         * micromips-opc.c (micromips_opcodes): Likewise.
 186         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 187         and "+T" handling.  Check for a "0" suffix when deciding whether to
 188         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 189
 190 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 191
 192         * s390-opc.c (J12_12, J24_24): New macros.
 193         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 194         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 195         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 196
 197 2013-07-04  Alan Modra  <amodra@gmail.com>
 198
 199         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 200
 201 2013-06-26  Nick Clifton  <nickc@redhat.com>
 202
 203         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 204         field when checking for type 2 nop.
 205         * rx-decode.c: Regenerate.
 206
 207 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 208
 209         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 210         and "movep" macros.
 211
 212 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 213
 214         * mips-dis.c (is_mips16_plt_tail): New function.
 215         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 216         word.
 217         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 218
 219 2013-06-21  DJ Delorie  <dj@redhat.com>
 220
 221         * msp430-decode.opc: New.
 222         * msp430-decode.c: New/generated.
 223         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 224         (MAINTAINER_CLEANFILES): Likewise.
 225         Add rule to build msp430-decode.c frommsp430decode.opc
 226         using the opc2c program.
 227         * Makefile.in: Regenerate.
 228         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 229         * configure: Regenerate.
 230
 231 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 232
 233         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 234         (SYMTAB_AVAILABLE): Removed.
 235         (#include "elf/aarch64.h): Ditto.
 236
 237 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 238             Maciej W. Rozycki  <macro@codesourcery.com>
 239             Chao-Ying Fu  <fu@mips.com>
 240
 241         * micromips-opc.c (EVA): Define.
 242         (TLBINV): Define.
 243         (micromips_opcodes): Add EVA opcodes.
 244         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 245         (print_insn_args): Handle EVA offsets.
 246         (print_insn_micromips): Likewise.
 247         * mips-opc.c (EVA): Define.
 248         (TLBINV): Define.
 249         (mips_builtin_opcodes): Add EVA opcodes.
 250
 251 2013-06-17  Alan Modra  <amodra@gmail.com>
 252
 253         * Makefile.am (mips-opc.lo): Add rules to create automatic
 254         dependency files.  Pass archdefs.
 255         (micromips-opc.lo, mips16-opc.lo): Likewise.
 256         * Makefile.in: Regenerate.
 257
 258 2013-06-14  DJ Delorie  <dj@redhat.com>
 259
 260         * rx-decode.opc (rx_decode_opcode): Bit operations on
 261         registers are 32-bit operations, not 8-bit operations.
 262         * rx-decode.c: Regenerate.
 263
 264 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 265
 266         * micromips-opc.c (IVIRT): New define.
 267         (IVIRT64): New define.
 268         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 269         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 270
 271         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 272         dmtgc0 to print cp0 names.
 273
 274 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 275
 276         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 277         argument.
 278
 279 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 280             Richard Sandiford  <rdsandiford@googlemail.com>
 281
 282         * micromips-opc.c (D32, D33, MC): Update definitions.
 283         (micromips_opcodes):  Initialize ase field.
 284         * mips-dis.c (mips_arch_choice): Add ase field.
 285         (mips_arch_choices): Initialize ase field.
 286         (set_default_mips_dis_options): Declare and setup mips_ase.
 287         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 288         MT32, MC): Update definitions.
 289         (mips_builtin_opcodes): Initialize ase field.
 290
 291 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 292
 293         * s390-opc.txt (flogr): Require a register pair destination.
 294
 295 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 296
 297         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 298         instruction format.
 299
 300 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 301
 302         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 303
 304 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 305
 306         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 307         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 308         XLS_MASK, PPCVSX2): New defines.
 309         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 310         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 311         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 312         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 313         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 314         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 315         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 316         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 317         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 318         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 319         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 320         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 321         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 322         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 323         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 324         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 325         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 326         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 327         <lxvx, stxvx>: New extended mnemonics.
 328
 329 2013-05-17  Alan Modra  <amodra@gmail.com>
 330
 331         * ia64-raw.tbl: Replace non-ASCII char.
 332         * ia64-waw.tbl: Likewise.
 333         * ia64-asmtab.c: Regenerate.
 334
 335 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 336
 337         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 338         * i386-init.h: Regenerated.
 339
 340 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 341
 342         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 343         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 344         check from [0, 255] to [-128, 255].
 345
 346 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 347
 348         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 349         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 350         (parse_mips_dis_option): Handle the virt option.
 351         (print_insn_args): Handle "+J".
 352         (print_mips_disassembler_options): Print out message about virt64.
 353         * mips-opc.c (IVIRT): New define.
 354         (IVIRT64): New define.
 355         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 356         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 357         Move rfe to the bottom as it conflicts with tlbgp.
 358
 359 2013-05-09  Alan Modra  <amodra@gmail.com>
 360
 361         * ppc-opc.c (extract_vlesi): Properly sign extend.
 362         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 363
 364 2013-05-02  Nick Clifton  <nickc@redhat.com>
 365
 366         * msp430-dis.c: Add support for MSP430X instructions.
 367
 368 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 369
 370         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 371         to "eccinj".
 372
 373 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 374
 375         PR binutils/15369
 376         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 377         of CGEN_CPU_ENDIAN.
 378         (hash_insns_list): Likewise.
 379
 380 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 381
 382         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 383         warning workaround.
 384
 385 2013-04-08  Jan Beulich <jbeulich@suse.com>
 386
 387         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 388         * i386-tbl.h: Re-generate.
 389
 390 2013-04-06  David S. Miller  <davem@davemloft.net>
 391
 392         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 393         of an opcode, prefer the one with F_PREFERRED set.
 394         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 395         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 396         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 397         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 398         instructions generating condition codes, mark existing mnenomics
 399         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 400         existing mnenomics as aliases.
 401
 402 2013-04-03  Nick Clifton  <nickc@redhat.com>
 403
 404         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 405         destination address by subtracting the operand from the current
 406         address.
 407         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 408         a positive value in the insn.
 409         (extract_u16_loop): Do not negate the returned value.
 410         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 411
 412         (ceilf.sw): Remove duplicate entry.
 413         (cvtf.hs): New entry.
 414         (cvtf.sh): Likewise.
 415         (fmaf.s): Likewise.
 416         (fmsf.s): Likewise.
 417         (fnmaf.s): Likewise.
 418         (fnmsf.s): Likewise.
 419         (maddf.s): Restrict to E3V5 architectures.
 420         (msubf.s): Likewise.
 421         (nmaddf.s): Likewise.
 422         (nmsubf.s): Likewise.
 423
 424 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 425
 426         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 427         check address mode.
 428         (print_insn): Pass sizeflag to get_sib.
 429
 430 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 431
 432         PR binutils/15068
 433         * tic6x-dis.c: Add support for displaying 16-bit insns.
 434
 435 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 436
 437         PR gas/15095
 438         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 439         individual msb and lsb halves in src1 & src2 fields.  Discard the
 440         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 441         follow what Ti SDK does in that case as any value in the src1
 442         field yields the same output with SDK disassembler.
 443
 444 2013-03-12  Michael Eager <eager@eagercon.com>
 445
 446         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 447
 448 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 449
 450         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 451
 452 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 453
 454         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 455
 456 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 457
 458         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 459
 460 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 461
 462         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 463         (thumb32_opcodes): Likewise.
 464         (print_insn_thumb32): Handle 'S' control char.
 465
 466 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 467
 468         * lm32-desc.c: Regenerate.
 469
 470 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 471
 472         * i386-reg.tbl (riz): Add RegRex64.
 473         * i386-tbl.h: Regenerated.
 474
 475 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 476
 477         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 478         (aarch64_feature_crc): New static.
 479         (CRC): New macro.
 480         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 481         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 482         * aarch64-asm-2.c: Re-generate.
 483         * aarch64-dis-2.c: Ditto.
 484         * aarch64-opc-2.c: Ditto.
 485
 486 2013-02-27  Alan Modra  <amodra@gmail.com>
 487
 488         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 489         * rl78-decode.c: Regenerate.
 490
 491 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 492
 493         * rl78-decode.opc: Fix encoding of DIVWU insn.
 494         * rl78-decode.c: Regenerate.
 495
 496 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 497
 498         PR gas/15159
 499         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 500
 501         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 502         (cpu_flags): Add CpuSMAP.
 503
 504         * i386-opc.h (CpuSMAP): New.
 505         (i386_cpu_flags): Add cpusmap.
 506
 507         * i386-opc.tbl: Add clac and stac.
 508
 509         * i386-init.h: Regenerated.
 510         * i386-tbl.h: Likewise.
 511
 512 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 513
 514         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 515         which also makes the disassembler output be in little
 516         endian like it should be.
 517
 518 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 519
 520         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 521         fields to NULL.
 522         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 523
 524 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 525
 526         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 527         section disassembled.
 528
 529 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 530
 531         * arm-dis.c: Update strht pattern.
 532
 533 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 534
 535         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 536         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 537         trunc.w.s macro for EE.
 538
 539 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 540             Andrew Jenner <andrew@codesourcery.com>
 541
 542         Based on patches from Altera Corporation.
 543
 544         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 545         nios2-opc.c.
 546         * Makefile.in: Regenerated.
 547         * configure.in: Add case for bfd_nios2_arch.
 548         * configure: Regenerated.
 549         * disassemble.c (ARCH_nios2): Define.
 550         (disassembler): Add case for bfd_arch_nios2.
 551         * nios2-dis.c: New file.
 552         * nios2-opc.c: New file.
 553
 554 2013-02-04  Alan Modra  <amodra@gmail.com>
 555
 556         * po/POTFILES.in: Regenerate.
 557         * rl78-decode.c: Regenerate.
 558         * rx-decode.c: Regenerate.
 559
 560 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 561
 562         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 563         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 564         * aarch64-asm.c (convert_xtl_to_shll): New function.
 565         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 566         calling convert_xtl_to_shll.
 567         * aarch64-dis.c (convert_shll_to_xtl): New function.
 568         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 569         calling convert_shll_to_xtl.
 570         * aarch64-gen.c: Update copyright year.
 571         * aarch64-asm-2.c: Re-generate.
 572         * aarch64-dis-2.c: Re-generate.
 573         * aarch64-opc-2.c: Re-generate.
 574
 575 2013-01-24  Nick Clifton  <nickc@redhat.com>
 576
 577         * v850-dis.c: Add support for e3v5 architecture.
 578         * v850-opc.c: Likewise.
 579
 580 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 581
 582         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 583         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 584         * aarch64-opc.c (operand_general_constraint_met_p): For
 585         AARCH64_MOD_LSL, move the range check on the shift amount before the
 586         alignment check; change to call set_sft_amount_out_of_range_error
 587         instead of set_imm_out_of_range_error.
 588         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 589         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 590         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 591         SIMD_IMM_SFT.
 592
 593 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 594
 595         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 596
 597         * i386-init.h: Regenerated.
 598         * i386-tbl.h: Likewise.
 599
 600 2013-01-15  Nick Clifton  <nickc@redhat.com>
 601
 602         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 603         values.
 604         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 605
 606 2013-01-14  Will Newton <will.newton@imgtec.com>
 607
 608         * metag-dis.c (REG_WIDTH): Increase to 64.
 609
 610 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 611
 612         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 613         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 614         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 615         (SH6): Update.
 616         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 617         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 618         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 619         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 620
 621 2013-01-10  Will Newton <will.newton@imgtec.com>
 622
 623         * Makefile.am: Add Meta.
 624         * configure.in: Add Meta.
 625         * disassemble.c: Add Meta support.
 626         * metag-dis.c: New file.
 627         * Makefile.in: Regenerate.
 628         * configure: Regenerate.
 629
 630 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 631
 632         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 633         (match_opcode): Rename to cr16_match_opcode.
 634
 635 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 636
 637         * mips-dis.c: Add names for CP0 registers of r5900.
 638         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 639         instructions sq and lq.
 640         Add support for MIPS r5900 CPU.
 641         Add support for 128 bit MMI (Multimedia Instructions).
 642         Add support for EE instructions (Emotion Engine).
 643         Disable unsupported floating point instructions (64 bit and
 644         undefined compare operations).
 645         Enable instructions of MIPS ISA IV which are supported by r5900.
 646         Disable 64 bit co processor instructions.
 647         Disable 64 bit multiplication and division instructions.
 648         Disable instructions for co-processor 2 and 3, because these are
 649         not supported (preparation for later VU0 support (Vector Unit)).
 650         Disable cvt.w.s because this behaves like trunc.w.s and the
 651         correct execution can't be ensured on r5900.
 652         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 653         will confuse less developers and compilers.
 654
 655 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 656
 657         * aarch64-opc.c (aarch64_print_operand): Change to print
 658         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 659         in comment.
 660         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 661         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 662         OP_MOV_IMM_WIDE.
 663
 664 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 665
 666         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 667         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 668
 669 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 670
 671         * i386-gen.c (process_copyright): Update copyright year to 2013.
 672
 673 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 674
 675         * cr16-dis.c (match_opcode,make_instruction): Remove static
 676         declaration.
 677         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 678         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 679
 680 For older changes see ChangeLog-2012
 681 \f
 682 Copyright (C) 2013 Free Software Foundation, Inc.
 683
 684 Copying and distribution of this file, with or without modification,
 685 are permitted in any medium without royalty provided the copyright
 686 notice and this notice are preserved.
 687
 688 Local Variables:
 689 mode: change-log
 690 left-margin: 8
 691 fill-column: 74
 692 version-control: never
 693 End: