opcodes/ChangeLog

   1 2010-10-28  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
   2
   3         * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
   4
   5 2010-10-25  Chao-ying Fu  <fu@mips.com>
   6
   7         * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
   8
   9 2010-10-25  Nathan Sidwell  <nathan@codesourcery.com>
  10
  11         * tic6x-dis.c: Add attribution.
  12
  13 2010-10-22  Alan Modra  <amodra@gmail.com>
  14
  15         * Makefile.am (CLEANFILES): Add stamp-lm32.  Sort.
  16         * Makefile.in: Regenerate.
  17
  18 2010-10-18  Maciej W. Rozycki  <macro@linux-mips.org>
  19
  20         * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
  21         macros before their corresponding MIPS III hardware instructions.
  22
  23 2010-10-16  H.J. Lu  <hongjiu.lu@intel.com>
  24
  25         * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
  26
  27         * i386-init.h: Regenerated.
  28
  29 2010-10-15  Mike Frysinger  <vapier@gentoo.org>
  30
  31         * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M.
  32
  33 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
  34
  35         * i386-opc.tbl: Remove CheckRegSize from movq.
  36         * i386-tbl.h: Regenerated.
  37
  38 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
  39
  40         * i386-opc.tbl: Remove CheckRegSize from instructions with
  41         0, 1 or fixed operands.
  42         * i386-tbl.h: Regenerated.
  43
  44 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
  45
  46         * i386-gen.c (opcode_modifiers): Add CheckRegSize.
  47
  48         * i386-opc.h (CheckRegSize): New.
  49         (i386_opcode_modifier): Add checkregsize.
  50
  51         * i386-opc.tbl: Add CheckRegSize to instructions which
  52         require register size check.
  53         * i386-tbl.h: Regenerated.
  54
  55 2010-10-12  Andreas Schwab  <schwab@linux-m68k.org>
  56
  57         * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
  58
  59 2010-10-11  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  60
  61         * s390-opc.c: Make the instruction masks for the load/store on
  62         condition instructions to cover the condition code mask as well.
  63         * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
  64
  65 2010-10-11  Jan Kratochvil  <jan.kratochvil@redhat.com>
  66             Jiang Jilin  <freephp@gmail.com>
  67
  68         * Makefile.am (libopcodes_a_SOURCES): New as empty.
  69         * Makefile.in: Regenerate.
  70
  71 2010-10-09  Matt Rice  <ratmice@gmail.com>
  72
  73         * fr30-desc.h: Regenerate.
  74         * frv-desc.h: Regenerate.
  75         * ip2k-desc.h: Regenerate.
  76         * iq2000-desc.h: Regenerate.
  77         * lm32-desc.h: Regenerate.
  78         * m32c-desc.h: Regenerate.
  79         * m32r-desc.h: Regenerate.
  80         * mep-desc.h: Regenerate.
  81         * mep-opc.c: Regenerate.
  82         * mt-desc.h: Regenerate.
  83         * openrisc-desc.h: Regenerate.
  84         * xc16x-desc.h: Regenerate.
  85         * xstormy16-desc.h: Regenerate.
  86
  87 2010-10-08  Pierre Muller  <muller@ics.u-strasbg.fr>
  88
  89         Fix build with -DDEBUG=7
  90         * frv-opc.c: Regenerate.
  91         * or32-dis.c (DEBUG): Don't redefine.
  92         (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
  93         Adapt DEBUG code to some type changes throughout.
  94         * or32-opc.c (or32_extract): Likewise.
  95
  96 2010-10-07  Bernd Schmidt  <bernds@codesourcery.com>
  97
  98         * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
  99         in SPKERNEL instructions.
 100
 101 2010-10-02  H.J. Lu  <hongjiu.lu@intel.com>
 102
 103         PR binutils/12076
 104         * i386-dis.c (RMAL): Remove duplicate.
 105
 106 2010-09-30  Pierre Muller  <muller@ics.u-strasbg.fr>
 107
 108         * s390-mkopc.c (main): Exit with error 1 if sscanf fails
 109         to parse all 6 parameters.
 110
 111 2010-09-28  Pierre Muller  <muller@ics.u-strasbg.fr>
 112
 113         * s390-mkopc.c (main): Change description array size to 80.
 114         Add maximum length of 79 to description parsing.
 115
 116 2010-09-27  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 117
 118         * configure: Regenerate.
 119
 120 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 121
 122         * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
 123         (main): Recognize the new CPU string.
 124         * s390-opc.c: Add new instruction formats and masks.
 125         * s390-opc.txt: Add new z196 instructions.
 126
 127 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 128
 129         * s390-dis.c (print_insn_s390): Pick instruction with most
 130         specific mask.
 131         * s390-opc.c: Add unused bits to the insn mask.
 132         * s390-opc.txt: Reorder some instructions to prefer more recent
 133         versions.
 134
 135 2010-09-27  Tejas Belagod  <tejas.belagod@arm.com>
 136
 137         * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
 138         correction to unaligned PCs while printing comment.
 139
 140 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 141
 142         * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
 143         (thumb32_opcodes): Likewise.
 144         (banked_regname): New function.
 145         (print_insn_arm): Add Virtualization Extensions support.
 146         (print_insn_thumb32): Likewise.
 147
 148 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 149
 150         * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
 151         ARM state.
 152
 153 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 154
 155         * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
 156         (thumb32_opcodes): Likewise.
 157
 158 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 159
 160         * arm-dis.c (arm_opcodes): Add support for pldw.
 161         (thumb32_opcodes): Likewise.
 162
 163 2010-09-22  Robin Getz  <robin.getz@analog.com>
 164
 165         * bfin-dis.c (fmtconst): Cast address to 32bits.
 166
 167 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 168
 169         * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
 170
 171 2010-09-22  Robin Getz  <robin.getz@analog.com>
 172
 173         * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
 174         Reject P6/P7 to TESTSET.
 175         (decode_PushPopReg_0): Check for parallel insns.  Reject pushing
 176         SP onto the stack.
 177         (decode_PushPopMultiple_0): Check for parallel insns.  Make sure
 178         P/D fields match all the time.
 179         (decode_CCflag_0): Check for parallel insns.  Verify x/y fields
 180         are 0 for accumulator compares.
 181         (decode_CC2stat_0): Check for parallel insns.  Reject CC<op>CC.
 182         (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
 183         decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
 184         decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 185         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 186         decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
 187         insns.
 188         (decode_dagMODim_0): Verify br field for IREG ops.
 189         (decode_LDST_0): Reject preg load into same preg.
 190         (_print_insn_bfin): Handle returns for ILLEGAL decodes.
 191         (print_insn_bfin): Likewise.
 192
 193 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 194
 195         * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
 196
 197 2010-09-22  Robin Getz  <robin.getz@analog.com>
 198
 199         * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
 200
 201 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 202
 203         * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
 204
 205 2010-09-22  Robin Getz  <robin.getz@analog.com>
 206
 207         * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
 208         register values greater than 8.
 209         (IS_RESERVEDREG, allreg, mostreg): New helpers.
 210         (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
 211         (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
 212         (decode_CC2dreg_0): Check valid CC register number.
 213
 214 2010-09-22  Robin Getz  <robin.getz@analog.com>
 215
 216         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
 217
 218 2010-09-22  Robin Getz  <robin.getz@analog.com>
 219
 220         * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
 221         (reg_names): Likewise.
 222         (decode_statbits): Likewise; while reformatting to make manageable.
 223
 224 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 225
 226         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
 227         (decode_pseudoOChar_0): New function.
 228         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
 229
 230 2010-09-22  Robin Getz  <robin.getz@analog.com>
 231
 232         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
 233         LSHIFT instead of SHIFT.
 234
 235 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 236
 237         * bfin-dis.c (constant_formats): Constify the whole structure.
 238         (fmtconst): Add const to return value.
 239         (reg_names): Mark const.
 240         (decode_multfunc): Mark s0/s1 as const.
 241         (decode_macfunc): Mark a/sop as const.
 242
 243 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
 244
 245         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
 246
 247 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 248
 249         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
 250         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
 251
 252 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
 253
 254         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
 255         dlx_insn_type array.
 256
 257 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 258
 259         PR binutils/11960
 260         * i386-dis.c (sIv): New.
 261         (dis386): Replace Iq with sIv on "pushT".
 262         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
 263         (x86_64_table): Replace {T|}/{P|} with P.
 264         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
 265         (OP_sI): Update v_mode.  Remove w_mode.
 266
 267 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
 268
 269         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
 270         on E500 and E500MC.
 271
 272 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
 273
 274         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
 275         prefetchw.
 276
 277 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 278
 279         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
 280         to processor flags for PENTIUMPRO processors and later.
 281         * i386-opc.h (enum): Add CpuNop.
 282         (i386_cpu_flags): Add cpunop bit.
 283         * i386-opc.tbl: Change nop cpu_flags.
 284         * i386-init.h: Regenerated.
 285         * i386-tbl.h: Likewise.
 286
 287 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 288
 289         * i386-opc.h (enum): Fix typos in comments.
 290
 291 2010-08-06  Alan Modra  <amodra@gmail.com>
 292
 293         * disassemble.c: Formatting.
 294         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 295
 296 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 297
 298         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
 299         * i386-tbl.h: Regenerated.
 300
 301 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 302
 303         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
 304
 305         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
 306         * i386-tbl.h: Regenerated.
 307
 308 2010-07-29  DJ Delorie  <dj@redhat.com>
 309
 310         * rx-decode.opc (SRR): New.
 311         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
 312         r0,r0) and NOP3 (max r0,r0) special cases.
 313         * rx-decode.c: Regenerate.
 314
 315 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
 316
 317         * i386-dis.c: Add 0F to VEX opcode enums.
 318
 319 2010-07-27  DJ Delorie  <dj@redhat.com>
 320
 321         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
 322         (rx_decode_opcode): Likewise.
 323         * rx-decode.c: Regenerate.
 324
 325 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 326             Ina Pandit  <ina.pandit@kpitcummins.com>
 327
 328         * v850-dis.c (v850_sreg_names): Updated structure for system
 329         registers.
 330         (float_cc_names): new structure for condition codes.
 331         (print_value): Update the function that prints value.
 332         (get_operand_value): New function to get the operand value.
 333         (disassemble): Updated to handle the disassembly of instructions.
 334         (print_insn_v850): Updated function to print instruction for different
 335         families.
 336         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 337         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 338         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 339         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 340         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 341         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 342         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 343         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 344         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 345         (v850_operands): Update with the relocation name. Also update
 346         the instructions with specific set of processors.
 347
 348 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 349
 350         * arm-dis.c (print_insn_arm): Add cases for printing more
 351         symbolic operands.
 352         (print_insn_thumb32): Likewise.
 353
 354 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 355
 356         * mips-dis.c (print_insn_mips): Correct branch instruction type
 357         determination.
 358
 359 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 360
 361         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 362         type and delay slot determination.
 363         (print_insn_mips16): Extend branch instruction type and delay
 364         slot determination to cover all instructions.
 365         * mips16-opc.c (BR): Remove macro.
 366         (UBR, CBR): New macros.
 367         (mips16_opcodes): Update branch annotation for "b", "beqz",
 368         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 369         and "jrc".
 370
 371 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 372
 373         AVX Programming Reference (June, 2010)
 374         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 375         * i386-opc.tbl: Likewise.
 376         * i386-tbl.h: Regenerated.
 377
 378 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 379
 380         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 381
 382 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 383
 384         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 385         ppc_cpu_t before inverting.
 386         (ppc_parse_cpu): Likewise.
 387         (print_insn_powerpc): Likewise.
 388
 389 2010-07-03  Alan Modra  <amodra@gmail.com>
 390
 391         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 392         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 393         (PPC64, MFDEC2): Update.
 394         (NON32, NO371): Define.
 395         (powerpc_opcode): Update to not use old opcode flags, and avoid
 396         -m601 duplicates.
 397
 398 2010-07-03  DJ Delorie  <dj@delorie.com>
 399
 400         * m32c-ibld.c: Regenerate.
 401
 402 2010-07-03  Alan Modra  <amodra@gmail.com>
 403
 404         * ppc-opc.c (PWR2COM): Define.
 405         (PPCPWR2): Add PPC_OPCODE_COMMON.
 406         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 407         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 408         "rac" from -mcom.
 409
 410 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 411
 412         AVX Programming Reference (June, 2010)
 413         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 414         (PREFIX_0FAE_REG_1): Likewise.
 415         (PREFIX_0FAE_REG_2): Likewise.
 416         (PREFIX_0FAE_REG_3): Likewise.
 417         (PREFIX_VEX_3813): Likewise.
 418         (PREFIX_VEX_3A1D): Likewise.
 419         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 420         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 421         PREFIX_VEX_3A1D.
 422         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 423         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 424         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 425
 426         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 427         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 428         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 429
 430         * i386-opc.h (CpuXsaveopt): New.
 431         (CpuFSGSBase): Likewise.
 432         (CpuRdRnd): Likewise.
 433         (CpuF16C): Likewise.
 434         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 435         cpuf16c.
 436
 437         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 438         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 439         * i386-init.h: Regenerated.
 440         * i386-tbl.h: Likewise.
 441
 442 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 443
 444         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 445         and mtocrf on EFS.
 446
 447 2010-06-29  Alan Modra  <amodra@gmail.com>
 448
 449         * maxq-dis.c: Delete file.
 450         * Makefile.am: Remove references to maxq.
 451         * configure.in: Likewise.
 452         * disassemble.c: Likewise.
 453         * Makefile.in: Regenerate.
 454         * configure: Regenerate.
 455         * po/POTFILES.in: Regenerate.
 456
 457 2010-06-29  Alan Modra  <amodra@gmail.com>
 458
 459         * mep-dis.c: Regenerate.
 460
 461 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 462
 463         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 464
 465 2010-06-27  Alan Modra  <amodra@gmail.com>
 466
 467         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 468         (decodeInstr): Likewise.
 469         * dlx-dis.c (print_insn_dlx): Likewise.
 470         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 471         * maxq-dis.c (check_move, print_insn): Likewise.
 472         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 473         * msp430-dis.c (msp430_branchinstr): Likewise.
 474         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 475         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 476         * sparc-dis.c (print_insn_sparc): Likewise.
 477         * fr30-asm.c: Regenerate.
 478         * frv-asm.c: Regenerate.
 479         * ip2k-asm.c: Regenerate.
 480         * iq2000-asm.c: Regenerate.
 481         * lm32-asm.c: Regenerate.
 482         * m32c-asm.c: Regenerate.
 483         * m32r-asm.c: Regenerate.
 484         * mep-asm.c: Regenerate.
 485         * mt-asm.c: Regenerate.
 486         * openrisc-asm.c: Regenerate.
 487         * xc16x-asm.c: Regenerate.
 488         * xstormy16-asm.c: Regenerate.
 489
 490 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 491
 492         PR gas/11673
 493         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 494
 495 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 496
 497         PR binutils/11676
 498         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 499
 500 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 501
 502         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 503         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 504         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 505         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 506         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 507         Treat lwsync as msync on e500.
 508
 509 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 510
 511         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 512
 513 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 514
 515         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 516         constants is the same on 32-bit and 64-bit hosts.
 517
 518 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 519
 520         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 521         .short directives so that they can be reassembled.
 522
 523 2010-05-26  Catherine Moore <clm@codesourcery.com>
 524             David Ung  <davidu@mips.com>
 525
 526         * mips-opc.c: Change membership to I1 for instructions ssnop and
 527         ehb.
 528
 529 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 530
 531         * i386-dis.c (sib): New.
 532         (get_sib): Likewise.
 533         (print_insn): Call get_sib.
 534         OP_E_memory): Use sib.
 535
 536 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 537
 538         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 539         * mips-opc.c (I16): Remove.
 540         (mips_builtin_op): Reclassify jalx.
 541
 542 2010-05-19  Alan Modra  <amodra@gmail.com>
 543
 544         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 545         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 546
 547 2010-05-13  Alan Modra  <amodra@gmail.com>
 548
 549         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 550
 551 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 552
 553         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 554         format.
 555         (print_insn_thumb16): Add support for new %W format.
 556
 557 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 558
 559         * Makefile.in: Regenerate with automake 1.11.1.
 560         * aclocal.m4: Ditto.
 561
 562 2010-05-05  Nick Clifton  <nickc@redhat.com>
 563
 564         * po/es.po: Updated Spanish translation.
 565
 566 2010-04-22  Nick Clifton  <nickc@redhat.com>
 567
 568         * po/opcodes.pot: Updated by the Translation project.
 569         * po/vi.po: Updated Vietnamese translation.
 570
 571 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 572
 573         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 574         bits in opcode.
 575
 576 2010-04-09  Nick Clifton  <nickc@redhat.com>
 577
 578         * i386-dis.c (print_insn): Remove unused variable op.
 579         (OP_sI): Remove unused variable mask.
 580
 581 2010-04-07  Alan Modra  <amodra@gmail.com>
 582
 583         * configure: Regenerate.
 584
 585 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 586
 587         * ppc-opc.c (RBOPT): New define.
 588         ("dccci"): Enable for PPCA2.  Make operands optional.
 589         ("iccci"): Likewise.  Do not deprecate for PPC476.
 590
 591 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 592
 593         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 594
 595 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 596
 597         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 598         * Makefile.in: Regenerate.
 599         * configure.in (bfd_tic6x_arch): New.
 600         * configure: Regenerate.
 601         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 602         (disassembler): Handle TI C6X.
 603         * tic6x-dis.c: New.
 604
 605 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 606
 607         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 608
 609 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 610
 611         * dis-buf.c (buffer_read_memory): Give error for reading just
 612         before the start of memory.
 613
 614 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 615             Quentin Neill <quentin.neill@amd.com>
 616
 617         * i386-dis.c (OP_LWP_I): Removed.
 618         (reg_table): Do not use OP_LWP_I, use Iq.
 619         (OP_LWPCB_E): Remove use of names16.
 620         (OP_LWP_E): Same.
 621         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 622         should not set the Vex.length bit.
 623         * i386-tbl.h: Regenerated.
 624
 625 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 626
 627         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 628
 629 2010-02-24  Nick Clifton  <nickc@redhat.com>
 630
 631         PR binutils/6773
 632         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 633         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 634         (thumb32_opcodes): Likewise.
 635
 636 2010-02-15  Nick Clifton  <nickc@redhat.com>
 637
 638         * po/vi.po: Updated Vietnamese translation.
 639
 640 2010-02-12  Doug Evans  <dje@sebabeach.org>
 641
 642         * lm32-opinst.c: Regenerate.
 643
 644 2010-02-11  Doug Evans  <dje@sebabeach.org>
 645
 646         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 647         (print_address): Delete CGEN_PRINT_ADDRESS.
 648         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 649         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 650         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 651         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 652
 653         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 654         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 655         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 656         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 657         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 658         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 659         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 660         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 661         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 662         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 663         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 664         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 665
 666 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 667
 668         * i386-dis.c: Update copyright.
 669         * i386-gen.c: Likewise.
 670         * i386-opc.h: Likewise.
 671         * i386-opc.tbl: Likewise.
 672
 673 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 674             Sebastian Pop  <sebastian.pop@amd.com>
 675
 676         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 677         function to handle 5th imm8 operand.
 678         (PREFIX_VEX_3A48): Added.
 679         (PREFIX_VEX_3A49): Added.
 680         (VEX_W_3A48_P_2): Added.
 681         (VEX_W_3A49_P_2): Added.
 682         (prefix table): Added entries for PREFIX_VEX_3A48
 683         and PREFIX_VEX_3A49.
 684         (vex table): Added entries for VEX_W_3A48_P_2 and
 685         and VEX_W_3A49_P_2.
 686         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 687         for Vec_Imm4 operands.
 688         * i386-opc.h (enum): Added Vec_Imm4.
 689         (i386_operand_type): Added vec_imm4.
 690         * i386-opc.tbl: Add entries for vpermilp[ds].
 691         * i386-init.h: Regenerated.
 692         * i386-tbl.h: Regenerated.
 693
 694 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 695
 696         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 697         and "pwr7".  Move "a2" into alphabetical order.
 698
 699 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 700
 701         * ppc-dis.c (ppc_opts): Add titan entry.
 702         * ppc-opc.c (TITAN, MULHW): Define.
 703         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 704
 705 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 706
 707         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 708         to CPU_BDVER1_FLAGS
 709         * i386-init.h: Regenerated.
 710
 711 2010-02-03  Anthony Green  <green@moxielogic.com>
 712
 713         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 714         0x0f, and make 0x00 an illegal instruction.
 715
 716 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 717
 718         * opcodes/arm-dis.c (struct arm_private_data): New.
 719         (print_insn_coprocessor, print_insn_arm): Update to use struct
 720         arm_private_data.
 721         (is_mapping_symbol, get_map_sym_type): New functions.
 722         (get_sym_code_type): Check the symbol's section.  Do not check
 723         mapping symbols.
 724         (print_insn): Default to disassembling ARM mode code.  Check
 725         for mapping symbols separately from other symbols.  Use
 726         struct arm_private_data.
 727
 728 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 729
 730         * i386-dis.c (EXVexWdqScalar): New.
 731         (vex_scalar_w_dq_mode): Likewise.
 732         (prefix_table): Update entries for PREFIX_VEX_3899,
 733         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 734         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 735         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 736         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 737         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 738         (OP_EX): Likewise.
 739
 740 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 741
 742         * i386-dis.c (XMScalar): New.
 743         (EXdScalar): Likewise.
 744         (EXqScalar): Likewise.
 745         (EXqScalarS): Likewise.
 746         (VexScalar): Likewise.
 747         (EXdVexScalarS): Likewise.
 748         (EXqVexScalarS): Likewise.
 749         (XMVexScalar): Likewise.
 750         (scalar_mode): Likewise.
 751         (d_scalar_mode): Likewise.
 752         (d_scalar_swap_mode): Likewise.
 753         (q_scalar_mode): Likewise.
 754         (q_scalar_swap_mode): Likewise.
 755         (vex_scalar_mode): Likewise.
 756         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 757         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 758         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 759         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 760         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 761         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 762         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 763         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 764         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 765         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 766         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 767         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 768         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 769         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 770         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 771         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 772         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 773         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 774         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 775         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 776         q_scalar_mode, q_scalar_swap_mode.
 777         (OP_XMM): Handle scalar_mode.
 778         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 779         and q_scalar_swap_mode.
 780         (OP_VEX): Handle vex_scalar_mode.
 781
 782 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 783
 784         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 785
 786 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 787
 788         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 789
 790 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 791
 792         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 793
 794 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 795
 796         * i386-dis.c (Bad_Opcode): New.
 797         (bad_opcode): Likewise.
 798         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 799         (dis386_twobyte): Likewise.
 800         (reg_table): Likewise.
 801         (prefix_table): Likewise.
 802         (x86_64_table): Likewise.
 803         (vex_len_table): Likewise.
 804         (vex_w_table): Likewise.
 805         (mod_table): Likewise.
 806         (rm_table): Likewise.
 807         (float_reg): Likewise.
 808         (reg_table): Remove trailing "(bad)" entries.
 809         (prefix_table): Likewise.
 810         (x86_64_table): Likewise.
 811         (vex_len_table): Likewise.
 812         (vex_w_table): Likewise.
 813         (mod_table): Likewise.
 814         (rm_table): Likewise.
 815         (get_valid_dis386): Handle bytemode 0.
 816
 817 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 818
 819         * i386-opc.h (VEXScalar): New.
 820
 821         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 822         instructions.
 823         * i386-tbl.h: Regenerated.
 824
 825 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 826
 827         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 828
 829         * i386-opc.tbl: Add xsave64 and xrstor64.
 830         * i386-tbl.h: Regenerated.
 831
 832 2010-01-20  Nick Clifton  <nickc@redhat.com>
 833
 834         PR 11170
 835         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 836         based post-indexed addressing.
 837
 838 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 839
 840         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 841         * i386-tbl.h: Regenerated.
 842
 843 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 844
 845         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 846         comments.
 847
 848 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 849
 850         * i386-dis.c (names_mm): New.
 851         (intel_names_mm): Likewise.
 852         (att_names_mm): Likewise.
 853         (names_xmm): Likewise.
 854         (intel_names_xmm): Likewise.
 855         (att_names_xmm): Likewise.
 856         (names_ymm): Likewise.
 857         (intel_names_ymm): Likewise.
 858         (att_names_ymm): Likewise.
 859         (print_insn): Set names_mm, names_xmm and names_ymm.
 860         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 861         (OP_XMM): Likewise.
 862         (OP_EM): Likewise.
 863         (OP_EMC): Likewise.
 864         (OP_MXC): Likewise.
 865         (OP_EX): Likewise.
 866         (XMM_Fixup): Likewise.
 867         (OP_VEX): Likewise.
 868         (OP_EX_VexReg): Likewise.
 869         (OP_Vex_2src): Likewise.
 870         (OP_Vex_2src_1): Likewise.
 871         (OP_Vex_2src_2): Likewise.
 872         (OP_REG_VexI4): Likewise.
 873
 874 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 875
 876         * i386-dis.c (print_insn): Update comments.
 877
 878 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 879
 880         * i386-dis.c (rex_original): Removed.
 881         (ckprefix): Remove rex_original.
 882         (print_insn): Update comments.
 883
 884 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 885
 886         * Makefile.in: Regenerate.
 887         * configure: Regenerate.
 888
 889 2010-01-07  Doug Evans  <dje@sebabeach.org>
 890
 891         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 892         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 893         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 894         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 895         * xstormy16-ibld.c: Regenerate.
 896
 897 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 898
 899         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 900         * i386-init.h: Regenerated.
 901
 902 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 903
 904         * arm-dis.c (print_insn): Fixed search for next symbol and data
 905         dumping condition, and the initial mapping symbol state.
 906
 907 2010-01-05  Doug Evans  <dje@sebabeach.org>
 908
 909         * cgen-ibld.in: #include "cgen/basic-modes.h".
 910         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 911         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 912         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 913         * xstormy16-ibld.c: Regenerate.
 914
 915 2010-01-04  Nick Clifton  <nickc@redhat.com>
 916
 917         PR 11123
 918         * arm-dis.c (print_insn_coprocessor): Initialise value.
 919
 920 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 921
 922         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 923
 924 2010-01-02  Doug Evans  <dje@sebabeach.org>
 925
 926         * cgen-asm.in: Update copyright year.
 927         * cgen-dis.in: Update copyright year.
 928         * cgen-ibld.in: Update copyright year.
 929         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 930         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 931         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 932         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 933         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 934         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 935         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 936         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 937         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 938         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 939         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 940         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 941         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 942         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 943         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 944         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 945         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 946         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 947         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 948         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 949         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 950
 951 For older changes see ChangeLog-2009
 952 \f
 953 Local Variables:
 954 mode: change-log
 955 left-margin: 8
 956 fill-column: 74
 957 version-control: never
 958 End: