1 2013-11-08 H.J. Lu <hongjiu.lu@intel.com>
4 * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
5 * i386-init.h: Regenerated.
7 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
9 * aarch64-opc.c (F_DEPRECATED): New macro.
10 (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
12 (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
15 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
17 * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
18 (convert_from_csel): Likewise.
19 * aarch64-opc.c (operand_general_constraint_met_p): Handle
20 AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
21 (aarch64_print_operand): Handle AARCH64_OPND_COND1.
22 * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
23 COND for cinc, cset, cinv, csetm and cneg.
24 (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
25 * aarch64-asm-2.c: Re-generated.
26 * aarch64-dis-2.c: Ditto.
27 * aarch64-opc-2.c: Ditto.
29 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
31 * aarch64-opc.c (set_syntax_error): New function.
32 (operand_general_constraint_met_p): Replace set_other_error
33 with set_syntax_error.
35 2013-10-30 Andreas Arnez <arnez@linux.vnet.ibm.com>
37 * s390-dis.c (init_disasm): Default to full 'zarch' opcode
38 availability even for 31-bit programs.
40 2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
42 * arm-dis.c (neon_opcodes): Adjust print string for vshll.
44 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
46 * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
47 +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
48 +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
51 (micromips_opcodes): Add MSA instructions.
52 * mips-dis.c (msa_control_names): New array.
53 (mips_abi_choice): Add ASE_MSA to mips32r2.
54 Remove ASE_MDMX from mips64r2.
55 Add ASE_MSA and ASE_MSA64 to mips64r2.
56 (parse_mips_dis_option): Handle -Mmsa.
57 (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
58 (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
59 (print_mips_disassembler_options): Print -Mmsa.
60 * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
61 +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
64 (mips_builtin_op): Add MSA instructions.
66 2013-10-13 Sandra Loosemore <sandra@codesourcery.com>
68 * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
69 as the primary name of r30.
71 2013-10-12 Jan Beulich <jbeulich@suse.com>
73 * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
75 (OP_E_register): Move v_bnd_mode alongside m_mode.
76 * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
77 Drop Reg16 and Disp16. Add NoRex64.
78 (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
79 * i386-tbl.h: Re-generate.
81 2013-10-10 Sean Keys <skeys@ipdatasys.com>
83 * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
85 * xgate-dis.c (print_insn): Refactor to work with table change.
87 2013-10-10 Roland McGrath <mcgrathr@google.com>
89 * i386-dis.c (oappend_maybe_intel): New function.
90 (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
91 (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
92 (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
94 * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
95 possible compiler warnings when the union's initializer is
96 actually meant for the 'preg' enum typed member.
97 * crx-opc.c (REG): Likewise.
99 * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
100 Remove duplicate const qualifier.
102 2013-10-08 Jan Beulich <jbeulich@suse.com>
104 * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
105 (clflush): Use Anysize instead of Byte|Unspecified.
106 (prefetch*): Likewise.
107 * i386-tbl.h: Re-generate.
109 2013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
111 * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
113 2013-09-30 H.J. Lu <hongjiu.lu@intel.com>
115 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
116 * i386-init.h: Regenerated.
118 2013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
120 * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
121 * i386-init.h: Regenerated.
123 2013-09-20 Alan Modra <amodra@gmail.com>
125 * configure: Regenerate.
127 2013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
129 * s390-opc.txt (clih): Make the immediate unsigned.
131 2013-09-04 Roland McGrath <mcgrathr@google.com>
134 * arm-dis.c (arm_opcodes): Add udf.
135 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
136 (thumb32_opcodes): Add udf.w.
137 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
139 2013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
141 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
142 For the load fp integer instructions only the suppression flag was
143 new with z196 version.
145 2013-08-28 Nick Clifton <nickc@redhat.com>
147 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
148 immediate is not suitable for the 32-bit ABI.
150 2013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
152 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
155 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
158 * aarch64-asm.c: Fix typos.
159 * aarch64-dis.c: Likewise.
160 * msp430-dis.c: Likewise.
162 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
164 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
165 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
166 Use +H rather than +C for the real "dext".
167 * mips-opc.c (mips_builtin_opcodes): Likewise.
169 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
171 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
172 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
173 and OPTIONAL_MAPPED_REG.
174 * mips-opc.c (decode_mips_operand): Likewise.
175 * mips16-opc.c (decode_mips16_operand): Likewise.
176 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
178 2013-08-19 H.J. Lu <hongjiu.lu@intel.com>
180 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
181 (PREFIX_EVEX_0F3A3F): Likewise.
182 * i386-dis-evex.h (evex_table): Updated.
184 2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
186 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
189 2013-08-05 Eric Botcazou <ebotcazou@adacore.com>
190 Konrad Eisele <konrad@gaisler.com>
192 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
194 * sparc-opc.c (MASK_LEON): Define.
195 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
196 (letandleon): New macro.
197 (v9andleon): Likewise.
198 (sparc_opc): Add leon.
199 (umac): Enable for letandleon.
201 (casa): Enable for v9andleon.
205 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
206 Richard Sandiford <rdsandiford@googlemail.com>
208 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
209 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
210 (print_vu0_channel): New function.
211 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
212 (print_insn_args): Handle '#'.
213 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
214 * mips-opc.c (mips_vu0_channel_mask): New constant.
215 (decode_mips_operand): Handle new VU0 operand types.
216 (VU0, VU0CH): New macros.
217 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
218 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
219 Use "+6" rather than "G" for QMFC2 and QMTC2.
221 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
223 * mips-formats.h (PCREL): Reorder parameters and update the definition
224 to match new mips_pcrel_operand layout.
225 (JUMP, JALX, BRANCH): Update accordingly.
226 * mips16-opc.c (decode_mips16_operand): Likewise.
228 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
230 * micromips-opc.c (WR_s): Delete.
232 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
234 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
236 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
237 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
238 (mips_builtin_opcodes): Use the new position-based read-write flags
239 instead of field-based ones. Use UDI for "udi..." instructions.
240 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
242 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
243 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
244 (WR_SP, RD_16): New macros.
245 (RD_SP): Redefine as an INSN2_* flag.
246 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
247 (mips16_opcodes): Use the new position-based read-write flags
248 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
250 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
252 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
253 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
254 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
255 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
256 (micromips_opcodes): Use the new position-based read-write flags
257 instead of field-based ones.
258 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
259 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
260 of field-based flags.
262 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
264 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
265 (WR_SP): Replace with...
267 (mips16_opcodes): Update accordingly.
268 * mips-dis.c (print_insn_mips16): Likewise.
270 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
272 * mips16-opc.c (mips16_opcodes): Reformat.
274 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
276 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
277 for operands that are hard-coded to $0.
278 * micromips-opc.c (micromips_opcodes): Likewise.
280 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
282 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
283 for the single-operand forms of JALR and JALR.HB.
284 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
287 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
289 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
290 instructions. Fix them to use WR_MACC instead of WR_CC and
291 add missing RD_MACCs.
293 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
295 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
297 2013-07-29 Peter Bergner <bergner@vnet.ibm.com>
299 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
301 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
302 Alexander Ivchenko <alexander.ivchenko@intel.com>
303 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
304 Sergey Lega <sergey.s.lega@intel.com>
305 Anna Tikhonova <anna.tikhonova@intel.com>
306 Ilya Tocar <ilya.tocar@intel.com>
307 Andrey Turetskiy <andrey.turetskiy@intel.com>
308 Ilya Verbin <ilya.verbin@intel.com>
309 Kirill Yukhin <kirill.yukhin@intel.com>
310 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
312 * i386-dis-evex.h: New.
313 * i386-dis.c (OP_Rounding): New.
320 (EXEvexHalfBcstXmmq): New.
323 (EXEvexXNoBcst): New.
332 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
333 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
334 evex_rounding_mode, evex_sae_mode, mask_mode.
335 (USE_EVEX_TABLE): New.
338 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
340 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
341 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
342 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
343 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
344 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
345 MOD_EVEX_0F38C7_REG_6.
346 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
347 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
348 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
349 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
350 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
351 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
352 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
353 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
354 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
355 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
356 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
357 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
358 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
359 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
360 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
361 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
362 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
363 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
364 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
365 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
366 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
367 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
368 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
369 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
370 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
371 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
372 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
373 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
374 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
375 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
376 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
377 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
378 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
379 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
380 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
381 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
382 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
383 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
384 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
385 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
386 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
387 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
388 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
389 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
390 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
391 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
392 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
393 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
394 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
395 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
396 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
397 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
398 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
399 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
400 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
401 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
402 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
403 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
404 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
405 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
406 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
407 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
408 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
409 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
410 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
411 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
412 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
413 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
414 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
415 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
416 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
417 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
418 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
419 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
420 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
421 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
423 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
424 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
425 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
426 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
427 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
428 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
429 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
430 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
431 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
432 VEX_W_0F3A32_P_2_LEN_0.
433 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
434 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
435 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
436 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
437 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
438 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
439 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
440 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
441 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
442 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
443 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
444 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
445 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
446 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
447 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
448 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
449 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
450 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
451 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
452 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
453 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
454 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
455 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
456 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
457 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
458 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
459 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
460 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
461 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
462 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
463 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
464 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
465 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
466 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
467 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
468 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
469 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
470 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
471 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
472 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
473 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
474 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
475 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
476 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
477 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
478 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
479 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
480 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
481 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
482 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
483 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
484 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
485 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
486 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
487 (struct vex): Add fields evex, r, v, mask_register_specifier,
489 (intel_names_xmm): Add upper 16 registers.
490 (att_names_xmm): Ditto.
491 (intel_names_ymm): Ditto.
492 (att_names_ymm): Ditto.
494 (intel_names_zmm): Ditto.
495 (att_names_zmm): Ditto.
497 (intel_names_mask): Ditto.
498 (att_names_mask): Ditto.
499 (names_rounding): Ditto.
500 (names_broadcast): Ditto.
501 (x86_64_table): Add escape to evex-table.
502 (reg_table): Include reg_table evex-entries from
503 i386-dis-evex.h. Fix prefetchwt1 instruction.
504 (prefix_table): Add entries for new instructions.
506 (vex_len_table): Ditto.
507 (vex_w_table): Ditto.
509 (get_valid_dis386): Properly handle new instructions.
510 (print_insn): Handle zmm and mask registers, print mask operand.
511 (intel_operand_size): Support EVEX, new modes and sizes.
512 (OP_E_register): Handle new modes.
513 (OP_E_memory): Ditto.
518 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
519 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
520 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
521 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
522 CpuAVX512PF and CpuVREX.
523 (operand_type_init): Add OPERAND_TYPE_REGZMM,
524 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
525 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
526 StaticRounding, SAE, Disp8MemShift, NoDefMask.
527 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
528 * i386-init.h: Regenerate.
529 * i386-opc.h (CpuAVX512F): New.
534 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
535 cpuavx512pf and cpuvrex fields.
536 (VecSIB): Add VecSIB512.
541 (StaticRounding): New.
543 (Disp8MemShift): New.
545 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
546 staticrounding, sae, disp8memshift and nodefmask.
550 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
553 * i386-opc.tbl: Add AVX512 instructions.
554 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
555 registers, mask registers.
556 * i386-tbl.h: Regenerate.
558 2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
561 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
562 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
564 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
566 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
567 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
569 (prefix_table): Updated.
570 (three_byte_table): Likewise.
571 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
572 (cpu_flags): Add CpuSHA.
573 (i386_cpu_flags): Add cpusha.
574 * i386-init.h: Regenerate.
575 * i386-opc.h (CpuSHA): New.
576 (CpuUnused): Restored.
577 (i386_cpu_flags): Add cpusha.
578 * i386-opc.tbl: Add SHA instructions.
579 * i386-tbl.h: Regenerate.
581 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
582 Kirill Yukhin <kirill.yukhin@intel.com>
583 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
585 * i386-dis.c (BND_Fixup): New.
592 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
594 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
595 (dis tables): Replace XX with BND for near branch and call
597 (prefix_table): Add new entries.
598 (mod_table): Likewise.
600 (intel_names_bnd): New.
601 (att_names_bnd): New.
603 (prefix_name): Handle BND_PREFIX.
604 (print_insn): Initialize names_bnd.
605 (intel_operand_size): Handle new modes.
606 (OP_E_register): Likewise.
607 (OP_E_memory): Likewise.
609 * i386-gen.c (cpu_flag_init): Add CpuMPX.
610 (cpu_flags): Add CpuMPX.
611 (operand_type_init): Add RegBND.
612 (opcode_modifiers): Add BNDPrefixOk.
613 (operand_types): Add RegBND.
614 * i386-init.h: Regenerate.
615 * i386-opc.h (CpuMPX): New.
616 (CpuUnused): Comment out.
617 (i386_cpu_flags): Add cpumpx.
619 (i386_opcode_modifier): Add bndprefixok.
621 (i386_operand_type): Add regbnd.
622 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
623 Add MPX instructions and bnd prefix.
624 * i386-reg.tbl: Add bnd0-bnd3 registers.
625 * i386-tbl.h: Regenerate.
627 2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
629 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
632 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
634 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
636 * Makefile.in: Regenerate.
637 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
638 all fields. Reformat.
640 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
642 * mips16-opc.c: Include mips-formats.h.
643 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
645 (decode_mips16_operand): New function.
646 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
647 (print_insn_arg): Handle OP_ENTRY_EXIT list.
648 Abort for OP_SAVE_RESTORE_LIST.
649 (print_mips16_insn_arg): Change interface. Use mips_operand
650 structures. Delete GET_OP_S. Move GET_OP definition to...
651 (print_insn_mips16): ...here. Call init_print_arg_state.
652 Update the call to print_mips16_insn_arg.
654 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
656 * mips-formats.h: New file.
657 * mips-opc.c: Include mips-formats.h.
658 (reg_0_map): New static array.
659 (decode_mips_operand): New function.
660 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
661 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
662 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
663 (int_c_map): New static arrays.
664 (decode_micromips_operand): New function.
665 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
666 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
667 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
668 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
669 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
670 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
671 (micromips_imm_b_map, micromips_imm_c_map): Delete.
672 (print_reg): New function.
673 (mips_print_arg_state): New structure.
674 (init_print_arg_state, print_insn_arg): New functions.
675 (print_insn_args): Change interface and use mips_operand structures.
676 Delete GET_OP_S. Move GET_OP definition to...
677 (print_insn_mips): ...here. Update the call to print_insn_args.
678 (print_insn_micromips): Use print_insn_args.
680 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
682 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
685 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
687 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
688 ADDA.S, MULA.S and SUBA.S.
690 2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
693 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
694 * i386-tbl.h: Regenerated.
696 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
698 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
699 and SD A(B) macros up.
700 * micromips-opc.c (micromips_opcodes): Likewise.
702 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
704 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
707 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
709 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
710 MDMX-like instructions.
711 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
712 printing "Q" operands for INSN_5400 instructions.
714 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
716 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
718 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
721 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
723 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
725 * mips16-opc.c (mips16_opcodes): Likewise.
726 * micromips-opc.c (micromips_opcodes): Likewise.
727 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
728 (print_insn_mips16): Handle "+i".
729 (print_insn_micromips): Likewise. Conditionally preserve the
730 ISA bit for "a" but not for "+i".
732 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
734 * micromips-opc.c (WR_mhi): Rename to..
736 (micromips_opcodes): Update "movep" entry accordingly. Replace
738 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
739 (micromips_to_32_reg_h_map1): ...this.
740 (micromips_to_32_reg_i_map): Rename to...
741 (micromips_to_32_reg_h_map2): ...this.
742 (print_micromips_insn): Remove "mi" case. Print both registers
743 in the pair for "mh".
745 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
747 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
748 * micromips-opc.c (micromips_opcodes): Likewise.
749 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
750 and "+T" handling. Check for a "0" suffix when deciding whether to
751 use coprocessor 0 names. In that case, also check for ",H" selectors.
753 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
755 * s390-opc.c (J12_12, J24_24): New macros.
756 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
757 (MASK_MII_UPI): Rename to MASK_MII_UPP.
758 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
760 2013-07-04 Alan Modra <amodra@gmail.com>
762 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
764 2013-06-26 Nick Clifton <nickc@redhat.com>
766 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
767 field when checking for type 2 nop.
768 * rx-decode.c: Regenerate.
770 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
772 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
775 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
777 * mips-dis.c (is_mips16_plt_tail): New function.
778 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
780 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
782 2013-06-21 DJ Delorie <dj@redhat.com>
784 * msp430-decode.opc: New.
785 * msp430-decode.c: New/generated.
786 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
787 (MAINTAINER_CLEANFILES): Likewise.
788 Add rule to build msp430-decode.c frommsp430decode.opc
789 using the opc2c program.
790 * Makefile.in: Regenerate.
791 * configure.in: Add msp430-decode.lo to msp430 architecture files.
792 * configure: Regenerate.
794 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
796 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
797 (SYMTAB_AVAILABLE): Removed.
798 (#include "elf/aarch64.h): Ditto.
800 2013-06-17 Catherine Moore <clm@codesourcery.com>
801 Maciej W. Rozycki <macro@codesourcery.com>
802 Chao-Ying Fu <fu@mips.com>
804 * micromips-opc.c (EVA): Define.
806 (micromips_opcodes): Add EVA opcodes.
807 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
808 (print_insn_args): Handle EVA offsets.
809 (print_insn_micromips): Likewise.
810 * mips-opc.c (EVA): Define.
812 (mips_builtin_opcodes): Add EVA opcodes.
814 2013-06-17 Alan Modra <amodra@gmail.com>
816 * Makefile.am (mips-opc.lo): Add rules to create automatic
817 dependency files. Pass archdefs.
818 (micromips-opc.lo, mips16-opc.lo): Likewise.
819 * Makefile.in: Regenerate.
821 2013-06-14 DJ Delorie <dj@redhat.com>
823 * rx-decode.opc (rx_decode_opcode): Bit operations on
824 registers are 32-bit operations, not 8-bit operations.
825 * rx-decode.c: Regenerate.
827 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
829 * micromips-opc.c (IVIRT): New define.
830 (IVIRT64): New define.
831 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
832 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
834 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
835 dmtgc0 to print cp0 names.
837 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
839 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
842 2013-06-08 Catherine Moore <clm@codesourcery.com>
843 Richard Sandiford <rdsandiford@googlemail.com>
845 * micromips-opc.c (D32, D33, MC): Update definitions.
846 (micromips_opcodes): Initialize ase field.
847 * mips-dis.c (mips_arch_choice): Add ase field.
848 (mips_arch_choices): Initialize ase field.
849 (set_default_mips_dis_options): Declare and setup mips_ase.
850 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
851 MT32, MC): Update definitions.
852 (mips_builtin_opcodes): Initialize ase field.
854 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
856 * s390-opc.txt (flogr): Require a register pair destination.
858 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
860 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
863 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
865 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
867 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
869 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
870 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
871 XLS_MASK, PPCVSX2): New defines.
872 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
873 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
874 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
875 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
876 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
877 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
878 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
879 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
880 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
881 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
882 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
883 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
884 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
885 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
886 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
887 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
888 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
889 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
890 <lxvx, stxvx>: New extended mnemonics.
892 2013-05-17 Alan Modra <amodra@gmail.com>
894 * ia64-raw.tbl: Replace non-ASCII char.
895 * ia64-waw.tbl: Likewise.
896 * ia64-asmtab.c: Regenerate.
898 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
900 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
901 * i386-init.h: Regenerated.
903 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
905 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
906 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
907 check from [0, 255] to [-128, 255].
909 2013-05-09 Andrew Pinski <apinski@cavium.com>
911 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
912 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
913 (parse_mips_dis_option): Handle the virt option.
914 (print_insn_args): Handle "+J".
915 (print_mips_disassembler_options): Print out message about virt64.
916 * mips-opc.c (IVIRT): New define.
917 (IVIRT64): New define.
918 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
919 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
920 Move rfe to the bottom as it conflicts with tlbgp.
922 2013-05-09 Alan Modra <amodra@gmail.com>
924 * ppc-opc.c (extract_vlesi): Properly sign extend.
925 (extract_vlensi): Likewise. Comment reason for setting invalid.
927 2013-05-02 Nick Clifton <nickc@redhat.com>
929 * msp430-dis.c: Add support for MSP430X instructions.
931 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
933 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
936 2013-04-17 Wei-chen Wang <cole945@gmail.com>
939 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
941 (hash_insns_list): Likewise.
943 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
945 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
948 2013-04-08 Jan Beulich <jbeulich@suse.com>
950 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
951 * i386-tbl.h: Re-generate.
953 2013-04-06 David S. Miller <davem@davemloft.net>
955 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
956 of an opcode, prefer the one with F_PREFERRED set.
957 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
958 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
959 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
960 mark existing mnenomics as aliases. Add "cc" suffix to edge
961 instructions generating condition codes, mark existing mnenomics
962 as aliases. Add "fp" prefix to VIS compare instructions, mark
963 existing mnenomics as aliases.
965 2013-04-03 Nick Clifton <nickc@redhat.com>
967 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
968 destination address by subtracting the operand from the current
970 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
971 a positive value in the insn.
972 (extract_u16_loop): Do not negate the returned value.
973 (D16_LOOP): Add V850_INVERSE_PCREL flag.
975 (ceilf.sw): Remove duplicate entry.
976 (cvtf.hs): New entry.
982 (maddf.s): Restrict to E3V5 architectures.
984 (nmaddf.s): Likewise.
985 (nmsubf.s): Likewise.
987 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
989 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
991 (print_insn): Pass sizeflag to get_sib.
993 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
996 * tic6x-dis.c: Add support for displaying 16-bit insns.
998 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
1001 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
1002 individual msb and lsb halves in src1 & src2 fields. Discard the
1003 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1004 follow what Ti SDK does in that case as any value in the src1
1005 field yields the same output with SDK disassembler.
1007 2013-03-12 Michael Eager <eager@eagercon.com>
1009 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
1011 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1013 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1015 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1017 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1019 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1021 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1023 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1025 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1026 (thumb32_opcodes): Likewise.
1027 (print_insn_thumb32): Handle 'S' control char.
1029 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
1031 * lm32-desc.c: Regenerate.
1033 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
1035 * i386-reg.tbl (riz): Add RegRex64.
1036 * i386-tbl.h: Regenerated.
1038 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1040 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1041 (aarch64_feature_crc): New static.
1043 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1044 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1045 * aarch64-asm-2.c: Re-generate.
1046 * aarch64-dis-2.c: Ditto.
1047 * aarch64-opc-2.c: Ditto.
1049 2013-02-27 Alan Modra <amodra@gmail.com>
1051 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1052 * rl78-decode.c: Regenerate.
1054 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
1056 * rl78-decode.opc: Fix encoding of DIVWU insn.
1057 * rl78-decode.c: Regenerate.
1059 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
1062 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1064 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1065 (cpu_flags): Add CpuSMAP.
1067 * i386-opc.h (CpuSMAP): New.
1068 (i386_cpu_flags): Add cpusmap.
1070 * i386-opc.tbl: Add clac and stac.
1072 * i386-init.h: Regenerated.
1073 * i386-tbl.h: Likewise.
1075 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
1077 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1078 which also makes the disassembler output be in little
1079 endian like it should be.
1081 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1083 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1085 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1087 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
1089 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1090 section disassembled.
1092 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1094 * arm-dis.c: Update strht pattern.
1096 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1098 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1099 single-float. Disable ll, lld, sc and scd for EE. Disable the
1100 trunc.w.s macro for EE.
1102 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
1103 Andrew Jenner <andrew@codesourcery.com>
1105 Based on patches from Altera Corporation.
1107 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1109 * Makefile.in: Regenerated.
1110 * configure.in: Add case for bfd_nios2_arch.
1111 * configure: Regenerated.
1112 * disassemble.c (ARCH_nios2): Define.
1113 (disassembler): Add case for bfd_arch_nios2.
1114 * nios2-dis.c: New file.
1115 * nios2-opc.c: New file.
1117 2013-02-04 Alan Modra <amodra@gmail.com>
1119 * po/POTFILES.in: Regenerate.
1120 * rl78-decode.c: Regenerate.
1121 * rx-decode.c: Regenerate.
1123 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
1125 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1126 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1127 * aarch64-asm.c (convert_xtl_to_shll): New function.
1128 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1129 calling convert_xtl_to_shll.
1130 * aarch64-dis.c (convert_shll_to_xtl): New function.
1131 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1132 calling convert_shll_to_xtl.
1133 * aarch64-gen.c: Update copyright year.
1134 * aarch64-asm-2.c: Re-generate.
1135 * aarch64-dis-2.c: Re-generate.
1136 * aarch64-opc-2.c: Re-generate.
1138 2013-01-24 Nick Clifton <nickc@redhat.com>
1140 * v850-dis.c: Add support for e3v5 architecture.
1141 * v850-opc.c: Likewise.
1143 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1145 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1146 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1147 * aarch64-opc.c (operand_general_constraint_met_p): For
1148 AARCH64_MOD_LSL, move the range check on the shift amount before the
1149 alignment check; change to call set_sft_amount_out_of_range_error
1150 instead of set_imm_out_of_range_error.
1151 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1152 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1153 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1156 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1158 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1160 * i386-init.h: Regenerated.
1161 * i386-tbl.h: Likewise.
1163 2013-01-15 Nick Clifton <nickc@redhat.com>
1165 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1167 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1169 2013-01-14 Will Newton <will.newton@imgtec.com>
1171 * metag-dis.c (REG_WIDTH): Increase to 64.
1173 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1175 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1176 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1177 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1179 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1180 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1181 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1182 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1184 2013-01-10 Will Newton <will.newton@imgtec.com>
1186 * Makefile.am: Add Meta.
1187 * configure.in: Add Meta.
1188 * disassemble.c: Add Meta support.
1189 * metag-dis.c: New file.
1190 * Makefile.in: Regenerate.
1191 * configure: Regenerate.
1193 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1195 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1196 (match_opcode): Rename to cr16_match_opcode.
1198 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1200 * mips-dis.c: Add names for CP0 registers of r5900.
1201 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1202 instructions sq and lq.
1203 Add support for MIPS r5900 CPU.
1204 Add support for 128 bit MMI (Multimedia Instructions).
1205 Add support for EE instructions (Emotion Engine).
1206 Disable unsupported floating point instructions (64 bit and
1207 undefined compare operations).
1208 Enable instructions of MIPS ISA IV which are supported by r5900.
1209 Disable 64 bit co processor instructions.
1210 Disable 64 bit multiplication and division instructions.
1211 Disable instructions for co-processor 2 and 3, because these are
1212 not supported (preparation for later VU0 support (Vector Unit)).
1213 Disable cvt.w.s because this behaves like trunc.w.s and the
1214 correct execution can't be ensured on r5900.
1215 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1216 will confuse less developers and compilers.
1218 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1220 * aarch64-opc.c (aarch64_print_operand): Change to print
1221 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1223 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1224 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1227 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1229 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1230 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1232 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1234 * i386-gen.c (process_copyright): Update copyright year to 2013.
1236 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1238 * cr16-dis.c (match_opcode,make_instruction): Remove static
1240 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1241 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1243 For older changes see ChangeLog-2012
1245 Copyright (C) 2013 Free Software Foundation, Inc.
1247 Copying and distribution of this file, with or without modification,
1248 are permitted in any medium without royalty provided the copyright
1249 notice and this notice are preserved.
1255 version-control: never