1 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
4 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
5 individual msb and lsb halves in src1 & src2 fields. Discard the
6 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
7 follow what Ti SDK does in that case as any value in the src1
8 field yields the same output with SDK disassembler.
10 2013-03-12 Michael Eager <eager@eagercon.com>
12 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
14 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
16 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
18 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
20 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
22 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
24 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
26 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
28 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
29 (thumb32_opcodes): Likewise.
30 (print_insn_thumb32): Handle 'S' control char.
32 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
34 * lm32-desc.c: Regenerate.
36 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
38 * i386-reg.tbl (riz): Add RegRex64.
39 * i386-tbl.h: Regenerated.
41 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
43 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
44 (aarch64_feature_crc): New static.
46 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
47 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
48 * aarch64-asm-2.c: Re-generate.
49 * aarch64-dis-2.c: Ditto.
50 * aarch64-opc-2.c: Ditto.
52 2013-02-27 Alan Modra <amodra@gmail.com>
54 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
55 * rl78-decode.c: Regenerate.
57 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
59 * rl78-decode.opc: Fix encoding of DIVWU insn.
60 * rl78-decode.c: Regenerate.
62 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
65 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
67 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
68 (cpu_flags): Add CpuSMAP.
70 * i386-opc.h (CpuSMAP): New.
71 (i386_cpu_flags): Add cpusmap.
73 * i386-opc.tbl: Add clac and stac.
75 * i386-init.h: Regenerated.
76 * i386-tbl.h: Likewise.
78 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
80 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
81 which also makes the disassembler output be in little
82 endian like it should be.
84 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
86 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
88 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
90 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
92 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
95 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
97 * arm-dis.c: Update strht pattern.
99 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
101 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
102 single-float. Disable ll, lld, sc and scd for EE. Disable the
103 trunc.w.s macro for EE.
105 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
106 Andrew Jenner <andrew@codesourcery.com>
108 Based on patches from Altera Corporation.
110 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
112 * Makefile.in: Regenerated.
113 * configure.in: Add case for bfd_nios2_arch.
114 * configure: Regenerated.
115 * disassemble.c (ARCH_nios2): Define.
116 (disassembler): Add case for bfd_arch_nios2.
117 * nios2-dis.c: New file.
118 * nios2-opc.c: New file.
120 2013-02-04 Alan Modra <amodra@gmail.com>
122 * po/POTFILES.in: Regenerate.
123 * rl78-decode.c: Regenerate.
124 * rx-decode.c: Regenerate.
126 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
128 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
129 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
130 * aarch64-asm.c (convert_xtl_to_shll): New function.
131 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
132 calling convert_xtl_to_shll.
133 * aarch64-dis.c (convert_shll_to_xtl): New function.
134 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
135 calling convert_shll_to_xtl.
136 * aarch64-gen.c: Update copyright year.
137 * aarch64-asm-2.c: Re-generate.
138 * aarch64-dis-2.c: Re-generate.
139 * aarch64-opc-2.c: Re-generate.
141 2013-01-24 Nick Clifton <nickc@redhat.com>
143 * v850-dis.c: Add support for e3v5 architecture.
144 * v850-opc.c: Likewise.
146 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
148 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
149 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
150 * aarch64-opc.c (operand_general_constraint_met_p): For
151 AARCH64_MOD_LSL, move the range check on the shift amount before the
152 alignment check; change to call set_sft_amount_out_of_range_error
153 instead of set_imm_out_of_range_error.
154 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
155 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
156 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
159 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
161 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
163 * i386-init.h: Regenerated.
164 * i386-tbl.h: Likewise.
166 2013-01-15 Nick Clifton <nickc@redhat.com>
168 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
170 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
172 2013-01-14 Will Newton <will.newton@imgtec.com>
174 * metag-dis.c (REG_WIDTH): Increase to 64.
176 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
178 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
179 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
180 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
182 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
183 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
184 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
185 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
187 2013-01-10 Will Newton <will.newton@imgtec.com>
189 * Makefile.am: Add Meta.
190 * configure.in: Add Meta.
191 * disassemble.c: Add Meta support.
192 * metag-dis.c: New file.
193 * Makefile.in: Regenerate.
194 * configure: Regenerate.
196 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
198 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
199 (match_opcode): Rename to cr16_match_opcode.
201 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
203 * mips-dis.c: Add names for CP0 registers of r5900.
204 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
205 instructions sq and lq.
206 Add support for MIPS r5900 CPU.
207 Add support for 128 bit MMI (Multimedia Instructions).
208 Add support for EE instructions (Emotion Engine).
209 Disable unsupported floating point instructions (64 bit and
210 undefined compare operations).
211 Enable instructions of MIPS ISA IV which are supported by r5900.
212 Disable 64 bit co processor instructions.
213 Disable 64 bit multiplication and division instructions.
214 Disable instructions for co-processor 2 and 3, because these are
215 not supported (preparation for later VU0 support (Vector Unit)).
216 Disable cvt.w.s because this behaves like trunc.w.s and the
217 correct execution can't be ensured on r5900.
218 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
219 will confuse less developers and compilers.
221 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
223 * aarch64-opc.c (aarch64_print_operand): Change to print
224 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
226 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
227 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
230 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
232 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
233 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
235 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
237 * i386-gen.c (process_copyright): Update copyright year to 2013.
239 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
241 * cr16-dis.c (match_opcode,make_instruction): Remove static
243 (dwordU,wordU): Moved typedefs to opcode/cr16.h
244 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
246 For older changes see ChangeLog-2012
248 Copyright (C) 2013 Free Software Foundation, Inc.
250 Copying and distribution of this file, with or without modification,
251 are permitted in any medium without royalty provided the copyright
252 notice and this notice are preserved.
258 version-control: never