* powerpc.cc (Powerpc_relobj): Add and use Address typedef.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
1 2012-08-29 Peter Bergner <bergner@vnet.ibm.com>
2
3 * ppc-opc.c (VXASHB_MASK): New define.
4 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
5
6 2012-08-28 Peter Bergner <bergner@vnet.ibm.com>
7
8 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
9 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
10 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
11 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
12 vupklsh>: Use VXVA_MASK.
13 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
14 <mfvscr>: Use VXVAVB_MASK.
15 <mtvscr>: Use VXVDVA_MASK.
16 <vspltb>: Use VXUIMM4_MASK.
17 <vsplth>: Use VXUIMM3_MASK.
18 <vspltw>: Use VXUIMM2_MASK.
19
20 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
21
22 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
23
24 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
25
26 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
27
28 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
29
30 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
31
32 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
33
34 * arm-dis.c (neon_opcodes): Add support for AES instructions.
35
36 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
37
38 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
39 conversions.
40
41 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
42
43 * arm-dis.c (coprocessor_opcodes): Add VRINT.
44 (neon_opcodes): Likewise.
45
46 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
47
48 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
49 variants.
50 (neon_opcodes): Likewise.
51
52 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
53
54 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
55 (neon_opcodes): Likewise.
56
57 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
58
59 * arm-dis.c (coprocessor_opcodes): Add VSEL.
60 (print_insn_coprocessor): Add new %<>c bitfield format
61 specifier.
62
63 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
64
65 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
66 (thumb32_opcodes): Likewise.
67 (print_arm_insn): Add support for %<>T formatter.
68
69 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
70
71 * arm-dis.c (arm_opcodes): Add HLT.
72 (thumb_opcodes): Likewise.
73
74 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
75
76 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
77
78 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
79
80 * arm-dis.c (arm_opcodes): Add SEVL.
81 (thumb_opcodes): Likewise.
82 (thumb32_opcodes): Likewise.
83
84 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
85
86 * arm-dis.c (data_barrier_option): New function.
87 (print_insn_arm): Use data_barrier_option.
88 (print_insn_thumb32): Use data_barrier_option.
89
90 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
91
92 * arm-dis.c (COND_UNCOND): New constant.
93 (print_insn_coprocessor): Add support for %u format specifier.
94 (print_insn_neon): Likewise.
95
96 2012-08-21 David S. Miller <davem@davemloft.net>
97
98 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
99 F3F4 macro.
100
101 2012-08-20 Edmar Wienskoski <edmar@freescale.com>
102
103 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
104 vabsduh, vabsduw, mviwsplt.
105
106 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
107
108 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
109 CPU_BTVER2_FLAGS.
110
111 * i386-opc.h: Update CpuPRFCHW comment.
112
113 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
114 * i386-init.h: Regenerated.
115 * i386-tbl.h: Likewise.
116
117 2012-08-17 Nick Clifton <nickc@redhat.com>
118
119 * po/uk.po: New Ukranian translation.
120 * configure.in (ALL_LINGUAS): Add uk.
121 * configure: Regenerate.
122
123 2012-08-16 Peter Bergner <bergner@vnet.ibm.com>
124
125 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
126 RBX for the third operand.
127 <"lswi">: Use RAX for second and NBI for the third operand.
128
129 2012-08-15 DJ Delorie <dj@redhat.com>
130
131 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
132 operands, so that data addresses can be corrected when not
133 ES-overridden.
134 * rl78-decode.c: Regenerate.
135 * rl78-dis.c (print_insn_rl78): Make order of modifiers
136 irrelevent. When the 'e' specifier is used on an operand and no
137 ES prefix is provided, adjust address to make it absolute.
138
139 2012-08-15 Peter Bergner <bergner@vnet.ibm.com>
140
141 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
142
143 2012-08-15 Peter Bergner <bergner@vnet.ibm.com>
144
145 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
146
147 2012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
148
149 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
150 macros, use local variables for info struct member accesses,
151 update the type of the variable used to hold the instruction
152 word.
153 (print_insn_mips, print_mips16_insn_arg): Likewise.
154 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
155 local variables for info struct member accesses.
156 (print_insn_micromips): Add GET_OP_S local macro.
157 (_print_insn_mips): Update the type of the variable used to hold
158 the instruction word.
159
160 2012-08-13 Ian Bolton <ian.bolton@arm.com>
161 Laurent Desnogues <laurent.desnogues@arm.com>
162 Jim MacArthur <jim.macarthur@arm.com>
163 Marcus Shawcroft <marcus.shawcroft@arm.com>
164 Nigel Stephens <nigel.stephens@arm.com>
165 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
166 Richard Earnshaw <rearnsha@arm.com>
167 Sofiane Naci <sofiane.naci@arm.com>
168 Tejas Belagod <tejas.belagod@arm.com>
169 Yufeng Zhang <yufeng.zhang@arm.com>
170
171 * Makefile.am: Add AArch64.
172 * Makefile.in: Regenerate.
173 * aarch64-asm.c: New file.
174 * aarch64-asm.h: New file.
175 * aarch64-dis.c: New file.
176 * aarch64-dis.h: New file.
177 * aarch64-gen.c: New file.
178 * aarch64-opc.c: New file.
179 * aarch64-opc.h: New file.
180 * aarch64-tbl.h: New file.
181 * configure.in: Add AArch64.
182 * configure: Regenerate.
183 * disassemble.c: Add AArch64.
184 * aarch64-asm-2.c: New file (automatically generated).
185 * aarch64-dis-2.c: New file (automatically generated).
186 * aarch64-opc-2.c: New file (automatically generated).
187 * po/POTFILES.in: Regenerate.
188
189 2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
190
191 * micromips-opc.c (micromips_opcodes): Update comment.
192 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
193 instructions for IOCT as appropriate.
194 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
195 opcode_is_member.
196 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
197 the result of a check for the -Wno-missing-field-initializers
198 GCC option.
199 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
200 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
201 compilation.
202 (mips16-opc.lo): Likewise.
203 (micromips-opc.lo): Likewise.
204 * aclocal.m4: Regenerate.
205 * configure: Regenerate.
206 * Makefile.in: Regenerate.
207
208 2012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
209
210 PR gas/14423
211 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
212 * i386-init.h: Regenerated.
213
214 2012-08-09 Nick Clifton <nickc@redhat.com>
215
216 * po/vi.po: Updated Vietnamese translation.
217
218 2012-08-07 Roland McGrath <mcgrathr@google.com>
219
220 * i386-dis.c (reg_table): Fill out REG_0F0D table with
221 AMD-reserved cases as "prefetch".
222 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
223 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
224 (reg_table): Use those under REG_0F18.
225 (mod_table): Add those cases as "nop/reserved".
226
227 2012-08-07 Jan Beulich <jbeulich@suse.com>
228
229 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
230
231 2012-08-06 Roland McGrath <mcgrathr@google.com>
232
233 * i386-dis.c (print_insn): Print spaces between multiple excess
234 prefixes. Return actual number of excess prefixes consumed,
235 not always one.
236
237 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
238
239 2012-08-06 Roland McGrath <mcgrathr@google.com>
240 Victor Khimenko <khim@google.com>
241 H.J. Lu <hongjiu.lu@intel.com>
242
243 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
244 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
245 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
246 (OP_E_register): Likewise.
247 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
248
249 2012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
250
251 * configure.in: Formatting.
252 * configure: Regenerate.
253
254 2012-08-01 Alan Modra <amodra@gmail.com>
255
256 * h8300-dis.c: Fix printf arg warnings.
257 * i960-dis.c: Likewise.
258 * mips-dis.c: Likewise.
259 * pdp11-dis.c: Likewise.
260 * sh-dis.c: Likewise.
261 * v850-dis.c: Likewise.
262 * configure.in: Formatting.
263 * configure: Regenerate.
264 * rl78-decode.c: Regenerate.
265 * po/POTFILES.in: Regenerate.
266
267 2012-07-31 Chao-Ying Fu <fu@mips.com>
268 Catherine Moore <clm@codesourcery.com>
269 Maciej W. Rozycki <macro@codesourcery.com>
270
271 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
272 (DSP_VOLA): Likewise.
273 (D32, D33): Likewise.
274 (micromips_opcodes): Add DSP ASE instructions.
275 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
276 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
277
278 2012-07-31 Jan Beulich <jbeulich@suse.com>
279
280 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
281 instruction group. Mark as requiring AVX2.
282 * i386-tbl.h: Re-generate.
283
284 2012-07-30 Nick Clifton <nickc@redhat.com>
285
286 * po/opcodes.pot: Updated template.
287 * po/es.po: Updated Spanish translation.
288 * po/fi.po: Updated Finnish translation.
289
290 2012-07-27 Mike Frysinger <vapier@gentoo.org>
291
292 * configure.in (BFD_VERSION): Run bfd/configure --version and
293 parse the output of that.
294 * configure: Regenerate.
295
296 2012-07-25 James Lemke <jwlemke@codesourcery.com>
297
298 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
299
300 2012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
301 Dr David Alan Gilbert <dave@treblig.org>
302
303 PR binutils/13135
304 * arm-dis.c: Add necessary casts for printing integer values.
305 Use %s when printing string values.
306 * hppa-dis.c: Likewise.
307 * m68k-dis.c: Likewise.
308 * microblaze-dis.c: Likewise.
309 * mips-dis.c: Likewise.
310 * sparc-dis.c: Likewise.
311
312 2012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
313
314 PR binutils/14355
315 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
316 (VEX_LEN_0FXOP_08_CD): Likewise.
317 (VEX_LEN_0FXOP_08_CE): Likewise.
318 (VEX_LEN_0FXOP_08_CF): Likewise.
319 (VEX_LEN_0FXOP_08_EC): Likewise.
320 (VEX_LEN_0FXOP_08_ED): Likewise.
321 (VEX_LEN_0FXOP_08_EE): Likewise.
322 (VEX_LEN_0FXOP_08_EF): Likewise.
323 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
324 vpcomub, vpcomuw, vpcomud, vpcomuq.
325 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
326 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
327 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
328 VEX_LEN_0FXOP_08_EF.
329
330 2012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
331
332 * i386-dis.c (PREFIX_0F38F6): New.
333 (prefix_table): Add adcx, adox instructions.
334 (three_byte_table): Use PREFIX_0F38F6.
335 (mod_table): Add rdseed instruction.
336 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
337 (cpu_flags): Likewise.
338 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
339 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
340 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
341 prefetchw.
342 * i386-tbl.h: Regenerate.
343 * i386-init.h: Likewise.
344
345 2012-07-05 Thomas Schwinge <thomas@codesourcery.com>
346
347 * mips-dis.c: Remove gratuitous newline.
348
349 2012-07-05 Sean Keys <skeys@ipdatasys.com>
350
351 * xgate-dis.c: Removed an IF statement that will
352 always be false due to overlapping operand masks.
353 * xgate-opc.c: Corrected 'com' opcode entry and
354 fixed spacing.
355
356 2012-07-02 Roland McGrath <mcgrathr@google.com>
357
358 * i386-opc.tbl: Add RepPrefixOk to nop.
359 * i386-tbl.h: Regenerate.
360
361 2012-06-28 Nick Clifton <nickc@redhat.com>
362
363 * po/vi.po: Updated Vietnamese translation.
364
365 2012-06-22 Roland McGrath <mcgrathr@google.com>
366
367 * i386-opc.tbl: Add RepPrefixOk to ret.
368 * i386-tbl.h: Regenerate.
369
370 * i386-opc.h (RepPrefixOk): New enum constant.
371 (i386_opcode_modifier): New bitfield 'repprefixok'.
372 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
373 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
374 instructions that have IsString.
375 * i386-tbl.h: Regenerate.
376
377 2012-06-11 Andreas Schwab <schwab@linux-m68k.org>
378
379 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
380 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
381 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
382 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
383 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
384 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
385 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
386 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
387 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
388
389 2012-05-19 Alan Modra <amodra@gmail.com>
390
391 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
392 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
393
394 2012-05-18 Alan Modra <amodra@gmail.com>
395
396 * ia64-opc.c: Remove #include "ansidecl.h".
397 * z8kgen.c: Include sysdep.h first.
398
399 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
400 * bfin-dis.c: Likewise.
401 * i860-dis.c: Likewise.
402 * ia64-dis.c: Likewise.
403 * ia64-gen.c: Likewise.
404 * m68hc11-dis.c: Likewise.
405 * mmix-dis.c: Likewise.
406 * msp430-dis.c: Likewise.
407 * or32-dis.c: Likewise.
408 * rl78-dis.c: Likewise.
409 * rx-dis.c: Likewise.
410 * tic4x-dis.c: Likewise.
411 * tilegx-opc.c: Likewise.
412 * tilepro-opc.c: Likewise.
413 * rx-decode.c: Regenerate.
414
415 2012-05-17 James Lemke <jwlemke@codesourcery.com>
416
417 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
418
419 2012-05-17 James Lemke <jwlemke@codesourcery.com>
420
421 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
422
423 2012-05-17 Daniel Richard G. <skunk@iskunk.org>
424 Nick Clifton <nickc@redhat.com>
425
426 PR 14072
427 * configure.in: Add check that sysdep.h has been included before
428 any system header files.
429 * configure: Regenerate.
430 * config.in: Regenerate.
431 * sysdep.h: Generate an error if included before config.h.
432 * alpha-opc.c: Include sysdep.h before any other header file.
433 * alpha-dis.c: Likewise.
434 * avr-dis.c: Likewise.
435 * cgen-opc.c: Likewise.
436 * cr16-dis.c: Likewise.
437 * cris-dis.c: Likewise.
438 * crx-dis.c: Likewise.
439 * d10v-dis.c: Likewise.
440 * d10v-opc.c: Likewise.
441 * d30v-dis.c: Likewise.
442 * d30v-opc.c: Likewise.
443 * h8500-dis.c: Likewise.
444 * i370-dis.c: Likewise.
445 * i370-opc.c: Likewise.
446 * m10200-dis.c: Likewise.
447 * m10300-dis.c: Likewise.
448 * micromips-opc.c: Likewise.
449 * mips-opc.c: Likewise.
450 * mips61-opc.c: Likewise.
451 * moxie-dis.c: Likewise.
452 * or32-opc.c: Likewise.
453 * pj-dis.c: Likewise.
454 * ppc-dis.c: Likewise.
455 * ppc-opc.c: Likewise.
456 * s390-dis.c: Likewise.
457 * sh-dis.c: Likewise.
458 * sh64-dis.c: Likewise.
459 * sparc-dis.c: Likewise.
460 * sparc-opc.c: Likewise.
461 * spu-dis.c: Likewise.
462 * tic30-dis.c: Likewise.
463 * tic54x-dis.c: Likewise.
464 * tic80-dis.c: Likewise.
465 * tic80-opc.c: Likewise.
466 * tilegx-dis.c: Likewise.
467 * tilepro-dis.c: Likewise.
468 * v850-dis.c: Likewise.
469 * v850-opc.c: Likewise.
470 * vax-dis.c: Likewise.
471 * w65-dis.c: Likewise.
472 * xgate-dis.c: Likewise.
473 * xtensa-dis.c: Likewise.
474 * rl78-decode.opc: Likewise.
475 * rl78-decode.c: Regenerate.
476 * rx-decode.opc: Likewise.
477 * rx-decode.c: Regenerate.
478
479 2012-05-17 Alan Modra <amodra@gmail.com>
480
481 * ppc_dis.c: Don't include elf/ppc.h.
482
483 2012-05-16 Meador Inge <meadori@codesourcery.com>
484
485 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
486 to PUSH/POP {reg}.
487
488 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
489 Stephane Carrez <stcarrez@nerim.fr>
490
491 * configure.in: Add S12X and XGATE co-processor support to m68hc11
492 target.
493 * disassemble.c: Likewise.
494 * configure: Regenerate.
495 * m68hc11-dis.c: Make objdump output more consistent, use hex
496 instead of decimal and use 0x prefix for hex.
497 * m68hc11-opc.c: Add S12X and XGATE opcodes.
498
499 2012-05-14 James Lemke <jwlemke@codesourcery.com>
500
501 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
502 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
503 (vle_opcd_indices): New array.
504 (lookup_vle): New function.
505 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
506 (print_insn_powerpc): Likewise.
507 * ppc-opc.c: Likewise.
508
509 2012-05-14 Catherine Moore <clm@codesourcery.com>
510 Maciej W. Rozycki <macro@codesourcery.com>
511 Rhonda Wittels <rhonda@codesourcery.com>
512 Nathan Froyd <froydnj@codesourcery.com>
513
514 * ppc-opc.c (insert_arx, extract_arx): New functions.
515 (insert_ary, extract_ary): New functions.
516 (insert_li20, extract_li20): New functions.
517 (insert_rx, extract_rx): New functions.
518 (insert_ry, extract_ry): New functions.
519 (insert_sci8, extract_sci8): New functions.
520 (insert_sci8n, extract_sci8n): New functions.
521 (insert_sd4h, extract_sd4h): New functions.
522 (insert_sd4w, extract_sd4w): New functions.
523 (insert_vlesi, extract_vlesi): New functions.
524 (insert_vlensi, extract_vlensi): New functions.
525 (insert_vleui, extract_vleui): New functions.
526 (insert_vleil, extract_vleil): New functions.
527 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
528 (BI16, BI32, BO32, B8): New.
529 (B15, B24, CRD32, CRS): New.
530 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
531 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
532 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
533 (SH6_MASK): Use PPC_OPSHIFT_INV.
534 (SI8, UI5, OIMM5, UI7, BO16): New.
535 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
536 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
537 (ALLOW8_SPRG): New.
538 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
539 (OPVUP, OPVUP_MASK OPVUP): New
540 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
541 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
542 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
543 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
544 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
545 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
546 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
547 (SE_IM5, SE_IM5_MASK): New.
548 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
549 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
550 (BO32DNZ, BO32DZ): New.
551 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
552 (PPCVLE): New.
553 (powerpc_opcodes): Add new VLE instructions. Update existing
554 instruction to include PPCVLE if supported.
555 * ppc-dis.c (ppc_opts): Add vle entry.
556 (get_powerpc_dialect): New function.
557 (powerpc_init_dialect): VLE support.
558 (print_insn_big_powerpc): Call get_powerpc_dialect.
559 (print_insn_little_powerpc): Likewise.
560 (operand_value_powerpc): Handle negative shift counts.
561 (print_insn_powerpc): Handle 2-byte instruction lengths.
562
563 2012-05-11 Daniel Richard G. <skunk@iskunk.org>
564
565 PR binutils/14028
566 * configure.in: Invoke ACX_HEADER_STRING.
567 * configure: Regenerate.
568 * config.in: Regenerate.
569 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
570 string.h and strings.h.
571
572 2012-05-11 Nick Clifton <nickc@redhat.com>
573
574 PR binutils/14006
575 * arm-dis.c (print_insn): Fix detection of instruction mode in
576 files containing multiple executable sections.
577
578 2012-05-03 Sean Keys <skeys@ipdatasys.com>
579
580 * Makefile.in, configure: regenerate
581 * disassemble.c (disassembler): Recognize ARCH_XGATE.
582 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
583 New functions.
584 * configure.in: Recognize xgate.
585 * xgate-dis.c, xgate-opc.c: New files for support of xgate
586 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
587 and opcode generation for xgate.
588
589 2012-04-30 DJ Delorie <dj@redhat.com>
590
591 * rx-decode.opc (MOV): Do not sign-extend immediates which are
592 already the maximum bit size.
593 * rx-decode.c: Regenerate.
594
595 2012-04-27 David S. Miller <davem@davemloft.net>
596
597 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
598 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
599
600 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
601 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
602
603 * sparc-opc.c (CBCOND): New define.
604 (CBCOND_XCC): Likewise.
605 (cbcond): New helper macro.
606 (sparc_opcodes): Add compare-and-branch instructions.
607
608 * sparc-dis.c (print_insn_sparc): Handle ')'.
609 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
610
611 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
612 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
613
614 2012-04-12 David S. Miller <davem@davemloft.net>
615
616 * sparc-dis.c (X_DISP10): Define.
617 (print_insn_sparc): Handle '='.
618
619 2012-04-01 Mike Frysinger <vapier@gentoo.org>
620
621 * bfin-dis.c (fmtconst): Replace decimal handling with a single
622 sprintf call and the '*' field width.
623
624 2012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
625
626 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
627
628 2012-03-16 Alan Modra <amodra@gmail.com>
629
630 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
631 (powerpc_opcd_indices): Bump array size.
632 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
633 corresponding to unused opcodes to following entry.
634 (lookup_powerpc): New function, extracted and optimised from..
635 (print_insn_powerpc): ..here.
636
637 2012-03-15 Alan Modra <amodra@gmail.com>
638 James Lemke <jwlemke@codesourcery.com>
639
640 * disassemble.c (disassemble_init_for_target): Handle ppc init.
641 * ppc-dis.c (private): New var.
642 (powerpc_init_dialect): Don't return calloc failure, instead use
643 private.
644 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
645 (powerpc_opcd_indices): New array.
646 (disassemble_init_powerpc): New function.
647 (print_insn_big_powerpc): Don't init dialect here.
648 (print_insn_little_powerpc): Likewise.
649 (print_insn_powerpc): Start search using powerpc_opcd_indices.
650
651 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
652
653 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
654 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
655 (PPCVEC2, PPCTMR, E6500): New short names.
656 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
657 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
658 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
659 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
660 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
661 optional operands on sync instruction for E6500 target.
662
663 2012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
664
665 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
666
667 2012-02-27 Alan Modra <amodra@gmail.com>
668
669 * mt-dis.c: Regenerate.
670
671 2012-02-27 Alan Modra <amodra@gmail.com>
672
673 * v850-opc.c (extract_v8): Rearrange to make it obvious this
674 is the inverse of corresponding insert function.
675 (extract_d22, extract_u9, extract_r4): Likewise.
676 (extract_d9): Correct sign extension.
677 (extract_d16_15): Don't assume "long" is 32 bits, and don't
678 rely on implementation defined behaviour for shift right of
679 signed types.
680 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
681 (extract_d23): Likewise, and correct mask.
682
683 2012-02-27 Alan Modra <amodra@gmail.com>
684
685 * crx-dis.c (print_arg): Mask constant to 32 bits.
686 * crx-opc.c (cst4_map): Use int array.
687
688 2012-02-27 Alan Modra <amodra@gmail.com>
689
690 * arc-dis.c (BITS): Don't use shifts to mask off bits.
691 (FIELDD): Sign extend with xor,sub.
692
693 2012-02-25 Walter Lee <walt@tilera.com>
694
695 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
696 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
697 TILEPRO_OPC_LW_TLS_SN.
698
699 2012-02-21 H.J. Lu <hongjiu.lu@intel.com>
700
701 * i386-opc.h (HLEPrefixNone): New.
702 (HLEPrefixLock): Likewise.
703 (HLEPrefixAny): Likewise.
704 (HLEPrefixRelease): Likewise.
705
706 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
707
708 * i386-dis.c (HLE_Fixup1): New.
709 (HLE_Fixup2): Likewise.
710 (HLE_Fixup3): Likewise.
711 (Ebh1): Likewise.
712 (Evh1): Likewise.
713 (Ebh2): Likewise.
714 (Evh2): Likewise.
715 (Ebh3): Likewise.
716 (Evh3): Likewise.
717 (MOD_C6_REG_7): Likewise.
718 (MOD_C7_REG_7): Likewise.
719 (RM_C6_REG_7): Likewise.
720 (RM_C7_REG_7): Likewise.
721 (XACQUIRE_PREFIX): Likewise.
722 (XRELEASE_PREFIX): Likewise.
723 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
724 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
725 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
726 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
727 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
728 MOD_C6_REG_7 and MOD_C7_REG_7.
729 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
730 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
731 xtest.
732 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
733 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
734
735 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
736 CPU_RTM_FLAGS.
737 (cpu_flags): Add CpuHLE and CpuRTM.
738 (opcode_modifiers): Add HLEPrefixOk.
739
740 * i386-opc.h (CpuHLE): New.
741 (CpuRTM): Likewise.
742 (HLEPrefixOk): Likewise.
743 (i386_cpu_flags): Add cpuhle and cpurtm.
744 (i386_opcode_modifier): Add hleprefixok.
745
746 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
747 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
748 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
749 operand. Add xacquire, xrelease, xabort, xbegin, xend and
750 xtest.
751 * i386-init.h: Regenerated.
752 * i386-tbl.h: Likewise.
753
754 2012-01-24 DJ Delorie <dj@redhat.com>
755
756 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
757 * rl78-decode.c: Regenerate.
758
759 2012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
760
761 PR binutils/10173
762 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
763
764 2012-01-17 Andreas Schwab <schwab@linux-m68k.org>
765
766 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
767 register and move them after pmove with PSR/PCSR register.
768
769 2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
770
771 * i386-dis.c (mod_table): Add vmfunc.
772
773 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
774 (cpu_flags): CpuVMFUNC.
775
776 * i386-opc.h (CpuVMFUNC): New.
777 (i386_cpu_flags): Add cpuvmfunc.
778
779 * i386-opc.tbl: Add vmfunc.
780 * i386-init.h: Regenerated.
781 * i386-tbl.h: Likewise.
782
783 For older changes see ChangeLog-2011
784 \f
785 Local Variables:
786 mode: change-log
787 left-margin: 8
788 fill-column: 74
789 version-control: never
790 End:
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