opcodes/ChangeLog

   1 2006-05-04  Thiemo Seufer  <ths@mips.com>
   2             Nigel Stephens  <nigel@mips.com>
   3             David Ung  <davidu@mips.com>
   4
   5         * mips-dis.c (mips_arch_choices): Add smartmips instruction
   6         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
   7         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
   8         MIPS64R2.
   9         * mips-opc.c: fix random typos in comments.
  10         (INSN_SMARTMIPS): New defines.
  11         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
  12         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
  13         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
  14         FP_S and FP_D flags to denote single and double register
  15         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
  16         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
  17         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
  18         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
  19         release 2 ISAs.
  20         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
  21
  22 2006-05-03  Thiemo Seufer  <ths@mips.com>
  23
  24         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
  25
  26 2006-05-02  Thiemo Seufer  <ths@mips.com>
  27             Nigel Stephens  <nigel@mips.com>
  28             David Ung  <davidu@mips.com>
  29
  30         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
  31         (print_mips16_insn_arg): Force mips16 to odd addresses.
  32
  33 2006-04-30  Thiemo Seufer  <ths@mips.com>
  34             David Ung  <davidu@mips.com>
  35
  36         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
  37         "udi0" to "udi15".
  38         * mips-dis.c (print_insn_args): Adds udi argument handling.
  39
  40 2006-04-28  James E Wilson  <wilson@specifix.com>
  41
  42         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
  43         error message.
  44
  45 2006-04-28  Thiemo Seufer  <ths@mips.com>
  46             David Ung  <davidu@mips.com>
  47             Nigel Stephens  <nigel@mips.com>
  48
  49         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
  50         names.
  51
  52 2006-04-28  Thiemo Seufer  <ths@mips.com>
  53             Nigel Stephens  <nigel@mips.com>
  54             David Ung  <davidu@mips.com>
  55
  56         * mips-dis.c (print_insn_args): Add mips_opcode argument.
  57         (print_insn_mips):  Adjust print_insn_args call.
  58
  59 2006-04-28  Thiemo Seufer  <ths@mips.com>
  60             Nigel Stephens  <nigel@mips.com>
  61
  62         * mips-dis.c (print_insn_args): Print $fcc only for FP
  63         instructions, use $cc elsewise.
  64
  65 2006-04-28  Thiemo Seufer  <ths@mips.com>
  66             Nigel Stephens  <nigel@mips.com>
  67
  68         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
  69         Map MIPS16 registers to O32 names.
  70         (print_mips16_insn_arg): Use mips16_reg_names.
  71
  72 2006-04-26  Julian Brown  <julian@codesourcery.com>
  73
  74         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
  75         VMOV.
  76
  77 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
  78             Julian Brown  <julian@codesourcery.com>
  79
  80         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
  81         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
  82         Add unified load/store instruction names.
  83         (neon_opcode_table): New.
  84         (arm_opcodes): Expand meaning of %<bitfield>['`?].
  85         (arm_decode_bitfield): New.
  86         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
  87         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
  88         (print_insn_neon): New.
  89         (print_insn_arm): Adjust print_insn_coprocessor call. Call
  90         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
  91         (print_insn_thumb32): Likewise.
  92
  93 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
  94
  95         * Makefile.am: Run "make dep-am".
  96         * Makefile.in: Regenerate.
  97
  98 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
  99
 100         * avr-dis.c (avr_operand): Warning fix.
 101
 102         * configure: Regenerate.
 103
 104 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 105
 106         * po/POTFILES.in: Regenerated.
 107
 108 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 109
 110         PR binutils/2454
 111         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 112         the symolic form of an address, so that the output of objdump -d
 113         can be reassembled.
 114
 115 2006-04-10  DJ Delorie  <dj@redhat.com>
 116
 117         * m32c-asm.c: Regenerate.
 118
 119 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 120
 121         * Makefile.am: Add install-html target.
 122         * Makefile.in: Regenerate.
 123
 124 2006-04-06  Nick Clifton  <nickc@redhat.com>
 125
 126         * po/vi/po: Updated Vietnamese translation.
 127
 128 2006-03-31  Paul Koning  <ni1d@arrl.net>
 129
 130         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 131
 132 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 133
 134         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 135         logic to identify halfword shifts.
 136
 137 2006-03-16  Paul Brook  <paul@codesourcery.com>
 138
 139         * arm-dis.c (arm_opcodes): Rename swi to svc.
 140         (thumb_opcodes): Ditto.
 141
 142 2006-03-13  DJ Delorie  <dj@redhat.com>
 143
 144         * m32c-asm.c: Regenerate.
 145         * m32c-desc.c: Likewise.
 146         * m32c-desc.h: Likewise.
 147         * m32c-dis.c: Likewise.
 148         * m32c-ibld.c: Likewise.
 149         * m32c-opc.c: Likewise.
 150         * m32c-opc.h: Likewise.
 151
 152 2006-03-10  DJ Delorie  <dj@redhat.com>
 153
 154         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 155         * m32c-opc.c: Likewise.
 156         * m32c-opc.h: Likewise.
 157
 158
 159 2006-03-09  Nick Clifton  <nickc@redhat.com>
 160
 161         * po/sv.po: Updated Swedish translation.
 162
 163 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 164
 165         PR binutils/2428
 166         * i386-dis.c (REP_Fixup): New function.
 167         (AL): Remove duplicate.
 168         (Xbr): New.
 169         (Xvr): Likewise.
 170         (Ybr): Likewise.
 171         (Yvr): Likewise.
 172         (indirDXr): Likewise.
 173         (ALr): Likewise.
 174         (eAXr): Likewise.
 175         (dis386): Updated entries of ins, outs, movs, lods and stos.
 176
 177 2006-03-05  Nick Clifton  <nickc@redhat.com>
 178
 179         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 180         signed 32-bit value into an unsigned 32-bit field when the host is
 181         a 64-bit machine.
 182         * fr30-ibld.c: Regenerate.
 183         * frv-ibld.c: Regenerate.
 184         * ip2k-ibld.c: Regenerate.
 185         * iq2000-asm.c: Regenerate.
 186         * iq2000-ibld.c: Regenerate.
 187         * m32c-ibld.c: Regenerate.
 188         * m32r-ibld.c: Regenerate.
 189         * openrisc-ibld.c: Regenerate.
 190         * xc16x-ibld.c: Regenerate.
 191         * xstormy16-ibld.c: Regenerate.
 192
 193 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 194
 195         * xc16x-asm.c: Regenerate.
 196         * xc16x-dis.c: Regenerate.
 197
 198 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 199
 200         * po/Make-in: Add html target.
 201
 202 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 203
 204         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 205         Intel Merom New Instructions.
 206         (THREE_BYTE_0): Likewise.
 207         (THREE_BYTE_1): Likewise.
 208         (three_byte_table): Likewise.
 209         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 210         THREE_BYTE_1 for entry 0x3a.
 211         (twobyte_has_modrm): Updated.
 212         (twobyte_uses_SSE_prefix): Likewise.
 213         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 214         Instructions.
 215
 216 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 217
 218         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 219         (v9_hpriv_reg_names): New table.
 220         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 221         New cases '$' and '%' for read/write hyperprivileged register.
 222         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 223         window handling and rdhpr/wrhpr instructions.
 224
 225 2006-02-24  DJ Delorie  <dj@redhat.com>
 226
 227         * m32c-desc.c: Regenerate with linker relaxation attributes.
 228         * m32c-desc.h: Likewise.
 229         * m32c-dis.c: Likewise.
 230         * m32c-opc.c: Likewise.
 231
 232 2006-02-24  Paul Brook  <paul@codesourcery.com>
 233
 234         * arm-dis.c (arm_opcodes): Add V7 instructions.
 235         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 236         (print_arm_address): New function.
 237         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 238         (psr_name): New function.
 239         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 240
 241 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 242
 243         * ia64-opc-i.c (bXc): New.
 244         (mXc): Likewise.
 245         (OpX2TaTbYaXcC): Likewise.
 246         (TF). Likewise.
 247         (TFCM). Likewise.
 248         (ia64_opcodes_i): Add instructions for tf.
 249
 250         * ia64-opc.h (IMMU5b): New.
 251
 252         * ia64-asmtab.c: Regenerated.
 253
 254 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 255
 256         * ia64-gen.c: Update copyright years.
 257         * ia64-opc-b.c: Likewise.
 258
 259 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 260
 261         * ia64-gen.c (lookup_regindex): Handle ".vm".
 262         (print_dependency_table): Handle '\"'.
 263
 264         * ia64-ic.tbl: Updated from SDM 2.2.
 265         * ia64-raw.tbl: Likewise.
 266         * ia64-waw.tbl: Likewise.
 267         * ia64-asmtab.c: Regenerated.
 268
 269         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 270
 271 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 272             Anil Paranjape   <anilp1@kpitcummins.com>
 273             Shilin Shakti    <shilins@kpitcummins.com>
 274
 275         * xc16x-desc.h: New file
 276         * xc16x-desc.c: New file
 277         * xc16x-opc.h: New file
 278         * xc16x-opc.c: New file
 279         * xc16x-ibld.c: New file
 280         * xc16x-asm.c: New file
 281         * xc16x-dis.c: New file
 282         * Makefile.am: Entries for xc16x
 283         * Makefile.in: Regenerate
 284         * cofigure.in: Add xc16x target information.
 285         * configure: Regenerate.
 286         * disassemble.c: Add xc16x target information.
 287
 288 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 289
 290         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 291         moves.
 292
 293 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 294
 295         * i386-dis.c ('Z'): Add a new macro.
 296         (dis386_twobyte): Use "movZ" for control register moves.
 297
 298 2006-02-10  Nick Clifton  <nickc@redhat.com>
 299
 300         * iq2000-asm.c: Regenerate.
 301
 302 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 303
 304         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 305
 306 2006-01-26  David Ung  <davidu@mips.com>
 307
 308         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 309         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 310         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 311         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 312         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 313
 314 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 315
 316         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 317         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 318         disassembled.
 319         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 320         buffer overflows when disassembling instructions like
 321         ld (ix+123),0x23
 322         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 323         operand, if the offset is negative.
 324
 325 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 326
 327         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 328         unsigned char to hold data to be disassembled.
 329
 330 2006-01-17  Andreas Schwab  <schwab@suse.de>
 331
 332         PR binutils/1486
 333         * disassemble.c (disassemble_init_for_target): Set
 334         disassembler_needs_relocs for bfd_arch_arm.
 335
 336 2006-01-16  Paul Brook  <paul@codesourcery.com>
 337
 338         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 339         f?add?, and f?sub? instructions.
 340
 341 2006-01-16  Nick Clifton  <nickc@redhat.com>
 342
 343         * po/zh_CN.po: New Chinese (simplified) translation.
 344         * configure.in (ALL_LINGUAS): Add "zh_CH".
 345         * configure: Regenerate.
 346
 347 2006-01-05  Paul Brook  <paul@codesourcery.com>
 348
 349         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 350
 351 2006-01-06  DJ Delorie  <dj@redhat.com>
 352
 353         * m32c-desc.c: Regenerate.
 354         * m32c-opc.c: Regenerate.
 355         * m32c-opc.h: Regenerate.
 356
 357 2006-01-03  DJ Delorie  <dj@redhat.com>
 358
 359         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 360         * m32c-ibld.c: Regenerated.
 361
 362 For older changes see ChangeLog-2005
 363 \f
 364 Local Variables:
 365 mode: change-log
 366 left-margin: 8
 367 fill-column: 74
 368 version-control: never
 369 End: