1 2018-08-21 Alan Modra <amodra@gmail.com>
3 * ppc-dis.c (operand_value_powerpc): Init "invalid".
4 (skip_optional_operands): Count optional operands, and update
5 ppc_optional_operand_value call.
6 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
7 (extract_vlensi): Likewise.
8 (extract_fxm): Return default value for missing optional operand.
9 (extract_ls, extract_raq, extract_tbr): Likewise.
10 (insert_sxl, extract_sxl): New functions.
11 (insert_esync, extract_esync): Remove Power9 handling and simplify.
12 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
14 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
17 2018-08-20 Alan Modra <amodra@gmail.com>
19 * sh-opc.h (MASK): Simplify.
21 2018-08-18 John Darrington <john@darrington.wattle.id.au>
23 * s12z-dis.c (bm_decode): Deal with cases where the mode is
24 BM_RESERVED0 or BM_RESERVED1
25 (bm_rel_decode, bm_n_bytes): Ditto.
27 2018-08-18 John Darrington <john@darrington.wattle.id.au>
31 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
33 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
34 address with the addr32 prefix and without base nor index
37 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
39 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
40 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
41 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
42 (cpu_flags): Add CpuCMOV and CpuFXSR.
43 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
44 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
45 * i386-init.h: Regenerated.
46 * i386-tbl.h: Likewise.
48 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
50 * arc-regs.h: Update auxiliary registers.
52 2018-08-06 Jan Beulich <jbeulich@suse.com>
54 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
55 (RegIP, RegIZ): Define.
56 * i386-reg.tbl: Adjust comments.
57 (rip): Use Qword instead of BaseIndex. Use RegIP.
58 (eip): Use Dword instead of BaseIndex. Use RegIP.
59 (riz): Add Qword. Use RegIZ.
60 (eiz): Add Dword. Use RegIZ.
61 * i386-tbl.h: Re-generate.
63 2018-08-03 Jan Beulich <jbeulich@suse.com>
65 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
66 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
67 vpmovzxdq, vpmovzxwd): Remove NoRex64.
68 * i386-tbl.h: Re-generate.
70 2018-08-03 Jan Beulich <jbeulich@suse.com>
72 * i386-gen.c (operand_types): Remove Mem field.
73 * i386-opc.h (union i386_operand_type): Remove mem field.
74 * i386-init.h, i386-tbl.h: Re-generate.
76 2018-08-01 Alan Modra <amodra@gmail.com>
78 * po/POTFILES.in: Regenerate.
80 2018-07-31 Nick Clifton <nickc@redhat.com>
82 * po/sv.po: Updated Swedish translation.
84 2018-07-31 Jan Beulich <jbeulich@suse.com>
86 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
87 * i386-init.h, i386-tbl.h: Re-generate.
89 2018-07-31 Jan Beulich <jbeulich@suse.com>
91 * i386-opc.h (ZEROING_MASKING) Rename to ...
92 (DYNAMIC_MASKING): ... this. Adjust comment.
93 * i386-opc.tbl (MaskingMorZ): Define.
94 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
95 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
96 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
97 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
98 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
99 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
100 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
101 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
102 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
104 2018-07-31 Jan Beulich <jbeulich@suse.com>
106 * i386-opc.tbl: Use element rather than vector size for AVX512*
107 scatter/gather insns.
108 * i386-tbl.h: Re-generate.
110 2018-07-31 Jan Beulich <jbeulich@suse.com>
112 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
113 (cpu_flags): Drop CpuVREX.
114 * i386-opc.h (CpuVREX): Delete.
115 (union i386_cpu_flags): Remove cpuvrex.
116 * i386-init.h, i386-tbl.h: Re-generate.
118 2018-07-30 Jim Wilson <jimw@sifive.com>
120 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
122 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
124 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
126 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
127 * Makefile.in: Regenerated.
128 * configure.ac: Add C-SKY.
129 * configure: Regenerated.
130 * csky-dis.c: New file.
131 * csky-opc.h: New file.
132 * disassemble.c (ARCH_csky): Define.
133 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
134 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
136 2018-07-27 Alan Modra <amodra@gmail.com>
138 * ppc-opc.c (insert_sprbat): Correct function parameter and
140 (extract_sprbat): Likewise, variable too.
142 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
143 Alan Modra <amodra@gmail.com>
145 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
146 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
147 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
148 support disjointed BAT.
149 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
150 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
151 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
153 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
154 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
156 * i386-gen.c (adjust_broadcast_modifier): New function.
157 (process_i386_opcode_modifier): Add an argument for operands.
158 Adjust the Broadcast value based on operands.
159 (output_i386_opcode): Pass operand_types to
160 process_i386_opcode_modifier.
161 (process_i386_opcodes): Pass NULL as operands to
162 process_i386_opcode_modifier.
163 * i386-opc.h (BYTE_BROADCAST): New.
164 (WORD_BROADCAST): Likewise.
165 (DWORD_BROADCAST): Likewise.
166 (QWORD_BROADCAST): Likewise.
167 (i386_opcode_modifier): Expand broadcast to 3 bits.
168 * i386-tbl.h: Regenerated.
170 2018-07-24 Alan Modra <amodra@gmail.com>
173 * or1k-desc.h: Regenerate.
175 2018-07-24 Jan Beulich <jbeulich@suse.com>
177 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
178 vcvtusi2ss, and vcvtusi2sd.
179 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
180 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
181 * i386-tbl.h: Re-generate.
183 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
185 * arc-opc.c (extract_w6): Fix extending the sign.
187 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
189 * arc-tbl.h (vewt): Allow it for ARC EM family.
191 2018-07-23 Alan Modra <amodra@gmail.com>
194 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
195 opcode variants for mtspr/mfspr encodings.
197 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
198 Maciej W. Rozycki <macro@mips.com>
200 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
201 loongson3a descriptors.
202 (parse_mips_ase_option): Handle -M loongson-mmi option.
203 (print_mips_disassembler_options): Document -M loongson-mmi.
204 * mips-opc.c (LMMI): New macro.
205 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
208 2018-07-19 Jan Beulich <jbeulich@suse.com>
210 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
211 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
212 IgnoreSize and [XYZ]MMword where applicable.
213 * i386-tbl.h: Re-generate.
215 2018-07-19 Jan Beulich <jbeulich@suse.com>
217 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
218 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
219 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
220 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
221 * i386-tbl.h: Re-generate.
223 2018-07-19 Jan Beulich <jbeulich@suse.com>
225 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
226 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
227 VPCLMULQDQ templates into their respective AVX512VL counterparts
228 where possible, using Disp8ShiftVL and CheckRegSize instead of
229 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
230 * i386-tbl.h: Re-generate.
232 2018-07-19 Jan Beulich <jbeulich@suse.com>
234 * i386-opc.tbl: Fold AVX512DQ templates into their respective
235 AVX512VL counterparts where possible, using Disp8ShiftVL and
236 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
237 IgnoreSize) as appropriate.
238 * i386-tbl.h: Re-generate.
240 2018-07-19 Jan Beulich <jbeulich@suse.com>
242 * i386-opc.tbl: Fold AVX512BW templates into their respective
243 AVX512VL counterparts where possible, using Disp8ShiftVL and
244 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
245 IgnoreSize) as appropriate.
246 * i386-tbl.h: Re-generate.
248 2018-07-19 Jan Beulich <jbeulich@suse.com>
250 * i386-opc.tbl: Fold AVX512CD templates into their respective
251 AVX512VL counterparts where possible, using Disp8ShiftVL and
252 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
253 IgnoreSize) as appropriate.
254 * i386-tbl.h: Re-generate.
256 2018-07-19 Jan Beulich <jbeulich@suse.com>
258 * i386-opc.h (DISP8_SHIFT_VL): New.
259 * i386-opc.tbl (Disp8ShiftVL): Define.
260 (various): Fold AVX512VL templates into their respective
261 AVX512F counterparts where possible, using Disp8ShiftVL and
262 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
263 IgnoreSize) as appropriate.
264 * i386-tbl.h: Re-generate.
266 2018-07-19 Jan Beulich <jbeulich@suse.com>
268 * Makefile.am: Change dependencies and rule for
269 $(srcdir)/i386-init.h.
270 * Makefile.in: Re-generate.
271 * i386-gen.c (process_i386_opcodes): New local variable
272 "marker". Drop opening of input file. Recognize marker and line
274 * i386-opc.tbl (OPCODE_I386_H): Define.
275 (i386-opc.h): Include it.
278 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
281 * i386-opc.h (Byte): Update comments.
290 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
292 * i386-tbl.h: Regenerated.
294 2018-07-12 Sudakshina Das <sudi.das@arm.com>
296 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
297 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
298 * aarch64-asm-2.c: Regenerate.
299 * aarch64-dis-2.c: Regenerate.
300 * aarch64-opc-2.c: Regenerate.
302 2018-07-12 Tamar Christina <tamar.christina@arm.com>
305 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
306 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
307 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
308 sqdmulh, sqrdmulh): Use Em16.
310 2018-07-11 Sudakshina Das <sudi.das@arm.com>
312 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
313 csdb together with them.
314 (thumb32_opcodes): Likewise.
316 2018-07-11 Jan Beulich <jbeulich@suse.com>
318 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
319 requiring 32-bit registers as operands 2 and 3. Improve
321 (mwait, mwaitx): Fold templates. Improve comments.
322 OPERAND_TYPE_INOUTPORTREG.
323 * i386-tbl.h: Re-generate.
325 2018-07-11 Jan Beulich <jbeulich@suse.com>
327 * i386-gen.c (operand_type_init): Remove
328 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
329 OPERAND_TYPE_INOUTPORTREG.
330 * i386-init.h: Re-generate.
332 2018-07-11 Jan Beulich <jbeulich@suse.com>
334 * i386-opc.tbl (wrssd, wrussd): Add Dword.
335 (wrssq, wrussq): Add Qword.
336 * i386-tbl.h: Re-generate.
338 2018-07-11 Jan Beulich <jbeulich@suse.com>
340 * i386-opc.h: Rename OTMax to OTNum.
341 (OTNumOfUints): Adjust calculation.
342 (OTUnused): Directly alias to OTNum.
344 2018-07-09 Maciej W. Rozycki <macro@mips.com>
346 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
348 (lea_reg_xys): Likewise.
349 (print_insn_loop_primitive): Rename `reg' local variable to
352 2018-07-06 Tamar Christina <tamar.christina@arm.com>
355 * aarch64-tbl.h (ldarh): Fix disassembly mask.
357 2018-07-06 Tamar Christina <tamar.christina@arm.com>
360 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
361 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
363 2018-07-02 Maciej W. Rozycki <macro@mips.com>
366 * mips-dis.c (mips_option_arg_t): New enumeration.
367 (mips_options): New variable.
368 (disassembler_options_mips): New function.
369 (print_mips_disassembler_options): Reimplement in terms of
370 `disassembler_options_mips'.
371 * arm-dis.c (disassembler_options_arm): Adapt to using the
372 `disasm_options_and_args_t' structure.
373 * ppc-dis.c (disassembler_options_powerpc): Likewise.
374 * s390-dis.c (disassembler_options_s390): Likewise.
376 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
378 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
380 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
381 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
382 * testsuite/ld-arm/tls-longplt.d: Likewise.
384 2018-06-29 Tamar Christina <tamar.christina@arm.com>
387 * aarch64-asm-2.c: Regenerate.
388 * aarch64-dis-2.c: Likewise.
389 * aarch64-opc-2.c: Likewise.
390 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
391 * aarch64-opc.c (operand_general_constraint_met_p,
392 aarch64_print_operand): Likewise.
393 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
394 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
396 (AARCH64_OPERANDS): Add Em2.
398 2018-06-26 Nick Clifton <nickc@redhat.com>
400 * po/uk.po: Updated Ukranian translation.
401 * po/de.po: Updated German translation.
402 * po/pt_BR.po: Updated Brazilian Portuguese translation.
404 2018-06-26 Nick Clifton <nickc@redhat.com>
406 * nfp-dis.c: Fix spelling mistake.
408 2018-06-24 Nick Clifton <nickc@redhat.com>
410 * configure: Regenerate.
411 * po/opcodes.pot: Regenerate.
413 2018-06-24 Nick Clifton <nickc@redhat.com>
417 2018-06-19 Tamar Christina <tamar.christina@arm.com>
419 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
420 * aarch64-asm-2.c: Regenerate.
421 * aarch64-dis-2.c: Likewise.
423 2018-06-21 Maciej W. Rozycki <macro@mips.com>
425 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
426 `-M ginv' option description.
428 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
431 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
434 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
436 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
437 * configure.ac: Remove AC_PREREQ.
438 * Makefile.in: Re-generate.
439 * aclocal.m4: Re-generate.
440 * configure: Re-generate.
442 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
444 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
445 mips64r6 descriptors.
446 (parse_mips_ase_option): Handle -Mginv option.
447 (print_mips_disassembler_options): Document -Mginv.
448 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
450 (mips_opcodes): Define ginvi and ginvt.
452 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
453 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
455 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
456 * mips-opc.c (CRC, CRC64): New macros.
457 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
458 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
461 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
464 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
465 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
467 2018-06-06 Alan Modra <amodra@gmail.com>
469 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
470 setjmp. Move init for some other vars later too.
472 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
474 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
475 (dis_private): Add new fields for property section tracking.
476 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
477 (xtensa_instruction_fits): New functions.
478 (fetch_data): Bump minimal fetch size to 4.
479 (print_insn_xtensa): Make struct dis_private static.
480 Load and prepare property table on section change.
481 Don't disassemble literals. Don't disassemble instructions that
482 cross property table boundaries.
484 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
486 * configure: Regenerated.
488 2018-06-01 Jan Beulich <jbeulich@suse.com>
490 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
491 * i386-tbl.h: Re-generate.
493 2018-06-01 Jan Beulich <jbeulich@suse.com>
495 * i386-opc.tbl (sldt, str): Add NoRex64.
496 * i386-tbl.h: Re-generate.
498 2018-06-01 Jan Beulich <jbeulich@suse.com>
500 * i386-opc.tbl (invpcid): Add Oword.
501 * i386-tbl.h: Re-generate.
503 2018-06-01 Alan Modra <amodra@gmail.com>
505 * sysdep.h (_bfd_error_handler): Don't declare.
506 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
507 * rl78-decode.opc: Likewise.
508 * msp430-decode.c: Regenerate.
509 * rl78-decode.c: Regenerate.
511 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
513 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
514 * i386-init.h : Regenerated.
516 2018-05-25 Alan Modra <amodra@gmail.com>
518 * Makefile.in: Regenerate.
519 * po/POTFILES.in: Regenerate.
521 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
523 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
524 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
525 (insert_bab, extract_bab, insert_btab, extract_btab,
526 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
527 (BAT, BBA VBA RBS XB6S): Delete macros.
528 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
529 (BB, BD, RBX, XC6): Update for new macros.
530 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
531 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
532 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
533 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
535 2018-05-18 John Darrington <john@darrington.wattle.id.au>
537 * Makefile.am: Add support for s12z architecture.
538 * configure.ac: Likewise.
539 * disassemble.c: Likewise.
540 * disassemble.h: Likewise.
541 * Makefile.in: Regenerate.
542 * configure: Regenerate.
543 * s12z-dis.c: New file.
546 2018-05-18 Alan Modra <amodra@gmail.com>
548 * nfp-dis.c: Don't #include libbfd.h.
549 (init_nfp3200_priv): Use bfd_get_section_contents.
550 (nit_nfp6000_mecsr_sec): Likewise.
552 2018-05-17 Nick Clifton <nickc@redhat.com>
554 * po/zh_CN.po: Updated simplified Chinese translation.
556 2018-05-16 Tamar Christina <tamar.christina@arm.com>
559 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
560 * aarch64-dis-2.c: Regenerate.
562 2018-05-15 Tamar Christina <tamar.christina@arm.com>
565 * aarch64-asm.c (opintl.h): Include.
566 (aarch64_ins_sysreg): Enforce read/write constraints.
567 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
568 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
569 (F_REG_READ, F_REG_WRITE): New.
570 * aarch64-opc.c (aarch64_print_operand): Generate notes for
572 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
573 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
574 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
575 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
576 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
577 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
578 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
579 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
580 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
581 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
582 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
583 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
584 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
585 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
586 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
587 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
588 msr (F_SYS_WRITE), mrs (F_SYS_READ).
590 2018-05-15 Tamar Christina <tamar.christina@arm.com>
593 * aarch64-dis.c (no_notes: New.
594 (parse_aarch64_dis_option): Support notes.
595 (aarch64_decode_insn, print_operands): Likewise.
596 (print_aarch64_disassembler_options): Document notes.
597 * aarch64-opc.c (aarch64_print_operand): Support notes.
599 2018-05-15 Tamar Christina <tamar.christina@arm.com>
602 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
603 and take error struct.
604 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
605 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
606 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
607 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
608 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
609 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
610 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
611 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
612 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
613 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
614 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
615 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
616 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
617 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
618 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
619 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
620 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
621 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
622 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
623 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
624 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
625 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
626 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
627 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
628 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
629 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
630 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
631 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
632 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
633 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
634 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
635 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
636 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
637 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
638 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
639 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
640 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
641 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
642 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
643 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
644 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
645 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
646 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
647 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
648 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
649 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
650 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
651 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
652 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
653 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
654 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
655 (determine_disassembling_preference, aarch64_decode_insn,
656 print_insn_aarch64_word, print_insn_data): Take errors struct.
657 (print_insn_aarch64): Use errors.
658 * aarch64-asm-2.c: Regenerate.
659 * aarch64-dis-2.c: Regenerate.
660 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
661 boolean in aarch64_insert_operan.
662 (print_operand_extractor): Likewise.
663 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
665 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
667 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
669 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
671 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
673 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
675 * cr16-opc.c (cr16_instruction): Comment typo fix.
676 * hppa-dis.c (print_insn_hppa): Likewise.
678 2018-05-08 Jim Wilson <jimw@sifive.com>
680 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
681 (match_c_slli64, match_srxi_as_c_srxi): New.
682 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
683 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
684 <c.slli, c.srli, c.srai>: Use match_s_slli.
685 <c.slli64, c.srli64, c.srai64>: New.
687 2018-05-08 Alan Modra <amodra@gmail.com>
689 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
690 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
691 partition opcode space for index lookup.
693 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
695 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
696 <insn_length>: ...with this. Update usage.
697 Remove duplicate call to *info->memory_error_func.
699 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
700 H.J. Lu <hongjiu.lu@intel.com>
702 * i386-dis.c (Gva): New.
703 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
704 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
705 (prefix_table): New instructions (see prefix above).
706 (mod_table): New instructions (see prefix above).
707 (OP_G): Handle va_mode.
708 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
710 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
711 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
712 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
713 * i386-opc.tbl: Add movidir{i,64b}.
714 * i386-init.h: Regenerated.
715 * i386-tbl.h: Likewise.
717 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
719 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
721 * i386-opc.h (AddrPrefixOp0): Renamed to ...
722 (AddrPrefixOpReg): This.
723 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
724 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
726 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
728 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
729 (vle_num_opcodes): Likewise.
730 (spe2_num_opcodes): Likewise.
731 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
733 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
734 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
737 2018-05-01 Tamar Christina <tamar.christina@arm.com>
739 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
741 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
743 Makefile.am: Added nfp-dis.c.
744 configure.ac: Added bfd_nfp_arch.
745 disassemble.h: Added print_insn_nfp prototype.
746 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
747 nfp-dis.c: New, for NFP support.
748 po/POTFILES.in: Added nfp-dis.c to the list.
749 Makefile.in: Regenerate.
750 configure: Regenerate.
752 2018-04-26 Jan Beulich <jbeulich@suse.com>
754 * i386-opc.tbl: Fold various non-memory operand AVX512VL
755 templates into their base ones.
756 * i386-tlb.h: Re-generate.
758 2018-04-26 Jan Beulich <jbeulich@suse.com>
760 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
761 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
762 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
763 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
764 * i386-init.h: Re-generate.
766 2018-04-26 Jan Beulich <jbeulich@suse.com>
768 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
769 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
770 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
771 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
773 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
775 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
777 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
778 cpuregzmm, and cpuregmask.
779 * i386-init.h: Re-generate.
780 * i386-tbl.h: Re-generate.
782 2018-04-26 Jan Beulich <jbeulich@suse.com>
784 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
785 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
786 * i386-init.h: Re-generate.
788 2018-04-26 Jan Beulich <jbeulich@suse.com>
790 * i386-gen.c (VexImmExt): Delete.
791 * i386-opc.h (VexImmExt, veximmext): Delete.
792 * i386-opc.tbl: Drop all VexImmExt uses.
793 * i386-tlb.h: Re-generate.
795 2018-04-25 Jan Beulich <jbeulich@suse.com>
797 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
799 * i386-tlb.h: Re-generate.
801 2018-04-25 Tamar Christina <tamar.christina@arm.com>
803 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
805 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
807 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
809 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
810 (cpu_flags): Add CpuCLDEMOTE.
811 * i386-init.h: Regenerate.
812 * i386-opc.h (enum): Add CpuCLDEMOTE,
813 (i386_cpu_flags): Add cpucldemote.
814 * i386-opc.tbl: Add cldemote.
815 * i386-tbl.h: Regenerate.
817 2018-04-16 Alan Modra <amodra@gmail.com>
819 * Makefile.am: Remove sh5 and sh64 support.
820 * configure.ac: Likewise.
821 * disassemble.c: Likewise.
822 * disassemble.h: Likewise.
823 * sh-dis.c: Likewise.
824 * sh64-dis.c: Delete.
825 * sh64-opc.c: Delete.
826 * sh64-opc.h: Delete.
827 * Makefile.in: Regenerate.
828 * configure: Regenerate.
829 * po/POTFILES.in: Regenerate.
831 2018-04-16 Alan Modra <amodra@gmail.com>
833 * Makefile.am: Remove w65 support.
834 * configure.ac: Likewise.
835 * disassemble.c: Likewise.
836 * disassemble.h: Likewise.
839 * Makefile.in: Regenerate.
840 * configure: Regenerate.
841 * po/POTFILES.in: Regenerate.
843 2018-04-16 Alan Modra <amodra@gmail.com>
845 * configure.ac: Remove we32k support.
846 * configure: Regenerate.
848 2018-04-16 Alan Modra <amodra@gmail.com>
850 * Makefile.am: Remove m88k support.
851 * configure.ac: Likewise.
852 * disassemble.c: Likewise.
853 * disassemble.h: Likewise.
854 * m88k-dis.c: Delete.
855 * Makefile.in: Regenerate.
856 * configure: Regenerate.
857 * po/POTFILES.in: Regenerate.
859 2018-04-16 Alan Modra <amodra@gmail.com>
861 * Makefile.am: Remove i370 support.
862 * configure.ac: Likewise.
863 * disassemble.c: Likewise.
864 * disassemble.h: Likewise.
865 * i370-dis.c: Delete.
866 * i370-opc.c: Delete.
867 * Makefile.in: Regenerate.
868 * configure: Regenerate.
869 * po/POTFILES.in: Regenerate.
871 2018-04-16 Alan Modra <amodra@gmail.com>
873 * Makefile.am: Remove h8500 support.
874 * configure.ac: Likewise.
875 * disassemble.c: Likewise.
876 * disassemble.h: Likewise.
877 * h8500-dis.c: Delete.
878 * h8500-opc.h: Delete.
879 * Makefile.in: Regenerate.
880 * configure: Regenerate.
881 * po/POTFILES.in: Regenerate.
883 2018-04-16 Alan Modra <amodra@gmail.com>
885 * configure.ac: Remove tahoe support.
886 * configure: Regenerate.
888 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
890 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
892 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
894 * i386-tbl.h: Regenerated.
896 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
898 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
899 PREFIX_MOD_1_0FAE_REG_6.
901 (OP_E_register): Use va_mode.
902 * i386-dis-evex.h (prefix_table):
903 New instructions (see prefixes above).
904 * i386-gen.c (cpu_flag_init): Add WAITPKG.
905 (cpu_flags): Likewise.
906 * i386-opc.h (enum): Likewise.
907 (i386_cpu_flags): Likewise.
908 * i386-opc.tbl: Add umonitor, umwait, tpause.
909 * i386-init.h: Regenerate.
910 * i386-tbl.h: Likewise.
912 2018-04-11 Alan Modra <amodra@gmail.com>
914 * opcodes/i860-dis.c: Delete.
915 * opcodes/i960-dis.c: Delete.
916 * Makefile.am: Remove i860 and i960 support.
917 * configure.ac: Likewise.
918 * disassemble.c: Likewise.
919 * disassemble.h: Likewise.
920 * Makefile.in: Regenerate.
921 * configure: Regenerate.
922 * po/POTFILES.in: Regenerate.
924 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
927 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
929 (print_insn): Clear vex instead of vex.evex.
931 2018-04-04 Nick Clifton <nickc@redhat.com>
933 * po/es.po: Updated Spanish translation.
935 2018-03-28 Jan Beulich <jbeulich@suse.com>
937 * i386-gen.c (opcode_modifiers): Delete VecESize.
938 * i386-opc.h (VecESize): Delete.
939 (struct i386_opcode_modifier): Delete vecesize.
940 * i386-opc.tbl: Drop VecESize.
941 * i386-tlb.h: Re-generate.
943 2018-03-28 Jan Beulich <jbeulich@suse.com>
945 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
946 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
947 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
948 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
949 * i386-tlb.h: Re-generate.
951 2018-03-28 Jan Beulich <jbeulich@suse.com>
953 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
955 * i386-tlb.h: Re-generate.
957 2018-03-28 Jan Beulich <jbeulich@suse.com>
959 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
960 (vex_len_table): Drop Y for vcvt*2si.
961 (putop): Replace plain 'Y' handling by abort().
963 2018-03-28 Nick Clifton <nickc@redhat.com>
966 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
967 instructions with only a base address register.
968 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
969 handle AARHC64_OPND_SVE_ADDR_R.
970 (aarch64_print_operand): Likewise.
971 * aarch64-asm-2.c: Regenerate.
972 * aarch64_dis-2.c: Regenerate.
973 * aarch64-opc-2.c: Regenerate.
975 2018-03-22 Jan Beulich <jbeulich@suse.com>
977 * i386-opc.tbl: Drop VecESize from register only insn forms and
978 memory forms not allowing broadcast.
979 * i386-tlb.h: Re-generate.
981 2018-03-22 Jan Beulich <jbeulich@suse.com>
983 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
984 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
985 sha256*): Drop Disp<N>.
987 2018-03-22 Jan Beulich <jbeulich@suse.com>
989 * i386-dis.c (EbndS, bnd_swap_mode): New.
990 (prefix_table): Use EbndS.
991 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
992 * i386-opc.tbl (bndmov): Move misplaced Load.
993 * i386-tlb.h: Re-generate.
995 2018-03-22 Jan Beulich <jbeulich@suse.com>
997 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
998 templates allowing memory operands and folded ones for register
1000 * i386-tlb.h: Re-generate.
1002 2018-03-22 Jan Beulich <jbeulich@suse.com>
1004 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1005 256-bit templates. Drop redundant leftover Disp<N>.
1006 * i386-tlb.h: Re-generate.
1008 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1010 * riscv-opc.c (riscv_insn_types): New.
1012 2018-03-13 Nick Clifton <nickc@redhat.com>
1014 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1016 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1018 * i386-opc.tbl: Add Optimize to clr.
1019 * i386-tbl.h: Regenerated.
1021 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1023 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1024 * i386-opc.h (OldGcc): Removed.
1025 (i386_opcode_modifier): Remove oldgcc.
1026 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1027 instructions for old (<= 2.8.1) versions of gcc.
1028 * i386-tbl.h: Regenerated.
1030 2018-03-08 Jan Beulich <jbeulich@suse.com>
1032 * i386-opc.h (EVEXDYN): New.
1033 * i386-opc.tbl: Fold various AVX512VL templates.
1034 * i386-tlb.h: Re-generate.
1036 2018-03-08 Jan Beulich <jbeulich@suse.com>
1038 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1039 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1040 vpexpandd, vpexpandq): Fold AFX512VF templates.
1041 * i386-tlb.h: Re-generate.
1043 2018-03-08 Jan Beulich <jbeulich@suse.com>
1045 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1046 Fold 128- and 256-bit VEX-encoded templates.
1047 * i386-tlb.h: Re-generate.
1049 2018-03-08 Jan Beulich <jbeulich@suse.com>
1051 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1052 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1053 vpexpandd, vpexpandq): Fold AVX512F templates.
1054 * i386-tlb.h: Re-generate.
1056 2018-03-08 Jan Beulich <jbeulich@suse.com>
1058 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1059 64-bit templates. Drop Disp<N>.
1060 * i386-tlb.h: Re-generate.
1062 2018-03-08 Jan Beulich <jbeulich@suse.com>
1064 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1065 and 256-bit templates.
1066 * i386-tlb.h: Re-generate.
1068 2018-03-08 Jan Beulich <jbeulich@suse.com>
1070 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1071 * i386-tlb.h: Re-generate.
1073 2018-03-08 Jan Beulich <jbeulich@suse.com>
1075 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1077 * i386-tlb.h: Re-generate.
1079 2018-03-08 Jan Beulich <jbeulich@suse.com>
1081 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1082 * i386-tlb.h: Re-generate.
1084 2018-03-08 Jan Beulich <jbeulich@suse.com>
1086 * i386-gen.c (opcode_modifiers): Delete FloatD.
1087 * i386-opc.h (FloatD): Delete.
1088 (struct i386_opcode_modifier): Delete floatd.
1089 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1091 * i386-tlb.h: Re-generate.
1093 2018-03-08 Jan Beulich <jbeulich@suse.com>
1095 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1097 2018-03-08 Jan Beulich <jbeulich@suse.com>
1099 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1100 * i386-tlb.h: Re-generate.
1102 2018-03-08 Jan Beulich <jbeulich@suse.com>
1104 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1106 * i386-tlb.h: Re-generate.
1108 2018-03-07 Alan Modra <amodra@gmail.com>
1110 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1112 * disassemble.h (print_insn_rs6000): Delete.
1113 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1114 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1115 (print_insn_rs6000): Delete.
1117 2018-03-03 Alan Modra <amodra@gmail.com>
1119 * sysdep.h (opcodes_error_handler): Define.
1120 (_bfd_error_handler): Declare.
1121 * Makefile.am: Remove stray #.
1122 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1124 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1125 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1126 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1127 opcodes_error_handler to print errors. Standardize error messages.
1128 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1129 and include opintl.h.
1130 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1131 * i386-gen.c: Standardize error messages.
1132 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1133 * Makefile.in: Regenerate.
1134 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1135 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1136 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1137 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1138 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1139 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1140 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1141 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1142 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1143 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1144 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1145 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1146 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1148 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1150 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1151 vpsub[bwdq] instructions.
1152 * i386-tbl.h: Regenerated.
1154 2018-03-01 Alan Modra <amodra@gmail.com>
1156 * configure.ac (ALL_LINGUAS): Sort.
1157 * configure: Regenerate.
1159 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1161 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1162 macro by assignements.
1164 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1167 * i386-gen.c (opcode_modifiers): Add Optimize.
1168 * i386-opc.h (Optimize): New enum.
1169 (i386_opcode_modifier): Add optimize.
1170 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1171 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1172 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1173 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1174 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1176 * i386-tbl.h: Regenerated.
1178 2018-02-26 Alan Modra <amodra@gmail.com>
1180 * crx-dis.c (getregliststring): Allocate a large enough buffer
1181 to silence false positive gcc8 warning.
1183 2018-02-22 Shea Levy <shea@shealevy.com>
1185 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1187 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1189 * i386-opc.tbl: Add {rex},
1190 * i386-tbl.h: Regenerated.
1192 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1194 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1195 (mips16_opcodes): Replace `M' with `m' for "restore".
1197 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1199 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1201 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1203 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1204 variable to `function_index'.
1206 2018-02-13 Nick Clifton <nickc@redhat.com>
1209 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1210 about truncation of printing.
1212 2018-02-12 Henry Wong <henry@stuffedcow.net>
1214 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1216 2018-02-05 Nick Clifton <nickc@redhat.com>
1218 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1220 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1222 * i386-dis.c (enum): Add pconfig.
1223 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1224 (cpu_flags): Add CpuPCONFIG.
1225 * i386-opc.h (enum): Add CpuPCONFIG.
1226 (i386_cpu_flags): Add cpupconfig.
1227 * i386-opc.tbl: Add PCONFIG instruction.
1228 * i386-init.h: Regenerate.
1229 * i386-tbl.h: Likewise.
1231 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1233 * i386-dis.c (enum): Add PREFIX_0F09.
1234 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1235 (cpu_flags): Add CpuWBNOINVD.
1236 * i386-opc.h (enum): Add CpuWBNOINVD.
1237 (i386_cpu_flags): Add cpuwbnoinvd.
1238 * i386-opc.tbl: Add WBNOINVD instruction.
1239 * i386-init.h: Regenerate.
1240 * i386-tbl.h: Likewise.
1242 2018-01-17 Jim Wilson <jimw@sifive.com>
1244 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1246 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1248 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1249 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1250 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1251 (cpu_flags): Add CpuIBT, CpuSHSTK.
1252 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1253 (i386_cpu_flags): Add cpuibt, cpushstk.
1254 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1255 * i386-init.h: Regenerate.
1256 * i386-tbl.h: Likewise.
1258 2018-01-16 Nick Clifton <nickc@redhat.com>
1260 * po/pt_BR.po: Updated Brazilian Portugese translation.
1261 * po/de.po: Updated German translation.
1263 2018-01-15 Jim Wilson <jimw@sifive.com>
1265 * riscv-opc.c (match_c_nop): New.
1266 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1268 2018-01-15 Nick Clifton <nickc@redhat.com>
1270 * po/uk.po: Updated Ukranian translation.
1272 2018-01-13 Nick Clifton <nickc@redhat.com>
1274 * po/opcodes.pot: Regenerated.
1276 2018-01-13 Nick Clifton <nickc@redhat.com>
1278 * configure: Regenerate.
1280 2018-01-13 Nick Clifton <nickc@redhat.com>
1282 2.30 branch created.
1284 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1286 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1287 * i386-tbl.h: Regenerate.
1289 2018-01-10 Jan Beulich <jbeulich@suse.com>
1291 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1292 * i386-tbl.h: Re-generate.
1294 2018-01-10 Jan Beulich <jbeulich@suse.com>
1296 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1297 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1298 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1299 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1300 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1301 Disp8MemShift of AVX512VL forms.
1302 * i386-tbl.h: Re-generate.
1304 2018-01-09 Jim Wilson <jimw@sifive.com>
1306 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1307 then the hi_addr value is zero.
1309 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1311 * arm-dis.c (arm_opcodes): Add csdb.
1312 (thumb32_opcodes): Add csdb.
1314 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1316 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1317 * aarch64-asm-2.c: Regenerate.
1318 * aarch64-dis-2.c: Regenerate.
1319 * aarch64-opc-2.c: Regenerate.
1321 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1324 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1325 Remove AVX512 vmovd with 64-bit operands.
1326 * i386-tbl.h: Regenerated.
1328 2018-01-05 Jim Wilson <jimw@sifive.com>
1330 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1333 2018-01-03 Alan Modra <amodra@gmail.com>
1335 Update year range in copyright notice of all files.
1337 2018-01-02 Jan Beulich <jbeulich@suse.com>
1339 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1340 and OPERAND_TYPE_REGZMM entries.
1342 For older changes see ChangeLog-2017
1344 Copyright (C) 2018 Free Software Foundation, Inc.
1346 Copying and distribution of this file, with or without modification,
1347 are permitted in any medium without royalty provided the copyright
1348 notice and this notice are preserved.
1354 version-control: never