1 2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-gen.c (opcode_modifiers): Replace VexOpcode with
5 * i386-opc.h (VexOpcode): Renamed to ...
8 (PREFIX_0X66): Likewise.
9 (PREFIX_0XF2): Likewise.
10 (PREFIX_0XF3): Likewise.
11 * i386-opc.tbl (Prefix_0X66): New.
12 (Prefix_0XF2): Likewise.
13 (Prefix_0XF3): Likewise.
14 Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
15 Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
16 * i386-tbl.h: Regenerated.
18 2020-10-05 Samanta Navarro <ferivoz@riseup.net>
20 * cgen-asm.c: Fix spelling mistakes.
21 * cgen-dis.c: Fix spelling mistakes.
22 * tic30-dis.c: Fix spelling mistakes.
24 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
27 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
29 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
32 * i386-dis.c (print_insn): Clear modrm if not needed.
33 (putop): Check need_modrm for modrm.mod != 3. Don't check
34 need_modrm for modrm.mod == 3.
36 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
38 * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
39 TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
40 TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
41 TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
42 TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
43 TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
44 TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
45 TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
46 WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
47 TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
48 TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
49 TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
50 TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
51 TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
53 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
55 * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
57 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
59 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
60 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
62 2020-09-26 Alan Modra <amodra@gmail.com>
64 * csky-opc.h: Formatting.
65 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
66 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
68 (get_register_number): Likewise.
69 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
71 2020-09-24 Lili Cui <lili.cui@intel.com>
74 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
76 2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
78 * csky-dis.c (csky_output_operand): Enclose body of if in curly
81 2020-09-24 Lili Cui <lili.cui@intel.com>
83 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
84 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
85 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
86 X86_64_0F01_REG_1_RM_7_P_2.
87 (prefix_table): Likewise.
88 (x86_64_table): Likewise.
90 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
91 and CPU_ANY_TDX_FLAGS.
92 (cpu_flags): Add CpuTDX.
93 * i386-opc.h (enum): Add CpuTDX.
94 (i386_cpu_flags): Add cputdx.
95 * i386-opc.tbl: Add TDX insns.
96 * i386-init.h: Regenerate.
97 * i386-tbl.h: Likewise.
99 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
101 * csky-dis.c (using_abi): New.
102 (parse_csky_dis_options): New function.
103 (get_gr_name): New function.
104 (get_cr_name): New function.
105 (csky_output_operand): Use get_gr_name and get_cr_name to
106 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
107 (print_insn_csky): Parse disassembler options.
108 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
109 (GENARAL_REG_BANK): Define.
110 (REG_SUPPORT_ALL): Define.
111 (REG_SUPPORT_ALL): New.
113 (REG_SUPPORT_A): Define.
114 (REG_SUPPORT_B): Define.
115 (REG_SUPPORT_C): Define.
116 (REG_SUPPORT_D): Define.
117 (REG_SUPPORT_E): Define.
118 (csky_abiv1_general_regs): New.
119 (csky_abiv1_control_regs): New.
120 (csky_abiv2_general_regs): New.
121 (csky_abiv2_control_regs): New.
122 (get_register_name): New function.
123 (get_register_number): New function.
124 (csky_get_general_reg_name): New function.
125 (csky_get_general_regno): New function.
126 (csky_get_control_reg_name): New function.
127 (csky_get_control_regno): New function.
128 (csky_v2_opcodes): Prefer two oprerans format for bclri and
129 bseti, strengthen the operands legality check of addc, zext
132 2020-09-23 Lili Cui <lili.cui@intel.com>
134 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
135 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
136 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
137 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
138 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
139 (reg_table): New instructions (see prefixes above).
140 (prefix_table): Likewise.
141 (three_byte_table): Likewise.
142 (mod_table): Likewise
143 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
144 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
145 (cpu_flags): Likewise.
146 (operand_type_init): Likewise.
147 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
148 (i386_cpu_flags): Add cpukl and cpuwide_kl.
149 * i386-opc.tbl: Add KL and WIDE_KL insns.
150 * i386-init.h: Regenerate.
151 * i386-tbl.h: Likewise.
153 2020-09-21 Alan Modra <amodra@gmail.com>
155 * rx-dis.c (flag_names): Add missing comma.
156 (register_names, flag_names, double_register_names),
157 (double_register_high_names, double_register_low_names),
158 (double_control_register_names, double_condition_names): Remove
161 2020-09-18 David Faust <david.faust@oracle.com>
163 * bpf-desc.c: Regenerate.
164 * bpf-desc.h: Likewise.
165 * bpf-opc.c: Likewise.
166 * bpf-opc.h: Likewise.
168 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
170 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
173 2020-09-16 Alan Modra <amodra@gmail.com>
175 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
177 2020-09-10 Nick Clifton <nickc@redhat.com>
179 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
180 for hidden, local, no-type symbols.
181 (disassemble_init_powerpc): Point the symbol_is_valid field in the
182 info structure at the new function.
184 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
186 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
187 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
190 2020-09-10 Nick Clifton <nickc@redhat.com>
192 * csky-dis.c (csky_output_operand): Coerce the immediate values to
193 long before printing.
195 2020-09-10 Alan Modra <amodra@gmail.com>
197 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
199 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
201 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
204 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
206 * csky-dis.c (csky_output_operand): Add handlers for
207 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
208 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
209 to support FPUV3 instructions.
210 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
211 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
212 OPRND_TYPE_DFLOAT_FMOVI.
213 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
214 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
215 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
216 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
217 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
218 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
219 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
220 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
221 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
222 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
223 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
224 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
225 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
226 (csky_v2_opcodes): Add FPUV3 instructions.
228 2020-09-08 Alex Coplan <alex.coplan@arm.com>
230 * aarch64-dis.c (print_operands): Pass CPU features to
231 aarch64_print_operand().
232 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
233 preferred disassembly of system registers.
234 (SR_RNG): Refactor to use new SR_FEAT2 macro.
240 (SR_EXPAND_ELx): New.
241 (SR_EXPAND_EL12): New.
242 (aarch64_sys_regs): Specify which registers are only on
243 A-profile, add R-profile system registers.
247 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
250 2020-09-08 Alex Coplan <alex.coplan@arm.com>
252 * aarch64-tbl.h (aarch64_feature_v8_r): New.
255 (aarch64_opcode_table): Add dfb.
256 * aarch64-opc-2.c: Regenerate.
257 * aarch64-asm-2.c: Regenerate.
258 * aarch64-dis-2.c: Regenerate.
260 2020-09-08 Alex Coplan <alex.coplan@arm.com>
262 * aarch64-dis.c (arch_variant): New.
263 (determine_disassembling_preference): Disassemble according to
265 (select_aarch64_variant): New.
266 (print_insn_aarch64): Set feature set.
268 2020-09-02 Alan Modra <amodra@gmail.com>
270 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
271 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
272 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
273 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
274 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
275 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
276 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
277 for value parameter and update code to suit.
278 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
279 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
281 2020-09-02 Alan Modra <amodra@gmail.com>
283 * i386-dis.c (OP_E_memory): Don't cast to signed type when
285 (get32, get32s): Use unsigned types in shift expressions.
287 2020-09-02 Alan Modra <amodra@gmail.com>
289 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
291 2020-09-02 Alan Modra <amodra@gmail.com>
293 * crx-dis.c: Whitespace.
294 (print_arg): Use unsigned type for longdisp and mask variables,
295 and for left shift constant.
297 2020-09-02 Alan Modra <amodra@gmail.com>
299 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
300 * bpf-ibld.c: Regenerate.
301 * epiphany-ibld.c: Regenerate.
302 * fr30-ibld.c: Regenerate.
303 * frv-ibld.c: Regenerate.
304 * ip2k-ibld.c: Regenerate.
305 * iq2000-ibld.c: Regenerate.
306 * lm32-ibld.c: Regenerate.
307 * m32c-ibld.c: Regenerate.
308 * m32r-ibld.c: Regenerate.
309 * mep-ibld.c: Regenerate.
310 * mt-ibld.c: Regenerate.
311 * or1k-ibld.c: Regenerate.
312 * xc16x-ibld.c: Regenerate.
313 * xstormy16-ibld.c: Regenerate.
315 2020-09-02 Alan Modra <amodra@gmail.com>
317 * bfin-dis.c (MASKBITS): Use SIGNBIT.
319 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
321 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
322 to CSKYV2_ISA_3E3R3 instruction set.
324 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
326 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
328 2020-09-01 Alan Modra <amodra@gmail.com>
330 * mep-ibld.c: Regenerate.
332 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
334 * csky-dis.c (csky_output_operand): Assign dis_info.value for
337 2020-08-30 Alan Modra <amodra@gmail.com>
339 * cr16-dis.c: Formatting.
340 (parameter): Delete struct typedef. Use dwordU instead
342 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
344 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
346 2020-08-29 Alan Modra <amodra@gmail.com>
349 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
350 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
352 2020-08-28 Alan Modra <amodra@gmail.com>
356 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
357 (extract_normal): Likewise.
358 (insert_normal): Likewise, and move past zero length test.
359 (put_insn_int_value): Handle mask for zero length, use 1UL.
360 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
361 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
362 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
363 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
365 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
367 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
368 (csky_dis_info): Add member isa.
369 (csky_find_inst_info): Skip instructions that do not belong to
371 (csky_get_disassembler): Get infomation from attribute section.
372 (print_insn_csky): Set defualt ISA flag.
373 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
374 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
375 isa_flag32'type to unsigned 64 bits.
377 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
379 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
381 2020-08-26 David Faust <david.faust@oracle.com>
383 * bpf-desc.c: Regenerate.
384 * bpf-desc.h: Likewise.
385 * bpf-opc.c: Likewise.
386 * bpf-opc.h: Likewise.
387 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
388 ISA when appropriate.
390 2020-08-25 Alan Modra <amodra@gmail.com>
393 * vax-dis.c (parse_disassembler_options): Always add at least one
394 to entry_addr_total_slots.
396 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
398 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
399 in other CPUs to speed up disassembling.
400 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
401 Change plsli.u16 to plsli.16, change sync's operand format.
403 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
405 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
407 2020-08-21 Nick Clifton <nickc@redhat.com>
409 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
412 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
414 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
416 2020-08-19 Alan Modra <amodra@gmail.com>
418 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
421 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
423 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
424 <xvcvbf16spn>: ...to this.
426 2020-08-12 Alex Coplan <alex.coplan@arm.com>
428 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
430 2020-08-12 Nick Clifton <nickc@redhat.com>
432 * po/sr.po: Updated Serbian translation.
434 2020-08-11 Alan Modra <amodra@gmail.com>
436 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
438 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
440 * aarch64-opc.c (aarch64_print_operand):
441 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
442 (aarch64_sys_reg_supported_p): Function removed.
443 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
444 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
447 2020-08-10 Alan Modra <amodra@gmail.com>
449 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
452 2020-08-10 Alan Modra <amodra@gmail.com>
454 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
455 Enable icbt for power5, miso for power8.
457 2020-08-10 Alan Modra <amodra@gmail.com>
459 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
460 mtvsrd, and similarly for mfvsrd.
462 2020-08-04 Christian Groessler <chris@groessler.org>
463 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
465 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
466 opcodes (special "out" to absolute address).
467 * z8k-opc.h: Regenerate.
469 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
472 * i386-opc.h (Prefix_Disp8): New.
473 (Prefix_Disp16): Likewise.
474 (Prefix_Disp32): Likewise.
475 (Prefix_Load): Likewise.
476 (Prefix_Store): Likewise.
477 (Prefix_VEX): Likewise.
478 (Prefix_VEX3): Likewise.
479 (Prefix_EVEX): Likewise.
480 (Prefix_REX): Likewise.
481 (Prefix_NoOptimize): Likewise.
482 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
483 * i386-tbl.h: Regenerated.
485 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
487 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
488 default case with abort() instead of printing an error message and
489 continuing, to avoid a maybe-uninitialized warning.
491 2020-07-24 Nick Clifton <nickc@redhat.com>
493 * po/de.po: Updated German translation.
495 2020-07-21 Jan Beulich <jbeulich@suse.com>
497 * i386-dis.c (OP_E_memory): Revert previous change.
499 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
502 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
503 without base nor index registers.
505 2020-07-15 Jan Beulich <jbeulich@suse.com>
507 * i386-dis.c (putop): Move 'V' and 'W' handling.
509 2020-07-15 Jan Beulich <jbeulich@suse.com>
511 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
512 construct for push/pop of register.
513 (putop): Honor cond when handling 'P'. Drop handling of plain
516 2020-07-15 Jan Beulich <jbeulich@suse.com>
518 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
519 description. Drop '&' description. Use P for push of immediate,
520 pushf/popf, enter, and leave. Use %LP for lret/retf.
521 (dis386_twobyte): Use P for push/pop of fs/gs.
522 (reg_table): Use P for push/pop. Use @ for near call/jmp.
523 (x86_64_table): Use P for far call/jmp.
524 (putop): Drop handling of 'U' and '&'. Move and adjust handling
525 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
527 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
528 and dqw_mode (unconditional).
530 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
533 * i386-dis.c (OP_E_memory): Without base nor index registers,
534 32-bit displacement to 64 bits.
536 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
538 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
539 faulty double register pair is detected.
541 2020-07-14 Jan Beulich <jbeulich@suse.com>
543 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
545 2020-07-14 Jan Beulich <jbeulich@suse.com>
547 * i386-dis.c (OP_R, Rm): Delete.
548 (MOD_0F24, MOD_0F26): Rename to ...
549 (X86_64_0F24, X86_64_0F26): ... respectively.
550 (dis386): Update 'L' and 'Z' comments.
551 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
553 (mod_table): Move opcode 0F24 and 0F26 entries ...
554 (x86_64_table): ... here.
555 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
558 2020-07-14 Jan Beulich <jbeulich@suse.com>
560 * i386-dis.c (Rd, Rdq, MaskR): Delete.
561 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
562 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
563 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
564 MOD_EVEX_0F387C): New enumerators.
565 (reg_table): Use Edq for rdssp.
566 (prefix_table): Use Edq for incssp.
567 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
568 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
569 ktest*, and kshift*. Use Edq / MaskE for kmov*.
570 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
571 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
572 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
573 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
574 0F3828_P_1 and 0F3838_P_1.
575 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
576 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
578 2020-07-14 Jan Beulich <jbeulich@suse.com>
580 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
581 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
582 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
583 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
584 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
585 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
586 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
587 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
588 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
589 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
590 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
591 (reg_table, prefix_table, three_byte_table, vex_table,
592 vex_len_table, mod_table, rm_table): Replace / remove respective
594 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
595 of PREFIX_DATA in used_prefixes.
597 2020-07-14 Jan Beulich <jbeulich@suse.com>
599 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
600 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
601 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
602 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
603 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
604 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
605 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
606 VEX_W_0F3A33_L_0): Delete.
607 (dis386): Adjust "BW" description.
608 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
609 0F3A31, 0F3A32, and 0F3A33.
610 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
612 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
615 2020-07-14 Jan Beulich <jbeulich@suse.com>
617 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
618 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
619 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
620 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
621 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
622 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
623 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
624 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
625 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
626 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
627 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
628 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
629 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
630 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
631 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
632 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
633 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
634 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
635 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
636 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
637 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
638 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
639 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
640 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
641 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
642 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
643 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
644 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
645 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
646 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
647 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
648 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
649 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
650 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
651 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
652 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
653 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
654 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
655 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
656 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
657 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
658 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
659 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
660 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
661 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
662 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
663 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
664 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
665 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
666 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
667 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
668 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
669 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
670 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
671 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
672 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
673 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
674 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
675 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
676 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
677 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
678 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
679 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
680 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
681 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
682 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
683 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
684 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
685 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
686 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
687 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
688 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
689 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
690 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
691 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
692 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
693 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
694 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
695 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
696 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
697 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
698 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
699 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
700 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
701 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
702 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
703 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
704 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
705 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
706 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
707 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
708 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
709 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
710 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
711 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
712 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
713 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
714 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
715 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
716 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
717 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
718 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
719 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
720 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
721 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
722 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
723 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
724 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
725 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
726 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
727 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
728 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
729 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
730 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
731 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
732 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
733 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
734 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
735 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
736 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
737 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
738 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
739 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
740 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
741 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
742 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
743 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
744 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
745 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
746 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
747 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
748 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
749 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
750 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
751 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
752 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
753 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
754 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
755 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
756 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
757 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
758 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
759 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
760 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
761 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
762 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
763 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
764 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
765 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
766 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
767 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
768 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
769 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
770 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
771 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
772 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
773 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
774 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
775 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
776 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
777 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
778 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
779 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
780 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
781 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
782 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
783 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
784 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
785 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
786 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
787 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
788 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
789 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
790 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
791 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
792 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
793 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
794 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
795 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
796 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
797 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
798 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
799 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
800 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
801 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
802 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
803 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
804 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
805 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
806 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
807 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
808 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
809 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
810 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
811 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
812 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
813 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
814 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
815 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
816 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
817 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
818 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
819 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
820 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
821 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
822 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
823 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
824 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
825 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
826 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
827 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
828 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
829 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
830 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
831 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
832 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
833 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
834 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
835 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
836 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
837 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
838 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
839 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
840 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
841 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
842 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
843 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
844 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
845 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
846 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
847 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
848 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
849 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
850 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
851 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
852 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
853 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
854 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
855 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
856 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
857 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
858 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
859 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
860 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
861 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
862 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
863 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
864 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
865 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
866 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
867 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
868 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
869 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
870 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
871 EVEX_W_0F3A72_P_2): Rename to ...
872 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
873 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
874 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
875 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
876 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
877 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
878 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
879 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
880 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
881 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
882 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
883 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
884 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
885 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
886 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
887 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
888 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
889 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
890 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
891 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
892 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
893 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
894 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
895 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
896 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
897 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
898 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
899 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
900 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
901 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
902 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
903 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
904 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
905 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
906 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
907 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
908 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
909 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
910 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
911 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
912 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
913 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
914 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
915 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
916 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
917 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
918 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
919 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
920 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
921 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
922 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
923 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
924 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
925 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
926 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
927 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
928 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
929 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
930 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
931 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
932 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
933 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
934 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
935 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
936 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
937 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
938 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
939 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
940 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
941 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
942 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
943 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
945 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
946 vex_w_table, mod_table): Replace / remove respective entries.
947 (print_insn): Move up dp->prefix_requirement handling. Handle
949 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
950 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
951 Replace / remove respective entries.
953 2020-07-14 Jan Beulich <jbeulich@suse.com>
955 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
956 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
957 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
958 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
959 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
961 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
962 0F2C, 0F2D, 0F2E, and 0F2F.
963 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
966 2020-07-14 Jan Beulich <jbeulich@suse.com>
968 * i386-dis.c (OP_VexR, VexScalarR): New.
969 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
970 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
971 need_vex_reg): Delete.
972 (prefix_table): Replace VexScalar by VexScalarR and
973 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
974 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
975 (vex_len_table): Replace EXqVexScalarS by EXqS.
976 (get_valid_dis386): Don't set need_vex_reg.
977 (print_insn): Don't initialize need_vex_reg.
978 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
979 q_scalar_swap_mode cases.
980 (OP_EX): Don't check for d_scalar_swap_mode and
982 (OP_VEX): Done check need_vex_reg.
983 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
984 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
985 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
987 2020-07-14 Jan Beulich <jbeulich@suse.com>
989 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
990 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
991 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
992 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
993 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
994 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
995 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
996 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
997 (vex_table): Replace Vex128 by Vex.
998 (vex_len_table): Likewise. Adjust referenced enum names.
999 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1000 referenced enum names.
1001 (OP_VEX): Drop vex128_mode and vex256_mode cases.
1002 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1004 2020-07-14 Jan Beulich <jbeulich@suse.com>
1006 * i386-dis.c (dis386): "LW" description now applies to "DQ".
1007 (putop): Handle "DQ". Don't handle "LW" anymore.
1008 (prefix_table, mod_table): Replace %LW by %DQ.
1009 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1011 2020-07-14 Jan Beulich <jbeulich@suse.com>
1013 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1014 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1015 d_scalar_swap_mode case handling. Move shift adjsutment into
1016 the case its applicable to.
1018 2020-07-14 Jan Beulich <jbeulich@suse.com>
1020 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1021 (EXbScalar, EXwScalar): Fold to ...
1022 (EXbwUnit): ... this.
1023 (b_scalar_mode, w_scalar_mode): Fold to ...
1024 (bw_unit_mode): ... this.
1025 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1026 w_scalar_mode handling by bw_unit_mode one.
1027 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1029 * i386-dis-evex-prefix.h: ... here.
1031 2020-07-14 Jan Beulich <jbeulich@suse.com>
1033 * i386-dis.c (PCMPESTR_Fixup): Delete.
1034 (dis386): Adjust "LQ" description.
1035 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1036 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1037 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1038 vpcmpestrm, and vpcmpestri.
1039 (putop): Honor "cond" when handling LQ.
1040 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1041 vcvtsi2ss and vcvtusi2ss.
1042 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1043 vcvtsi2sd and vcvtusi2sd.
1045 2020-07-14 Jan Beulich <jbeulich@suse.com>
1047 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1048 (simd_cmp_op): Add const.
1049 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1050 (CMP_Fixup): Handle VEX case.
1051 (prefix_table): Replace VCMP by CMP.
1052 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1054 2020-07-14 Jan Beulich <jbeulich@suse.com>
1056 * i386-dis.c (MOVBE_Fixup): Delete.
1058 (prefix_table): Use Mv for movbe entries.
1060 2020-07-14 Jan Beulich <jbeulich@suse.com>
1062 * i386-dis.c (CRC32_Fixup): Delete.
1063 (prefix_table): Use Eb/Ev for crc32 entries.
1065 2020-07-14 Jan Beulich <jbeulich@suse.com>
1067 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1068 Conditionalize invocations of "USED_REX (0)".
1070 2020-07-14 Jan Beulich <jbeulich@suse.com>
1072 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1073 CH, DH, BH, AX, DX): Delete.
1074 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1075 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1076 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1078 2020-07-10 Lili Cui <lili.cui@intel.com>
1080 * i386-dis.c (TMM): New.
1083 (MVexSIBMEM): Likewise.
1084 (tmm_mode): Likewise.
1085 (vex_sibmem_mode): Likewise.
1086 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1087 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1088 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1089 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1090 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1091 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1092 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1093 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1094 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1095 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1096 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1097 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1098 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1099 (PREFIX_VEX_0F3849_X86_64): Likewise.
1100 (PREFIX_VEX_0F384B_X86_64): Likewise.
1101 (PREFIX_VEX_0F385C_X86_64): Likewise.
1102 (PREFIX_VEX_0F385E_X86_64): Likewise.
1103 (X86_64_VEX_0F3849): Likewise.
1104 (X86_64_VEX_0F384B): Likewise.
1105 (X86_64_VEX_0F385C): Likewise.
1106 (X86_64_VEX_0F385E): Likewise.
1107 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1108 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1109 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1110 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1111 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1112 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1113 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1114 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1115 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1116 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1117 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1118 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1119 (VEX_W_0F3849_X86_64_P_0): Likewise.
1120 (VEX_W_0F3849_X86_64_P_2): Likewise.
1121 (VEX_W_0F3849_X86_64_P_3): Likewise.
1122 (VEX_W_0F384B_X86_64_P_1): Likewise.
1123 (VEX_W_0F384B_X86_64_P_2): Likewise.
1124 (VEX_W_0F384B_X86_64_P_3): Likewise.
1125 (VEX_W_0F385C_X86_64_P_1): Likewise.
1126 (VEX_W_0F385E_X86_64_P_0): Likewise.
1127 (VEX_W_0F385E_X86_64_P_1): Likewise.
1128 (VEX_W_0F385E_X86_64_P_2): Likewise.
1129 (VEX_W_0F385E_X86_64_P_3): Likewise.
1130 (names_tmm): Likewise.
1131 (att_names_tmm): Likewise.
1132 (intel_operand_size): Handle void_mode.
1133 (OP_XMM): Handle tmm_mode.
1136 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1137 CpuAMX_BF16 and CpuAMX_TILE.
1138 (operand_type_shorthands): Add RegTMM.
1139 (operand_type_init): Likewise.
1140 (operand_types): Add Tmmword.
1141 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1142 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1143 * i386-opc.h (CpuAMX_INT8): New.
1144 (CpuAMX_BF16): Likewise.
1145 (CpuAMX_TILE): Likewise.
1147 (Tmmword): Likewise.
1148 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1149 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1150 (i386_operand_type): Add tmmword.
1151 * i386-opc.tbl: Add AMX instructions.
1152 * i386-reg.tbl: Add AMX registers.
1153 * i386-init.h: Regenerated.
1154 * i386-tbl.h: Likewise.
1156 2020-07-08 Jan Beulich <jbeulich@suse.com>
1158 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1159 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1161 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1162 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1164 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1165 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1166 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1167 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1168 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1169 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1170 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1171 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1172 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1173 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1174 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1175 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1176 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1177 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1178 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1179 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1180 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1181 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1182 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1183 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1184 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1185 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1186 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1187 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1188 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1189 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1190 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1191 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1192 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1193 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1194 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1195 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1196 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1197 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1198 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1199 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1200 (reg_table): Re-order XOP entries. Adjust their operands.
1201 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1202 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1203 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1204 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1205 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1206 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1207 entries by references ...
1208 (vex_len_table): ... to resepctive new entries here. For several
1209 new and existing entries reference ...
1210 (vex_w_table): ... new entries here.
1211 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1213 2020-07-08 Jan Beulich <jbeulich@suse.com>
1215 * i386-dis.c (XMVexScalarI4): Define.
1216 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1217 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1218 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1219 (vex_len_table): Move scalar FMA4 entries ...
1220 (prefix_table): ... here.
1221 (OP_REG_VexI4): Handle scalar_mode.
1222 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1223 * i386-tbl.h: Re-generate.
1225 2020-07-08 Jan Beulich <jbeulich@suse.com>
1227 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1228 Vex_2src_2): Delete.
1229 (OP_VexW, VexW): New.
1230 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1231 for shifts and rotates by register.
1233 2020-07-08 Jan Beulich <jbeulich@suse.com>
1235 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1236 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1237 OP_EX_VexReg): Delete.
1238 (OP_VexI4, VexI4): New.
1239 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1240 (prefix_table): ... here.
1241 (print_insn): Drop setting of vex_w_done.
1243 2020-07-08 Jan Beulich <jbeulich@suse.com>
1245 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1246 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1247 (xop_table): Replace operands of 4-operand insns.
1248 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1250 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1252 * arc-opc.c (insert_rbd): New function.
1255 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1258 2020-07-07 Jan Beulich <jbeulich@suse.com>
1260 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1261 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1262 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1263 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1265 (putop): Handle "BW".
1266 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1267 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1269 * i386-dis-evex-prefix.h: ... here.
1271 2020-07-06 Jan Beulich <jbeulich@suse.com>
1273 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1274 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1275 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1276 VEX_W_0FXOP_09_83): New enumerators.
1277 (xop_table): Reference the above.
1278 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1279 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1280 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1281 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1283 2020-07-06 Jan Beulich <jbeulich@suse.com>
1285 * i386-dis.c (EVEX_W_0F3838_P_1,
1286 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1287 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1288 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1289 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1290 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1291 (putop): Centralize management of last[]. Delete SAVE_LAST.
1292 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1293 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1294 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1295 * i386-dis-evex-prefix.h: here.
1297 2020-07-06 Jan Beulich <jbeulich@suse.com>
1299 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1300 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1301 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1302 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1304 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1305 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1306 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1307 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1308 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1309 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1310 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1311 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1312 these, respectively.
1313 * i386-dis-evex-len.h: Adjust comments.
1314 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1315 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1316 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1317 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1318 MOD_EVEX_0F385B_P_2_W_1 table entries.
1319 * i386-dis-evex-w.h: Reference mod_table[] for
1320 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1323 2020-07-06 Jan Beulich <jbeulich@suse.com>
1325 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1326 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1328 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1329 Likewise. Mark 256-bit entries invalid.
1331 2020-07-06 Jan Beulich <jbeulich@suse.com>
1333 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1334 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1335 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1336 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1337 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1338 PREFIX_EVEX_0F382B): Delete.
1339 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1340 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1341 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1342 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1343 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1345 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1346 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1347 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1348 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1350 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1351 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1352 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1353 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1354 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1355 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1356 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1357 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1358 PREFIX_EVEX_0F382B): Remove table entries.
1359 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1360 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1361 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1363 2020-07-06 Jan Beulich <jbeulich@suse.com>
1365 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1366 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1368 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1369 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1370 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1371 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1374 2020-07-06 Jan Beulich <jbeulich@suse.com>
1376 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1377 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1378 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1379 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1380 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1381 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1382 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1383 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1384 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1387 2020-07-06 Jan Beulich <jbeulich@suse.com>
1389 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1390 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1391 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1393 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1395 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1397 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1399 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1401 2020-07-06 Jan Beulich <jbeulich@suse.com>
1403 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1404 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1405 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1406 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1407 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1408 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1409 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1410 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1411 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1412 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1413 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1414 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1415 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1416 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1417 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1418 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1419 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1420 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1421 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1422 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1423 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1424 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1425 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1426 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1427 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1428 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1429 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1430 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1431 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1432 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1433 (prefix_table): Add EXxEVexR to FMA table entries.
1434 (OP_Rounding): Move abort() invocation.
1435 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1436 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1437 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1438 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1439 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1440 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1441 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1442 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1443 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1444 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1446 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1447 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1448 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1449 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1450 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1451 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1452 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1453 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1454 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1455 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1456 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1457 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1458 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1459 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1460 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1461 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1462 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1463 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1464 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1465 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1466 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1467 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1468 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1469 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1470 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1471 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1472 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1473 Delete table entries.
1474 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1475 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1476 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1479 2020-07-06 Jan Beulich <jbeulich@suse.com>
1481 * i386-dis.c (EXqScalarS): Delete.
1482 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1483 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1485 2020-07-06 Jan Beulich <jbeulich@suse.com>
1487 * i386-dis.c (safe-ctype.h): Include.
1488 (EXdScalar, EXqScalar): Delete.
1489 (d_scalar_mode, q_scalar_mode): Delete.
1490 (prefix_table, vex_len_table): Use EXxmm_md in place of
1491 EXdScalar and EXxmm_mq in place of EXqScalar.
1492 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1493 d_scalar_mode and q_scalar_mode.
1494 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1495 (vmovsd): Use EXxmm_mq.
1497 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1500 * arc-dis.c: Fix spelling mistake.
1501 * po/opcodes.pot: Regenerate.
1503 2020-07-06 Nick Clifton <nickc@redhat.com>
1505 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1506 * po/uk.po: Updated Ukranian translation.
1508 2020-07-04 Nick Clifton <nickc@redhat.com>
1510 * configure: Regenerate.
1511 * po/opcodes.pot: Regenerate.
1513 2020-07-04 Nick Clifton <nickc@redhat.com>
1515 Binutils 2.35 branch created.
1517 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1519 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1520 * i386-opc.h (VexSwapSources): New.
1521 (i386_opcode_modifier): Add vexswapsources.
1522 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1523 with two source operands swapped.
1524 * i386-tbl.h: Regenerated.
1526 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1528 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1529 unprivileged CSR can also be initialized.
1531 2020-06-29 Alan Modra <amodra@gmail.com>
1533 * arm-dis.c: Use C style comments.
1534 * cr16-opc.c: Likewise.
1535 * ft32-dis.c: Likewise.
1536 * moxie-opc.c: Likewise.
1537 * tic54x-dis.c: Likewise.
1538 * s12z-opc.c: Remove useless comment.
1539 * xgate-dis.c: Likewise.
1541 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1543 * i386-opc.tbl: Add a blank line.
1545 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1547 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1548 (VecSIB128): Renamed to ...
1550 (VecSIB256): Renamed to ...
1552 (VecSIB512): Renamed to ...
1554 (VecSIB): Renamed to ...
1556 (i386_opcode_modifier): Replace vecsib with sib.
1557 * i386-opc.tbl (VecSIB128): New.
1558 (VecSIB256): Likewise.
1559 (VecSIB512): Likewise.
1560 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1561 and VecSIB512, respectively.
1563 2020-06-26 Jan Beulich <jbeulich@suse.com>
1565 * i386-dis.c: Adjust description of I macro.
1566 (x86_64_table): Drop use of I.
1567 (float_mem): Replace use of I.
1568 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1570 2020-06-26 Jan Beulich <jbeulich@suse.com>
1572 * i386-dis.c: (print_insn): Avoid straight assignment to
1573 priv.orig_sizeflag when processing -M sub-options.
1575 2020-06-25 Jan Beulich <jbeulich@suse.com>
1577 * i386-dis.c: Adjust description of J macro.
1578 (dis386, x86_64_table, mod_table): Replace J.
1579 (putop): Remove handling of J.
1581 2020-06-25 Jan Beulich <jbeulich@suse.com>
1583 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1585 2020-06-25 Jan Beulich <jbeulich@suse.com>
1587 * i386-dis.c: Adjust description of "LQ" macro.
1588 (dis386_twobyte): Use LQ for sysret.
1589 (putop): Adjust handling of LQ.
1591 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1593 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1594 * riscv-dis.c: Include elfxx-riscv.h.
1596 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1598 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1600 2020-06-17 Lili Cui <lili.cui@intel.com>
1602 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1604 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1607 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1608 * i386-opc.tbl: Likewise.
1609 * i386-tbl.h: Regenerated.
1611 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1613 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1615 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1617 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1618 (SR_CORE): Likewise.
1619 (SR_FEAT): Likewise.
1621 (SR_V8_1): Likewise.
1622 (SR_V8_2): Likewise.
1623 (SR_V8_3): Likewise.
1624 (SR_V8_4): Likewise.
1627 (SR_SSBS): Likewise.
1629 (SR_ID_PFR2): Likewise.
1630 (SR_PROFILE): Likewise.
1631 (SR_MEMTAG): Likewise.
1632 (SR_SCXTNUM): Likewise.
1633 (aarch64_sys_regs): Refactor to store feature information in the table.
1634 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1635 that now describe their own features.
1636 (aarch64_pstatefield_supported_p): Likewise.
1638 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1640 * i386-dis.c (prefix_table): Fix a typo in comments.
1642 2020-06-09 Jan Beulich <jbeulich@suse.com>
1644 * i386-dis.c (rex_ignored): Delete.
1645 (ckprefix): Drop rex_ignored initialization.
1646 (get_valid_dis386): Drop setting of rex_ignored.
1647 (print_insn): Drop checking of rex_ignored. Don't record data
1648 size prefix as used with VEX-and-alike encodings.
1650 2020-06-09 Jan Beulich <jbeulich@suse.com>
1652 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1653 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1654 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1655 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1656 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1657 VEX_0F12, and VEX_0F16.
1658 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1659 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1660 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1661 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1662 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1663 MOD_VEX_0F16_PREFIX_2 entries.
1665 2020-06-09 Jan Beulich <jbeulich@suse.com>
1667 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1668 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1669 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1670 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1671 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1672 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1673 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1674 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1675 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1676 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1677 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1678 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1679 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1680 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1681 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1682 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1683 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1684 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1685 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1686 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1687 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1688 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1689 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1690 EVEX_W_0FC6_P_2): Delete.
1691 (print_insn): Add EVEX.W vs embedded prefix consistency check
1692 to prefix validation.
1693 * i386-dis-evex.h (evex_table): Don't further descend for
1694 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1695 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1697 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1698 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1699 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1700 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1701 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1702 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1703 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1704 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1705 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1706 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1707 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1708 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1709 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1710 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1711 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1712 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1713 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1714 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1715 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1716 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1717 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1718 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1719 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1720 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1721 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1722 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1723 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1725 2020-06-09 Jan Beulich <jbeulich@suse.com>
1727 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1728 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1729 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1731 (print_insn): Drop pointless check against bad_opcode. Split
1732 prefix validation into legacy and VEX-and-alike parts.
1733 (putop): Re-work 'X' macro handling.
1735 2020-06-09 Jan Beulich <jbeulich@suse.com>
1737 * i386-dis.c (MOD_0F51): Rename to ...
1738 (MOD_0F50): ... this.
1740 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1742 * arm-dis.c (arm_opcodes): Add dfb.
1743 (thumb32_opcodes): Add dfb.
1745 2020-06-08 Jan Beulich <jbeulich@suse.com>
1747 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1749 2020-06-06 Alan Modra <amodra@gmail.com>
1751 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1753 2020-06-05 Alan Modra <amodra@gmail.com>
1755 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1756 size is large enough.
1758 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1760 * disassemble.c (disassemble_init_for_target): Set endian_code for
1762 * bpf-desc.c: Regenerate.
1763 * bpf-opc.c: Likewise.
1764 * bpf-dis.c: Likewise.
1766 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1768 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1769 (cgen_put_insn_value): Likewise.
1770 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1771 * cgen-dis.in (print_insn): Likewise.
1772 * cgen-ibld.in (insert_1): Likewise.
1773 (insert_1): Likewise.
1774 (insert_insn_normal): Likewise.
1775 (extract_1): Likewise.
1776 * bpf-dis.c: Regenerate.
1777 * bpf-ibld.c: Likewise.
1778 * bpf-ibld.c: Likewise.
1779 * cgen-dis.in: Likewise.
1780 * cgen-ibld.in: Likewise.
1781 * cgen-opc.c: Likewise.
1782 * epiphany-dis.c: Likewise.
1783 * epiphany-ibld.c: Likewise.
1784 * fr30-dis.c: Likewise.
1785 * fr30-ibld.c: Likewise.
1786 * frv-dis.c: Likewise.
1787 * frv-ibld.c: Likewise.
1788 * ip2k-dis.c: Likewise.
1789 * ip2k-ibld.c: Likewise.
1790 * iq2000-dis.c: Likewise.
1791 * iq2000-ibld.c: Likewise.
1792 * lm32-dis.c: Likewise.
1793 * lm32-ibld.c: Likewise.
1794 * m32c-dis.c: Likewise.
1795 * m32c-ibld.c: Likewise.
1796 * m32r-dis.c: Likewise.
1797 * m32r-ibld.c: Likewise.
1798 * mep-dis.c: Likewise.
1799 * mep-ibld.c: Likewise.
1800 * mt-dis.c: Likewise.
1801 * mt-ibld.c: Likewise.
1802 * or1k-dis.c: Likewise.
1803 * or1k-ibld.c: Likewise.
1804 * xc16x-dis.c: Likewise.
1805 * xc16x-ibld.c: Likewise.
1806 * xstormy16-dis.c: Likewise.
1807 * xstormy16-ibld.c: Likewise.
1809 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1811 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1812 (print_insn_): Handle instruction endian.
1813 * bpf-dis.c: Regenerate.
1814 * bpf-desc.c: Regenerate.
1815 * epiphany-dis.c: Likewise.
1816 * epiphany-desc.c: Likewise.
1817 * fr30-dis.c: Likewise.
1818 * fr30-desc.c: Likewise.
1819 * frv-dis.c: Likewise.
1820 * frv-desc.c: Likewise.
1821 * ip2k-dis.c: Likewise.
1822 * ip2k-desc.c: Likewise.
1823 * iq2000-dis.c: Likewise.
1824 * iq2000-desc.c: Likewise.
1825 * lm32-dis.c: Likewise.
1826 * lm32-desc.c: Likewise.
1827 * m32c-dis.c: Likewise.
1828 * m32c-desc.c: Likewise.
1829 * m32r-dis.c: Likewise.
1830 * m32r-desc.c: Likewise.
1831 * mep-dis.c: Likewise.
1832 * mep-desc.c: Likewise.
1833 * mt-dis.c: Likewise.
1834 * mt-desc.c: Likewise.
1835 * or1k-dis.c: Likewise.
1836 * or1k-desc.c: Likewise.
1837 * xc16x-dis.c: Likewise.
1838 * xc16x-desc.c: Likewise.
1839 * xstormy16-dis.c: Likewise.
1840 * xstormy16-desc.c: Likewise.
1842 2020-06-03 Nick Clifton <nickc@redhat.com>
1844 * po/sr.po: Updated Serbian translation.
1846 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1848 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1849 (riscv_get_priv_spec_class): Likewise.
1851 2020-06-01 Alan Modra <amodra@gmail.com>
1853 * bpf-desc.c: Regenerate.
1855 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1856 David Faust <david.faust@oracle.com>
1858 * bpf-desc.c: Regenerate.
1859 * bpf-opc.h: Likewise.
1860 * bpf-opc.c: Likewise.
1861 * bpf-dis.c: Likewise.
1863 2020-05-28 Alan Modra <amodra@gmail.com>
1865 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1868 2020-05-28 Alan Modra <amodra@gmail.com>
1870 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1872 (print_insn_ns32k): Revert last change.
1874 2020-05-28 Nick Clifton <nickc@redhat.com>
1876 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1879 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1881 Fix extraction of signed constants in nios2 disassembler (again).
1883 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1884 extractions of signed fields.
1886 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1888 * s390-opc.txt: Relocate vector load/store instructions with
1889 additional alignment parameter and change architecture level
1890 constraint from z14 to z13.
1892 2020-05-21 Alan Modra <amodra@gmail.com>
1894 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1895 * sparc-dis.c: Likewise.
1896 * tic4x-dis.c: Likewise.
1897 * xtensa-dis.c: Likewise.
1898 * bpf-desc.c: Regenerate.
1899 * epiphany-desc.c: Regenerate.
1900 * fr30-desc.c: Regenerate.
1901 * frv-desc.c: Regenerate.
1902 * ip2k-desc.c: Regenerate.
1903 * iq2000-desc.c: Regenerate.
1904 * lm32-desc.c: Regenerate.
1905 * m32c-desc.c: Regenerate.
1906 * m32r-desc.c: Regenerate.
1907 * mep-asm.c: Regenerate.
1908 * mep-desc.c: Regenerate.
1909 * mt-desc.c: Regenerate.
1910 * or1k-desc.c: Regenerate.
1911 * xc16x-desc.c: Regenerate.
1912 * xstormy16-desc.c: Regenerate.
1914 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1916 * riscv-opc.c (riscv_ext_version_table): The table used to store
1917 all information about the supported spec and the corresponding ISA
1918 versions. Currently, only Zicsr is supported to verify the
1919 correctness of Z sub extension settings. Others will be supported
1920 in the future patches.
1921 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1922 classes and the corresponding strings.
1923 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1924 spec class by giving a ISA spec string.
1925 * riscv-opc.c (struct priv_spec_t): New structure.
1926 (struct priv_spec_t priv_specs): List for all supported privilege spec
1927 classes and the corresponding strings.
1928 (riscv_get_priv_spec_class): New function. Get the corresponding
1929 privilege spec class by giving a spec string.
1930 (riscv_get_priv_spec_name): New function. Get the corresponding
1931 privilege spec string by giving a CSR version class.
1932 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1933 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1934 according to the chosen version. Build a hash table riscv_csr_hash to
1935 store the valid CSR for the chosen pirv verison. Dump the direct
1936 CSR address rather than it's name if it is invalid.
1937 (parse_riscv_dis_option_without_args): New function. Parse the options
1939 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1940 parse the options without arguments first, and then handle the options
1941 with arguments. Add the new option -Mpriv-spec, which has argument.
1942 * riscv-dis.c (print_riscv_disassembler_options): Add description
1943 about the new OBJDUMP option.
1945 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1947 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1948 WC values on POWER10 sync, dcbf and wait instructions.
1949 (insert_pl, extract_pl): New functions.
1950 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1951 (LS3): New , 3-bit L for sync.
1952 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1953 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1954 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1955 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1956 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1957 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1958 <wait>: Enable PL operand on POWER10.
1959 <dcbf>: Enable L3OPT operand on POWER10.
1960 <sync>: Enable SC2 operand on POWER10.
1962 2020-05-19 Stafford Horne <shorne@gmail.com>
1965 * or1k-asm.c: Regenerate.
1966 * or1k-desc.c: Regenerate.
1967 * or1k-desc.h: Regenerate.
1968 * or1k-dis.c: Regenerate.
1969 * or1k-ibld.c: Regenerate.
1970 * or1k-opc.c: Regenerate.
1971 * or1k-opc.h: Regenerate.
1972 * or1k-opinst.c: Regenerate.
1974 2020-05-11 Alan Modra <amodra@gmail.com>
1976 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1979 2020-05-11 Alan Modra <amodra@gmail.com>
1981 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1982 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1984 2020-05-11 Alan Modra <amodra@gmail.com>
1986 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1988 2020-05-11 Alan Modra <amodra@gmail.com>
1990 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1991 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1993 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1995 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1998 2020-05-11 Alan Modra <amodra@gmail.com>
2000 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2001 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2002 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2003 (prefix_opcodes): Add xxeval.
2005 2020-05-11 Alan Modra <amodra@gmail.com>
2007 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2008 xxgenpcvwm, xxgenpcvdm.
2010 2020-05-11 Alan Modra <amodra@gmail.com>
2012 * ppc-opc.c (MP, VXVAM_MASK): Define.
2013 (VXVAPS_MASK): Use VXVA_MASK.
2014 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2015 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2016 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2017 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2019 2020-05-11 Alan Modra <amodra@gmail.com>
2020 Peter Bergner <bergner@linux.ibm.com>
2022 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2024 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2025 YMSK2, XA6a, XA6ap, XB6a entries.
2026 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2027 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2029 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2030 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2031 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2032 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2033 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2034 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2035 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2036 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2037 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2038 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2039 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2040 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2041 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2042 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2044 2020-05-11 Alan Modra <amodra@gmail.com>
2046 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2047 (insert_xts, extract_xts): New functions.
2048 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2049 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2050 (VXRC_MASK, VXSH_MASK): Define.
2051 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2052 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2053 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2054 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2055 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2056 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2057 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2059 2020-05-11 Alan Modra <amodra@gmail.com>
2061 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2062 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2063 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2064 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2065 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2067 2020-05-11 Alan Modra <amodra@gmail.com>
2069 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2070 (XTP, DQXP, DQXP_MASK): Define.
2071 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2072 (prefix_opcodes): Add plxvp and pstxvp.
2074 2020-05-11 Alan Modra <amodra@gmail.com>
2076 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2077 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2078 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2080 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2082 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2084 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2086 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2088 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2090 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2092 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2094 2020-05-11 Alan Modra <amodra@gmail.com>
2096 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2098 2020-05-11 Alan Modra <amodra@gmail.com>
2100 * ppc-dis.c (ppc_opts): Add "power10" entry.
2101 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2102 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2104 2020-05-11 Nick Clifton <nickc@redhat.com>
2106 * po/fr.po: Updated French translation.
2108 2020-04-30 Alex Coplan <alex.coplan@arm.com>
2110 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2111 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2112 (operand_general_constraint_met_p): validate
2113 AARCH64_OPND_UNDEFINED.
2114 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2116 * aarch64-asm-2.c: Regenerated.
2117 * aarch64-dis-2.c: Regenerated.
2118 * aarch64-opc-2.c: Regenerated.
2120 2020-04-29 Nick Clifton <nickc@redhat.com>
2123 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2126 2020-04-29 Nick Clifton <nickc@redhat.com>
2128 * po/sv.po: Updated Swedish translation.
2130 2020-04-29 Nick Clifton <nickc@redhat.com>
2133 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2134 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2135 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2138 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2141 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2142 cmpi only on m68020up and cpu32.
2144 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2146 * aarch64-asm.c (aarch64_ins_none): New.
2147 * aarch64-asm.h (ins_none): New declaration.
2148 * aarch64-dis.c (aarch64_ext_none): New.
2149 * aarch64-dis.h (ext_none): New declaration.
2150 * aarch64-opc.c (aarch64_print_operand): Update case for
2151 AARCH64_OPND_BARRIER_PSB.
2152 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2153 (AARCH64_OPERANDS): Update inserter/extracter for
2154 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2155 * aarch64-asm-2.c: Regenerated.
2156 * aarch64-dis-2.c: Regenerated.
2157 * aarch64-opc-2.c: Regenerated.
2159 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2161 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2162 (aarch64_feature_ras, RAS): Likewise.
2163 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2164 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2165 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2166 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2167 * aarch64-asm-2.c: Regenerated.
2168 * aarch64-dis-2.c: Regenerated.
2169 * aarch64-opc-2.c: Regenerated.
2171 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2173 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2174 (print_insn_neon): Support disassembly of conditional
2177 2020-02-16 David Faust <david.faust@oracle.com>
2179 * bpf-desc.c: Regenerate.
2180 * bpf-desc.h: Likewise.
2181 * bpf-opc.c: Regenerate.
2182 * bpf-opc.h: Likewise.
2184 2020-04-07 Lili Cui <lili.cui@intel.com>
2186 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2187 (prefix_table): New instructions (see prefixes above).
2188 (rm_table): Likewise
2189 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2190 CPU_ANY_TSXLDTRK_FLAGS.
2191 (cpu_flags): Add CpuTSXLDTRK.
2192 * i386-opc.h (enum): Add CpuTSXLDTRK.
2193 (i386_cpu_flags): Add cputsxldtrk.
2194 * i386-opc.tbl: Add XSUSPLDTRK insns.
2195 * i386-init.h: Regenerate.
2196 * i386-tbl.h: Likewise.
2198 2020-04-02 Lili Cui <lili.cui@intel.com>
2200 * i386-dis.c (prefix_table): New instructions serialize.
2201 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2202 CPU_ANY_SERIALIZE_FLAGS.
2203 (cpu_flags): Add CpuSERIALIZE.
2204 * i386-opc.h (enum): Add CpuSERIALIZE.
2205 (i386_cpu_flags): Add cpuserialize.
2206 * i386-opc.tbl: Add SERIALIZE insns.
2207 * i386-init.h: Regenerate.
2208 * i386-tbl.h: Likewise.
2210 2020-03-26 Alan Modra <amodra@gmail.com>
2212 * disassemble.h (opcodes_assert): Declare.
2213 (OPCODES_ASSERT): Define.
2214 * disassemble.c: Don't include assert.h. Include opintl.h.
2215 (opcodes_assert): New function.
2216 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2217 (bfd_h8_disassemble): Reduce size of data array. Correctly
2218 calculate maxlen. Omit insn decoding when insn length exceeds
2219 maxlen. Exit from nibble loop when looking for E, before
2220 accessing next data byte. Move processing of E outside loop.
2221 Replace tests of maxlen in loop with assertions.
2223 2020-03-26 Alan Modra <amodra@gmail.com>
2225 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2227 2020-03-25 Alan Modra <amodra@gmail.com>
2229 * z80-dis.c (suffix): Init mybuf.
2231 2020-03-22 Alan Modra <amodra@gmail.com>
2233 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2234 successflly read from section.
2236 2020-03-22 Alan Modra <amodra@gmail.com>
2238 * arc-dis.c (find_format): Use ISO C string concatenation rather
2239 than line continuation within a string. Don't access needs_limm
2240 before testing opcode != NULL.
2242 2020-03-22 Alan Modra <amodra@gmail.com>
2244 * ns32k-dis.c (print_insn_arg): Update comment.
2245 (print_insn_ns32k): Reduce size of index_offset array, and
2246 initialize, passing -1 to print_insn_arg for args that are not
2247 an index. Don't exit arg loop early. Abort on bad arg number.
2249 2020-03-22 Alan Modra <amodra@gmail.com>
2251 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2252 * s12z-opc.c: Formatting.
2253 (operands_f): Return an int.
2254 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2255 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2256 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2257 (exg_sex_discrim): Likewise.
2258 (create_immediate_operand, create_bitfield_operand),
2259 (create_register_operand_with_size, create_register_all_operand),
2260 (create_register_all16_operand, create_simple_memory_operand),
2261 (create_memory_operand, create_memory_auto_operand): Don't
2262 segfault on malloc failure.
2263 (z_ext24_decode): Return an int status, negative on fail, zero
2265 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2266 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2267 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2268 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2269 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2270 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2271 (loop_primitive_decode, shift_decode, psh_pul_decode),
2272 (bit_field_decode): Similarly.
2273 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2274 to return value, update callers.
2275 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2276 Don't segfault on NULL operand.
2277 (decode_operation): Return OP_INVALID on first fail.
2278 (decode_s12z): Check all reads, returning -1 on fail.
2280 2020-03-20 Alan Modra <amodra@gmail.com>
2282 * metag-dis.c (print_insn_metag): Don't ignore status from
2285 2020-03-20 Alan Modra <amodra@gmail.com>
2287 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2288 Initialize parts of buffer not written when handling a possible
2289 2-byte insn at end of section. Don't attempt decoding of such
2290 an insn by the 4-byte machinery.
2292 2020-03-20 Alan Modra <amodra@gmail.com>
2294 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2295 partially filled buffer. Prevent lookup of 4-byte insns when
2296 only VLE 2-byte insns are possible due to section size. Print
2297 ".word" rather than ".long" for 2-byte leftovers.
2299 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2302 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2304 2020-03-13 Jan Beulich <jbeulich@suse.com>
2306 * i386-dis.c (X86_64_0D): Rename to ...
2307 (X86_64_0E): ... this.
2309 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2311 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2312 * Makefile.in: Regenerated.
2314 2020-03-09 Jan Beulich <jbeulich@suse.com>
2316 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2318 * i386-tbl.h: Re-generate.
2320 2020-03-09 Jan Beulich <jbeulich@suse.com>
2322 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2323 vprot*, vpsha*, and vpshl*.
2324 * i386-tbl.h: Re-generate.
2326 2020-03-09 Jan Beulich <jbeulich@suse.com>
2328 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2329 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2330 * i386-tbl.h: Re-generate.
2332 2020-03-09 Jan Beulich <jbeulich@suse.com>
2334 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2335 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2336 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2337 * i386-tbl.h: Re-generate.
2339 2020-03-09 Jan Beulich <jbeulich@suse.com>
2341 * i386-gen.c (struct template_arg, struct template_instance,
2342 struct template_param, struct template, templates,
2343 parse_template, expand_templates): New.
2344 (process_i386_opcodes): Various local variables moved to
2345 expand_templates. Call parse_template and expand_templates.
2346 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2347 * i386-tbl.h: Re-generate.
2349 2020-03-06 Jan Beulich <jbeulich@suse.com>
2351 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2352 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2353 register and memory source templates. Replace VexW= by VexW*
2355 * i386-tbl.h: Re-generate.
2357 2020-03-06 Jan Beulich <jbeulich@suse.com>
2359 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2360 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2361 * i386-tbl.h: Re-generate.
2363 2020-03-06 Jan Beulich <jbeulich@suse.com>
2365 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2366 * i386-tbl.h: Re-generate.
2368 2020-03-06 Jan Beulich <jbeulich@suse.com>
2370 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2371 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2372 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2373 VexW0 on SSE2AVX variants.
2374 (vmovq): Drop NoRex64 from XMM/XMM variants.
2375 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2376 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2377 applicable use VexW0.
2378 * i386-tbl.h: Re-generate.
2380 2020-03-06 Jan Beulich <jbeulich@suse.com>
2382 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2383 * i386-opc.h (Rex64): Delete.
2384 (struct i386_opcode_modifier): Remove rex64 field.
2385 * i386-opc.tbl (crc32): Drop Rex64.
2386 Replace Rex64 with Size64 everywhere else.
2387 * i386-tbl.h: Re-generate.
2389 2020-03-06 Jan Beulich <jbeulich@suse.com>
2391 * i386-dis.c (OP_E_memory): Exclude recording of used address
2392 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2393 addressed memory operands for MPX insns.
2395 2020-03-06 Jan Beulich <jbeulich@suse.com>
2397 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2398 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2399 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2400 (ptwrite): Split into non-64-bit and 64-bit forms.
2401 * i386-tbl.h: Re-generate.
2403 2020-03-06 Jan Beulich <jbeulich@suse.com>
2405 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2407 * i386-tbl.h: Re-generate.
2409 2020-03-04 Jan Beulich <jbeulich@suse.com>
2411 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2412 (prefix_table): Move vmmcall here. Add vmgexit.
2413 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2414 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2415 (cpu_flags): Add CpuSEV_ES entry.
2416 * i386-opc.h (CpuSEV_ES): New.
2417 (union i386_cpu_flags): Add cpusev_es field.
2418 * i386-opc.tbl (vmgexit): New.
2419 * i386-init.h, i386-tbl.h: Re-generate.
2421 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2423 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2425 * i386-opc.h (IGNORESIZE): New.
2426 (DEFAULTSIZE): Likewise.
2427 (IgnoreSize): Removed.
2428 (DefaultSize): Likewise.
2429 (MnemonicSize): New.
2430 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2432 * i386-opc.tbl (IgnoreSize): New.
2433 (DefaultSize): Likewise.
2434 * i386-tbl.h: Regenerated.
2436 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2439 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2442 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2445 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2446 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2447 * i386-tbl.h: Regenerated.
2449 2020-02-26 Alan Modra <amodra@gmail.com>
2451 * aarch64-asm.c: Indent labels correctly.
2452 * aarch64-dis.c: Likewise.
2453 * aarch64-gen.c: Likewise.
2454 * aarch64-opc.c: Likewise.
2455 * alpha-dis.c: Likewise.
2456 * i386-dis.c: Likewise.
2457 * nds32-asm.c: Likewise.
2458 * nfp-dis.c: Likewise.
2459 * visium-dis.c: Likewise.
2461 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2463 * arc-regs.h (int_vector_base): Make it available for all ARC
2466 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2468 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2471 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2473 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2474 c.mv/c.li if rs1 is zero.
2476 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2478 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2479 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2481 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2482 * i386-opc.h (CpuABM): Removed.
2484 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2485 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2486 popcnt. Remove CpuABM from lzcnt.
2487 * i386-init.h: Regenerated.
2488 * i386-tbl.h: Likewise.
2490 2020-02-17 Jan Beulich <jbeulich@suse.com>
2492 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2493 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2494 VexW1 instead of open-coding them.
2495 * i386-tbl.h: Re-generate.
2497 2020-02-17 Jan Beulich <jbeulich@suse.com>
2499 * i386-opc.tbl (AddrPrefixOpReg): Define.
2500 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2501 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2502 templates. Drop NoRex64.
2503 * i386-tbl.h: Re-generate.
2505 2020-02-17 Jan Beulich <jbeulich@suse.com>
2508 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2509 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2510 into Intel syntax instance (with Unpsecified) and AT&T one
2512 (vcvtneps2bf16): Likewise, along with folding the two so far
2514 * i386-tbl.h: Re-generate.
2516 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2518 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2519 CPU_ANY_SSE4A_FLAGS.
2521 2020-02-17 Alan Modra <amodra@gmail.com>
2523 * i386-gen.c (cpu_flag_init): Correct last change.
2525 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2527 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2530 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2532 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2535 2020-02-14 Jan Beulich <jbeulich@suse.com>
2538 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2539 destination for Cpu64-only variant.
2540 (movzx): Fold patterns.
2541 * i386-tbl.h: Re-generate.
2543 2020-02-13 Jan Beulich <jbeulich@suse.com>
2545 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2546 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2547 CPU_ANY_SSE4_FLAGS entry.
2548 * i386-init.h: Re-generate.
2550 2020-02-12 Jan Beulich <jbeulich@suse.com>
2552 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2553 with Unspecified, making the present one AT&T syntax only.
2554 * i386-tbl.h: Re-generate.
2556 2020-02-12 Jan Beulich <jbeulich@suse.com>
2558 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2559 * i386-tbl.h: Re-generate.
2561 2020-02-12 Jan Beulich <jbeulich@suse.com>
2564 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2565 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2566 Amd64 and Intel64 templates.
2567 (call, jmp): Likewise for far indirect variants. Dro
2569 * i386-tbl.h: Re-generate.
2571 2020-02-11 Jan Beulich <jbeulich@suse.com>
2573 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2574 * i386-opc.h (ShortForm): Delete.
2575 (struct i386_opcode_modifier): Remove shortform field.
2576 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2577 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2578 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2579 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2581 * i386-tbl.h: Re-generate.
2583 2020-02-11 Jan Beulich <jbeulich@suse.com>
2585 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2586 fucompi): Drop ShortForm from operand-less templates.
2587 * i386-tbl.h: Re-generate.
2589 2020-02-11 Alan Modra <amodra@gmail.com>
2591 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2592 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2593 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2594 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2595 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2597 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2599 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2600 (cde_opcodes): Add VCX* instructions.
2602 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2603 Matthew Malcomson <matthew.malcomson@arm.com>
2605 * arm-dis.c (struct cdeopcode32): New.
2606 (CDE_OPCODE): New macro.
2607 (cde_opcodes): New disassembly table.
2608 (regnames): New option to table.
2609 (cde_coprocs): New global variable.
2610 (print_insn_cde): New
2611 (print_insn_thumb32): Use print_insn_cde.
2612 (parse_arm_disassembler_options): Parse coprocN args.
2614 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2617 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2619 * i386-opc.h (AMD64): Removed.
2620 (Intel64): Likewose.
2622 (INTEL64): Likewise.
2623 (INTEL64ONLY): Likewise.
2624 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2625 * i386-opc.tbl (Amd64): New.
2626 (Intel64): Likewise.
2627 (Intel64Only): Likewise.
2628 Replace AMD64 with Amd64. Update sysenter/sysenter with
2629 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2630 * i386-tbl.h: Regenerated.
2632 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2635 * z80-dis.c: Add support for GBZ80 opcodes.
2637 2020-02-04 Alan Modra <amodra@gmail.com>
2639 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2641 2020-02-03 Alan Modra <amodra@gmail.com>
2643 * m32c-ibld.c: Regenerate.
2645 2020-02-01 Alan Modra <amodra@gmail.com>
2647 * frv-ibld.c: Regenerate.
2649 2020-01-31 Jan Beulich <jbeulich@suse.com>
2651 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2652 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2653 (OP_E_memory): Replace xmm_mdq_mode case label by
2654 vex_scalar_w_dq_mode one.
2655 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2657 2020-01-31 Jan Beulich <jbeulich@suse.com>
2659 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2660 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2661 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2662 (intel_operand_size): Drop vex_w_dq_mode case label.
2664 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2666 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2667 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2669 2020-01-30 Alan Modra <amodra@gmail.com>
2671 * m32c-ibld.c: Regenerate.
2673 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2675 * bpf-opc.c: Regenerate.
2677 2020-01-30 Jan Beulich <jbeulich@suse.com>
2679 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2680 (dis386): Use them to replace C2/C3 table entries.
2681 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2682 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2683 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2684 * i386-tbl.h: Re-generate.
2686 2020-01-30 Jan Beulich <jbeulich@suse.com>
2688 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2690 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2692 * i386-tbl.h: Re-generate.
2694 2020-01-30 Alan Modra <amodra@gmail.com>
2696 * tic4x-dis.c (tic4x_dp): Make unsigned.
2698 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2699 Jan Beulich <jbeulich@suse.com>
2702 * i386-dis.c (MOVSXD_Fixup): New function.
2703 (movsxd_mode): New enum.
2704 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2705 (intel_operand_size): Handle movsxd_mode.
2706 (OP_E_register): Likewise.
2708 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2709 register on movsxd. Add movsxd with 16-bit destination register
2710 for AMD64 and Intel64 ISAs.
2711 * i386-tbl.h: Regenerated.
2713 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2716 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2717 * aarch64-asm-2.c: Regenerate
2718 * aarch64-dis-2.c: Likewise.
2719 * aarch64-opc-2.c: Likewise.
2721 2020-01-21 Jan Beulich <jbeulich@suse.com>
2723 * i386-opc.tbl (sysret): Drop DefaultSize.
2724 * i386-tbl.h: Re-generate.
2726 2020-01-21 Jan Beulich <jbeulich@suse.com>
2728 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2730 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2731 * i386-tbl.h: Re-generate.
2733 2020-01-20 Nick Clifton <nickc@redhat.com>
2735 * po/de.po: Updated German translation.
2736 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2737 * po/uk.po: Updated Ukranian translation.
2739 2020-01-20 Alan Modra <amodra@gmail.com>
2741 * hppa-dis.c (fput_const): Remove useless cast.
2743 2020-01-20 Alan Modra <amodra@gmail.com>
2745 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2747 2020-01-18 Nick Clifton <nickc@redhat.com>
2749 * configure: Regenerate.
2750 * po/opcodes.pot: Regenerate.
2752 2020-01-18 Nick Clifton <nickc@redhat.com>
2754 Binutils 2.34 branch created.
2756 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2758 * opintl.h: Fix spelling error (seperate).
2760 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2762 * i386-opc.tbl: Add {vex} pseudo prefix.
2763 * i386-tbl.h: Regenerated.
2765 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2768 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2769 (neon_opcodes): Likewise.
2770 (select_arm_features): Make sure we enable MVE bits when selecting
2771 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2774 2020-01-16 Jan Beulich <jbeulich@suse.com>
2776 * i386-opc.tbl: Drop stale comment from XOP section.
2778 2020-01-16 Jan Beulich <jbeulich@suse.com>
2780 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2781 (extractps): Add VexWIG to SSE2AVX forms.
2782 * i386-tbl.h: Re-generate.
2784 2020-01-16 Jan Beulich <jbeulich@suse.com>
2786 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2787 Size64 from and use VexW1 on SSE2AVX forms.
2788 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2789 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2790 * i386-tbl.h: Re-generate.
2792 2020-01-15 Alan Modra <amodra@gmail.com>
2794 * tic4x-dis.c (tic4x_version): Make unsigned long.
2795 (optab, optab_special, registernames): New file scope vars.
2796 (tic4x_print_register): Set up registernames rather than
2797 malloc'd registertable.
2798 (tic4x_disassemble): Delete optable and optable_special. Use
2799 optab and optab_special instead. Throw away old optab,
2800 optab_special and registernames when info->mach changes.
2802 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2805 * z80-dis.c (suffix): Use .db instruction to generate double
2808 2020-01-14 Alan Modra <amodra@gmail.com>
2810 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2811 values to unsigned before shifting.
2813 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2815 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2817 (print_insn_thumb16, print_insn_thumb32): Likewise.
2818 (print_insn): Initialize the insn info.
2819 * i386-dis.c (print_insn): Initialize the insn info fields, and
2822 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2824 * arc-opc.c (C_NE): Make it required.
2826 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2828 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2829 reserved register name.
2831 2020-01-13 Alan Modra <amodra@gmail.com>
2833 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2834 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2836 2020-01-13 Alan Modra <amodra@gmail.com>
2838 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2839 result of wasm_read_leb128 in a uint64_t and check that bits
2840 are not lost when copying to other locals. Use uint32_t for
2841 most locals. Use PRId64 when printing int64_t.
2843 2020-01-13 Alan Modra <amodra@gmail.com>
2845 * score-dis.c: Formatting.
2846 * score7-dis.c: Formatting.
2848 2020-01-13 Alan Modra <amodra@gmail.com>
2850 * score-dis.c (print_insn_score48): Use unsigned variables for
2851 unsigned values. Don't left shift negative values.
2852 (print_insn_score32): Likewise.
2853 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2855 2020-01-13 Alan Modra <amodra@gmail.com>
2857 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2859 2020-01-13 Alan Modra <amodra@gmail.com>
2861 * fr30-ibld.c: Regenerate.
2863 2020-01-13 Alan Modra <amodra@gmail.com>
2865 * xgate-dis.c (print_insn): Don't left shift signed value.
2866 (ripBits): Formatting, use 1u.
2868 2020-01-10 Alan Modra <amodra@gmail.com>
2870 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2871 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2873 2020-01-10 Alan Modra <amodra@gmail.com>
2875 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2876 and XRREG value earlier to avoid a shift with negative exponent.
2877 * m10200-dis.c (disassemble): Similarly.
2879 2020-01-09 Nick Clifton <nickc@redhat.com>
2882 * z80-dis.c (ld_ii_ii): Use correct cast.
2884 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2887 * z80-dis.c (ld_ii_ii): Use character constant when checking
2890 2020-01-09 Jan Beulich <jbeulich@suse.com>
2892 * i386-dis.c (SEP_Fixup): New.
2894 (dis386_twobyte): Use it for sysenter/sysexit.
2895 (enum x86_64_isa): Change amd64 enumerator to value 1.
2896 (OP_J): Compare isa64 against intel64 instead of amd64.
2897 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2899 * i386-tbl.h: Re-generate.
2901 2020-01-08 Alan Modra <amodra@gmail.com>
2903 * z8k-dis.c: Include libiberty.h
2904 (instr_data_s): Make max_fetched unsigned.
2905 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2906 Don't exceed byte_info bounds.
2907 (output_instr): Make num_bytes unsigned.
2908 (unpack_instr): Likewise for nibl_count and loop.
2909 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2911 * z8k-opc.h: Regenerate.
2913 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2915 * arc-tbl.h (llock): Use 'LLOCK' as class.
2917 (scond): Use 'SCOND' as class.
2919 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2922 2020-01-06 Alan Modra <amodra@gmail.com>
2924 * m32c-ibld.c: Regenerate.
2926 2020-01-06 Alan Modra <amodra@gmail.com>
2929 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2930 Peek at next byte to prevent recursion on repeated prefix bytes.
2931 Ensure uninitialised "mybuf" is not accessed.
2932 (print_insn_z80): Don't zero n_fetch and n_used here,..
2933 (print_insn_z80_buf): ..do it here instead.
2935 2020-01-04 Alan Modra <amodra@gmail.com>
2937 * m32r-ibld.c: Regenerate.
2939 2020-01-04 Alan Modra <amodra@gmail.com>
2941 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2943 2020-01-04 Alan Modra <amodra@gmail.com>
2945 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2947 2020-01-04 Alan Modra <amodra@gmail.com>
2949 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2951 2020-01-03 Jan Beulich <jbeulich@suse.com>
2953 * aarch64-tbl.h (aarch64_opcode_table): Use
2954 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2956 2020-01-03 Jan Beulich <jbeulich@suse.com>
2958 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2959 forms of SUDOT and USDOT.
2961 2020-01-03 Jan Beulich <jbeulich@suse.com>
2963 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2965 * aarch64-dis-2.c: Re-generate.
2967 2020-01-03 Jan Beulich <jbeulich@suse.com>
2969 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2971 * aarch64-dis-2.c: Re-generate.
2973 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2975 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2977 2020-01-01 Alan Modra <amodra@gmail.com>
2979 Update year range in copyright notice of all files.
2981 For older changes see ChangeLog-2019
2983 Copyright (C) 2020 Free Software Foundation, Inc.
2985 Copying and distribution of this file, with or without modification,
2986 are permitted in any medium without royalty provided the copyright
2987 notice and this notice are preserved.
2993 version-control: never
projects / deliverable / binutils-gdb.git / blob