opcodes/ChangeLog

   1 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
   2
   3         * xtensa-dis.c: Use ISO C90 formatting.
   4
   5 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
   6
   7         * ppc-opc.c: Revert 2004-09-09 change.
   8
   9 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
  10
  11         * xtensa-dis.c (state_names): Delete.
  12         (fetch_data): Use xtensa_isa_maxlength.
  13         (print_xtensa_operand): Replace operand parameter with opcode/operand
  14         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
  15         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
  16         instruction bundles.  Use xmalloc instead of malloc.
  17
  18 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
  19
  20         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
  21         initializers.
  22
  23 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
  24
  25         * crx-opc.c (crx_instruction): Support Co-processor insns.
  26         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
  27         (getregliststring): Change function to use the above enum.
  28         (print_arg): Handle CO-Processor insns.
  29         (crx_cinvs): Add 'b' option to invalidate the branch-target
  30         cache.
  31
  32 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
  33
  34         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
  35         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
  36         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
  37         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
  38         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
  39
  40 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
  41
  42         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
  43         rather than add it.
  44
  45 2004-09-30  Paul Brook  <paul@codesourcery.com>
  46
  47         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
  48         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
  49
  50 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
  51
  52         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
  53         (CONFIG_STATUS_DEPENDENCIES): New.
  54         (Makefile): Removed.
  55         (config.status): Likewise.
  56         * Makefile.in: Regenerated.
  57
  58 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
  59
  60         * Makefile.am: Run "make dep-am".
  61         * Makefile.in: Regenerate.
  62         * aclocal.m4: Regenerate.
  63         * configure: Regenerate.
  64         * po/POTFILES.in: Regenerate.
  65         * po/opcodes.pot: Regenerate.
  66
  67 2004-09-11  Andreas Schwab  <schwab@suse.de>
  68
  69         * configure: Rebuild.
  70
  71 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
  72
  73         * ppc-opc.c (L): Make this field not optional.
  74
  75 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
  76
  77         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
  78         Fix parameter to 'm[t|f]csr' insns.
  79
  80 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
  81
  82         * configure.in: Autoupdate to autoconf 2.59.
  83         * aclocal.m4: Rebuild with aclocal 1.4p6.
  84         * configure: Rebuild with autoconf 2.59.
  85         * Makefile.in: Rebuild with automake 1.4p6 (picking up
  86         bfd changes for autoconf 2.59 on the way).
  87         * config.in: Rebuild with autoheader 2.59.
  88
  89 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
  90
  91         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
  92
  93 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
  94
  95         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
  96         (GRPPADLCK2): New define.
  97         (twobyte_has_modrm): True for 0xA6.
  98         (grps): GRPPADLCK2 for opcode 0xA6.
  99
 100 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 101
 102         Introduce SH2a support.
 103         * sh-opc.h (arch_sh2a_base): Renumber.
 104         (arch_sh2a_nofpu_base): Remove.
 105         (arch_sh_base_mask): Adjust.
 106         (arch_opann_mask): New.
 107         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 108         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 109         (sh_table): Adjust whitespace.
 110         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 111         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 112         instruction list throughout.
 113         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 114         of arch_sh2a in instruction list throughout.
 115         (arch_sh2e_up): Accomodate above changes.
 116         (arch_sh2_up): Ditto.
 117         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 118         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 119         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 120         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 121         * sh-opc.h (arch_sh2a_nofpu): New.
 122         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 123         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 124         instruction.
 125         2004-01-20  DJ Delorie  <dj@redhat.com>
 126         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 127         2003-12-29  DJ Delorie  <dj@redhat.com>
 128         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 129         sh_opcode_info, sh_table): Add sh2a support.
 130         (arch_op32): New, to tag 32-bit opcodes.
 131         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 132         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 133         * sh-opc.h (arch_sh2a): Add.
 134         * sh-dis.c (arch_sh2a): Handle.
 135         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 136
 137 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 138
 139         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 140
 141 2004-07-22  Nick Clifton  <nickc@redhat.com>
 142
 143         PR/280
 144         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 145         insns - this is done by objdump itself.
 146         * h8500-dis.c (print_insn_h8500): Likewise.
 147
 148 2004-07-21  Jan Beulich <jbeulich@novell.com>
 149
 150         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 151         regardless of address size prefix in effect.
 152         (ptr_reg): Size or address registers does not depend on rex64, but
 153         on the presence of an address size override.
 154         (OP_MMX): Use rex.x only for xmm registers.
 155         (OP_EM): Use rex.z only for xmm registers.
 156
 157 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 158
 159         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 160         move/branch operations to the bottom so that VR5400 multimedia
 161         instructions take precedence in disassembly.
 162
 163 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 164
 165         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 166         ISA-specific "break" encoding.
 167
 168 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 169
 170         * arm-opc.h: Fix typo in comment.
 171
 172 2004-07-11  Andreas Schwab  <schwab@suse.de>
 173
 174         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 175
 176 2004-07-09  Andreas Schwab  <schwab@suse.de>
 177
 178         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 179
 180 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 181
 182         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 183         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 184         (crx-dis.lo): New target.
 185         (crx-opc.lo): Likewise.
 186         * Makefile.in: Regenerate.
 187         * configure.in: Handle bfd_crx_arch.
 188         * configure: Regenerate.
 189         * crx-dis.c: New file.
 190         * crx-opc.c: New file.
 191         * disassemble.c (ARCH_crx): Define.
 192         (disassembler): Handle ARCH_crx.
 193
 194 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 195
 196         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 197         * ia64-asmtab.c: Regnerate.
 198
 199 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 200
 201         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 202         (extract_fxm): Don't test dialect.
 203         (XFXFXM_MASK): Include the power4 bit.
 204         (XFXM): Add p4 param.
 205         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 206
 207 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 208
 209         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 210         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 211
 212 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 213
 214         * ppc-opc.c (BH, XLBH_MASK): Define.
 215         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 216
 217 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 218
 219         * i386-dis.c (x_mode): Comment.
 220         (two_source_ops): File scope.
 221         (float_mem): Correct fisttpll and fistpll.
 222         (float_mem_mode): New table.
 223         (dofloat): Use it.
 224         (OP_E): Correct intel mode PTR output.
 225         (ptr_reg): Use open_char and close_char.
 226         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 227         operands.  Set two_source_ops.
 228
 229 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 230
 231         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 232         instead of _raw_size.
 233
 234 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 235
 236         * ia64-gen.c (in_iclass): Handle more postinc st
 237         and ld variants.
 238         * ia64-asmtab.c: Rebuilt.
 239
 240 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 241
 242         * s390-opc.txt: Correct architecture mask for some opcodes.
 243         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 244         in the esa mode as well.
 245
 246 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 247
 248         * sh-dis.c (target_arch): Make unsigned.
 249         (print_insn_sh): Replace (most of) switch with a call to
 250         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 251         * sh-opc.h: Redefine architecture flags values.
 252         Add sh3-nommu architecture.
 253         Reorganise <arch>_up macros so they make more visual sense.
 254         (SH_MERGE_ARCH_SET): Define new macro.
 255         (SH_VALID_BASE_ARCH_SET): Likewise.
 256         (SH_VALID_MMU_ARCH_SET): Likewise.
 257         (SH_VALID_CO_ARCH_SET): Likewise.
 258         (SH_VALID_ARCH_SET): Likewise.
 259         (SH_MERGE_ARCH_SET_VALID): Likewise.
 260         (SH_ARCH_SET_HAS_FPU): Likewise.
 261         (SH_ARCH_SET_HAS_DSP): Likewise.
 262         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 263         (sh_get_arch_from_bfd_mach): Add prototype.
 264         (sh_get_arch_up_from_bfd_mach): Likewise.
 265         (sh_get_bfd_mach_from_arch_set): Likewise.
 266         (sh_merge_bfd_arc): Likewise.
 267
 268 2004-05-24  Peter Barada  <peter@the-baradas.com>
 269
 270         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 271         into new match_insn_m68k function.  Loop over canidate
 272         matches and select first that completely matches.
 273         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 274         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 275         to verify addressing for MAC/EMAC.
 276         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 277         reigster halves since 'fpu' and 'spl' look misleading.
 278         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 279         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 280         first, tighten up match masks.
 281         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 282         'size' from special case code in print_insn_m68k to
 283         determine decode size of insns.
 284
 285 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 286
 287         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 288         well as when -mpower4.
 289
 290 2004-05-13  Nick Clifton  <nickc@redhat.com>
 291
 292         * po/fr.po: Updated French translation.
 293
 294 2004-05-05  Peter Barada  <peter@the-baradas.com>
 295
 296         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 297         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 298         * m68k-op.c: Switch from ColdFire chips to core variants.
 299
 300 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 301
 302         PR 147.
 303         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 304
 305 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 306
 307         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 308         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 309
 310 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 311
 312         * sh-dis.c (print_insn_sh): Print the value in constant pool
 313         as a symbol if it looks like a symbol.
 314
 315 2004-04-22  Peter Barada <peter@the-baradas.com>
 316
 317         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 318         appropriate ColdFire architectures.
 319         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 320         mask addressing.
 321         Add EMAC instructions, fix MAC instructions. Remove
 322         macmw/macml/msacmw/msacml instructions since mask addressing now
 323         supported.
 324
 325 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 326
 327         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 328         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 329         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 330         macro.  Adjust all users.
 331
 332 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 333
 334         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 335         separately.
 336
 337 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 338
 339         * m32r-asm.c: Regenerate.
 340
 341 2004-03-29  Stan Shebs  <shebs@apple.com>
 342
 343         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 344         used.
 345
 346 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 347
 348         * aclocal.m4: Regenerate.
 349         * config.in: Regenerate.
 350         * configure: Regenerate.
 351         * po/POTFILES.in: Regenerate.
 352         * po/opcodes.pot: Regenerate.
 353
 354 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 355
 356         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 357         PPC_OPERANDS_GPR_0.
 358         * ppc-opc.c (RA0): Define.
 359         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 360         (RAOPT): Rename from RAO.  Update all uses.
 361         (powerpc_opcodes): Use RA0 as appropriate.
 362
 363 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 364
 365         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 366
 367 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 368
 369         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 370
 371 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 372
 373         * i386-dis.c (GRPPLOCK): Delete.
 374         (grps): Delete GRPPLOCK entry.
 375
 376 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 377
 378         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 379         (M, Mp): Use OP_M.
 380         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 381         (GRPPADLCK): Define.
 382         (dis386): Use NOP_Fixup on "nop".
 383         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 384         (twobyte_has_modrm): Set for 0xa7.
 385         (padlock_table): Delete.  Move to..
 386         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 387         and clflush.
 388         (print_insn): Revert PADLOCK_SPECIAL code.
 389         (OP_E): Delete sfence, lfence, mfence checks.
 390
 391 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 392
 393         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 394         (INVLPG_Fixup): New function.
 395         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 396
 397 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 398
 399         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 400         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 401         (padlock_table): New struct with PadLock instructions.
 402         (print_insn): Handle PADLOCK_SPECIAL.
 403
 404 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 405
 406         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 407         (OP_E): Twiddle clflush to sfence here.
 408
 409 2004-03-08  Nick Clifton  <nickc@redhat.com>
 410
 411         * po/de.po: Updated German translation.
 412
 413 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 414
 415         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 416         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 417         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 418         accordingly.
 419
 420 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 421
 422         * frv-asm.c: Regenerate.
 423         * frv-desc.c: Regenerate.
 424         * frv-desc.h: Regenerate.
 425         * frv-dis.c: Regenerate.
 426         * frv-ibld.c: Regenerate.
 427         * frv-opc.c: Regenerate.
 428         * frv-opc.h: Regenerate.
 429
 430 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 431
 432         * frv-desc.c, frv-opc.c: Regenerate.
 433
 434 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 435
 436         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 437
 438 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 439
 440         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 441         Also correct mistake in the comment.
 442
 443 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 444
 445         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 446         ensure that double registers have even numbers.
 447         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 448         that reserved instruction 0xfffd does not decode the same
 449         as 0xfdfd (ftrv).
 450         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 451         REG_N refers to a double register.
 452         Add REG_N_B01 nibble type and use it instead of REG_NM
 453         in ftrv.
 454         Adjust the bit patterns in a few comments.
 455
 456 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 457
 458         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 459
 460 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 461
 462         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 463
 464 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 465
 466         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 467
 468 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 469
 470         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 471         mtivor32, mtivor33, mtivor34.
 472
 473 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 474
 475         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 476
 477 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 478
 479         * arm-opc.h Maverick accumulator register opcode fixes.
 480
 481 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 482
 483         * m32r-dis.c: Regenerate.
 484
 485 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 486
 487         * sh-opc.h (sh_table): "fsrra", not "fssra".
 488
 489 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 490
 491         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 492         contraints.
 493
 494 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 495
 496         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 497
 498 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 499
 500         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 501         1.  Don't print scale factor on AT&T mode when index missing.
 502
 503 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 504
 505         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 506         when loaded into XR registers.
 507
 508 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 509
 510         * frv-desc.h: Regenerate.
 511         * frv-desc.c: Regenerate.
 512         * frv-opc.c: Regenerate.
 513
 514 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 515
 516         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 517
 518 2004-01-09  Paul Brook  <paul@codesourcery.com>
 519
 520         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 521         specific opcodes.
 522
 523 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 524
 525         * Makefile.am (libopcodes_la_DEPENDENCIES)
 526         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 527         comment about the problem.
 528         * Makefile.in: Regenerate.
 529
 530 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 531
 532         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 533         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 534         cut&paste errors in shifting/truncating numerical operands.
 535         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 536         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 537         (parse_uslo16): Likewise.
 538         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 539         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 540         (parse_s12): Likewise.
 541         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 542         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 543         (parse_uslo16): Likewise.
 544         (parse_uhi16): Parse gothi and gotfuncdeschi.
 545         (parse_d12): Parse got12 and gotfuncdesc12.
 546         (parse_s12): Likewise.
 547
 548 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 549
 550         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 551         instruction which looks similar to an 'rla' instruction.
 552
 553 For older changes see ChangeLog-0203
 554 \f
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 556 mode: change-log
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