opcodes/ChangeLog

   1 2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         AVX Programming Reference (June, 2011)
   4         * i386-dis.c (XMGatherQ): New.
   5         * i386-dis.c (EXxmm_mb): New.
   6         (EXxmm_mb): Likewise.
   7         (EXxmm_mw): Likewise.
   8         (EXxmm_md): Likewise.
   9         (EXxmm_mq): Likewise.
  10         (EXxmmdw): Likewise.
  11         (EXxmmqd): Likewise.
  12         (VexGatherQ): Likewise.
  13         (MVexVSIBDWpX): Likewise.
  14         (MVexVSIBQWpX): Likewise.
  15         (xmm_mb_mode): Likewise.
  16         (xmm_mw_mode): Likewise.
  17         (xmm_md_mode): Likewise.
  18         (xmm_mq_mode): Likewise.
  19         (xmmdw_mode): Likewise.
  20         (xmmqd_mode): Likewise.
  21         (ymmxmm_mode): Likewise.
  22         (vex_vsib_d_w_dq_mode): Likewise.
  23         (vex_vsib_q_w_dq_mode): Likewise.
  24         (MOD_VEX_0F385A_PREFIX_2): Likewise.
  25         (MOD_VEX_0F388C_PREFIX_2): Likewise.
  26         (MOD_VEX_0F388E_PREFIX_2): Likewise.
  27         (PREFIX_0F3882): Likewise.
  28         (PREFIX_VEX_0F3816): Likewise.
  29         (PREFIX_VEX_0F3836): Likewise.
  30         (PREFIX_VEX_0F3845): Likewise.
  31         (PREFIX_VEX_0F3846): Likewise.
  32         (PREFIX_VEX_0F3847): Likewise.
  33         (PREFIX_VEX_0F3858): Likewise.
  34         (PREFIX_VEX_0F3859): Likewise.
  35         (PREFIX_VEX_0F385A): Likewise.
  36         (PREFIX_VEX_0F3878): Likewise.
  37         (PREFIX_VEX_0F3879): Likewise.
  38         (PREFIX_VEX_0F388C): Likewise.
  39         (PREFIX_VEX_0F388E): Likewise.
  40         (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
  41         (PREFIX_VEX_0F38F5): Likewise.
  42         (PREFIX_VEX_0F38F6): Likewise.
  43         (PREFIX_VEX_0F3A00): Likewise.
  44         (PREFIX_VEX_0F3A01): Likewise.
  45         (PREFIX_VEX_0F3A02): Likewise.
  46         (PREFIX_VEX_0F3A38): Likewise.
  47         (PREFIX_VEX_0F3A39): Likewise.
  48         (PREFIX_VEX_0F3A46): Likewise.
  49         (PREFIX_VEX_0F3AF0): Likewise.
  50         (VEX_LEN_0F3816_P_2): Likewise.
  51         (VEX_LEN_0F3819_P_2): Likewise.
  52         (VEX_LEN_0F3836_P_2): Likewise.
  53         (VEX_LEN_0F385A_P_2_M_0): Likewise.
  54         (VEX_LEN_0F38F5_P_0): Likewise.
  55         (VEX_LEN_0F38F5_P_1): Likewise.
  56         (VEX_LEN_0F38F5_P_3): Likewise.
  57         (VEX_LEN_0F38F6_P_3): Likewise.
  58         (VEX_LEN_0F38F7_P_1): Likewise.
  59         (VEX_LEN_0F38F7_P_2): Likewise.
  60         (VEX_LEN_0F38F7_P_3): Likewise.
  61         (VEX_LEN_0F3A00_P_2): Likewise.
  62         (VEX_LEN_0F3A01_P_2): Likewise.
  63         (VEX_LEN_0F3A38_P_2): Likewise.
  64         (VEX_LEN_0F3A39_P_2): Likewise.
  65         (VEX_LEN_0F3A46_P_2): Likewise.
  66         (VEX_LEN_0F3AF0_P_3): Likewise.
  67         (VEX_W_0F3816_P_2): Likewise.
  68         (VEX_W_0F3818_P_2): Likewise.
  69         (VEX_W_0F3819_P_2): Likewise.
  70         (VEX_W_0F3836_P_2): Likewise.
  71         (VEX_W_0F3846_P_2): Likewise.
  72         (VEX_W_0F3858_P_2): Likewise.
  73         (VEX_W_0F3859_P_2): Likewise.
  74         (VEX_W_0F385A_P_2_M_0): Likewise.
  75         (VEX_W_0F3878_P_2): Likewise.
  76         (VEX_W_0F3879_P_2): Likewise.
  77         (VEX_W_0F3A00_P_2): Likewise.
  78         (VEX_W_0F3A01_P_2): Likewise.
  79         (VEX_W_0F3A02_P_2): Likewise.
  80         (VEX_W_0F3A38_P_2): Likewise.
  81         (VEX_W_0F3A39_P_2): Likewise.
  82         (VEX_W_0F3A46_P_2): Likewise.
  83         (MOD_VEX_0F3818_PREFIX_2): Removed.
  84         (MOD_VEX_0F3819_PREFIX_2): Likewise.
  85         (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
  86         (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
  87         (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
  88         (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
  89         (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
  90         (VEX_LEN_0F3A0E_P_2): Likewise.
  91         (VEX_LEN_0F3A0F_P_2): Likewise.
  92         (VEX_LEN_0F3A42_P_2): Likewise.
  93         (VEX_LEN_0F3A4C_P_2): Likewise.
  94         (VEX_W_0F3818_P_2_M_0): Likewise.
  95         (VEX_W_0F3819_P_2_M_0): Likewise.
  96         (prefix_table): Updated.
  97         (three_byte_table): Likewise.
  98         (vex_table): Likewise.
  99         (vex_len_table): Likewise.
 100         (vex_w_table): Likewise.
 101         (mod_table): Likewise.
 102         (putop): Handle "LW".
 103         (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
 104         xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
 105         vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
 106         (OP_EX): Likewise.
 107         (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
 108         vex_vsib_q_w_dq_mode.
 109         (OP_XMM): Handle vex_vsib_q_w_dq_mode.
 110         (OP_VEX): Likewise.
 111
 112         * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
 113         and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
 114         CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
 115         (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
 116         (opcode_modifiers): Add VecSIB.
 117
 118         * i386-opc.h (CpuAVX2): New.
 119         (CpuBMI2): Likewise.
 120         (CpuLZCNT): Likewise.
 121         (CpuINVPCID): Likewise.
 122         (VecSIB128): Likewise.
 123         (VecSIB256): Likewise.
 124         (VecSIB): Likewise.
 125         (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
 126         (i386_opcode_modifier): Add vecsib.
 127
 128         * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
 129         * i386-init.h: Regenerated.
 130         * i386-tbl.h: Likewise.
 131
 132 2011-06-03  Quentin Neill  <quentin.neill@amd.com>
 133
 134         * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
 135         * i386-init.h: Regenerated.
 136
 137 2011-06-03  Nick Clifton  <nickc@redhat.com>
 138
 139         PR binutils/12752
 140         * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
 141         computing address offsets.
 142         (print_arm_address): Likewise.
 143         (print_insn_arm): Likewise.
 144         (print_insn_thumb16): Likewise.
 145         (print_insn_thumb32): Likewise.
 146
 147 2011-06-02  Jie Zhang <jie@codesourcery.com>
 148             Nathan Sidwell <nathan@codesourcery.com>
 149             Maciej Rozycki <macro@codesourcery.com>
 150
 151         * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
 152         as address offset.
 153         (print_arm_address): Likewise. Elide positive #0 appropriately.
 154         (print_insn_arm): Likewise.
 155
 156 2011-06-02  Nick Clifton  <nickc@redhat.com>
 157
 158         PR gas/12752
 159         * arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
 160         passed to print_address_func.
 161
 162 2011-06-02  Nick Clifton  <nickc@redhat.com>
 163
 164         * arm-dis.c: Fix spelling mistakes.
 165         * op/opcodes.pot: Regenerate.
 166
 167 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 168
 169         * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
 170         S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
 171         * s390-opc.txt: Fix cxr instruction type.
 172
 173 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 174
 175         * s390-opc.c: Add new instruction types marking register pair
 176         operands.
 177         * s390-opc.txt: Match instructions having register pair operands
 178         to the new instruction types.
 179
 180 2011-05-19  Nick Clifton  <nickc@redhat.com>
 181
 182         * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
 183         operands.
 184
 185 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
 186
 187         * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
 188         * i386-init.h: Regenerated.
 189
 190 2011-04-27  Nick Clifton  <nickc@redhat.com>
 191
 192         * po/da.po: Updated Danish translation.
 193
 194 2011-04-26  Anton Blanchard  <anton@samba.org>
 195
 196         * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
 197
 198 2011-04-21  DJ Delorie  <dj@redhat.com>
 199
 200         * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
 201         * rx-decode.c: Regenerate.
 202
 203 2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 204
 205         * i386-init.h: Regenerated.
 206
 207 2011-04-19  Quentin Neill  <quentin.neill@amd.com>
 208
 209         * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
 210         from bdver1 flags.
 211
 212 2011-04-13  Nick Clifton  <nickc@redhat.com>
 213
 214         * v850-dis.c (disassemble): Always print a closing square brace if
 215         an opening square brace was printed.
 216
 217 2011-04-12  Nick Clifton  <nickc@redhat.com>
 218
 219         PR binutils/12534
 220         * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
 221         patterns.
 222         (print_insn_thumb32): Handle %L.
 223
 224 2011-04-11  Julian Brown  <julian@codesourcery.com>
 225
 226         * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
 227         (print_insn_thumb32): Add APSR bitmask support.
 228
 229 2011-04-07  Paul Carroll<pcarroll@codesourcery.com>
 230
 231         * arm-dis.c (print_insn): init vars moved into private_data structure.
 232
 233 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 234
 235         * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
 236
 237 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 238
 239         * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
 240         post-increment to support LPM Z+ instruction. Add support for 'E'
 241         constraint for DES instruction.
 242         (print_insn_avr): Adjust calls to avr_operand. Rename variable.
 243
 244 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 245
 246         * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
 247
 248 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 249
 250         * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
 251         Use branch types instead.
 252         (print_insn): Likewise.
 253
 254 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 255
 256         * mips-opc.c (mips_builtin_opcodes): Correct register use
 257         annotation of "alnv.ps".
 258
 259 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 260
 261         * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 262
 263 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 264
 265         * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
 266
 267 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 268
 269         * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
 270
 271 2011-02-19  Mike Frysinger  <vapier@gentoo.org>
 272
 273         * bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
 274         a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
 275         av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
 276         exception, end_of_registers, msize, memory, bfd_mach.
 277         (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
 278         LB0REG, LC1REG, LT1REG, LB1REG): Delete
 279         (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
 280         (get_allreg): Change to new defines.  Fallback to abort().
 281
 282 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 283
 284         * bfin-dis.c: Add whitespace/parenthesis where needed.
 285
 286 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 287
 288         * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
 289         than 7.
 290
 291 2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 292
 293         * configure: Regenerate.
 294
 295 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 296
 297         * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
 298
 299 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 300
 301         * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
 302         dregs only when P is set, and dregs_lo otherwise.
 303
 304 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 305
 306         * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
 307
 308 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 309
 310         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
 311
 312 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 313
 314         * bfin-dis.c (machine_registers): Delete REG_GP.
 315         (reg_names): Delete "GP".
 316         (decode_allregs): Change REG_GP to REG_LASTREG.
 317
 318 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 319
 320         * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
 321         M_IH, M_IU): Delete.
 322
 323 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 324
 325         * bfin-dis.c (reg_names): Add const.
 326         (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
 327         decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
 328         decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
 329         decode_counters, decode_allregs): Likewise.
 330
 331 2011-02-09  Michael Snyder  <msnyder@vmware.com>
 332
 333         * i386-dis.c (OP_J): Parenthesize expression to prevent
 334         truncated addresses.
 335         (print_insn): Fix indentation off-by-one.
 336
 337 2011-02-01  Nick Clifton  <nickc@redhat.com>
 338
 339         * po/da.po: Updated Danish translation.
 340
 341 2011-01-21  Dave Murphy  <davem@devkitpro.org>
 342
 343         * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
 344
 345 2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>
 346
 347         * i386-dis.c (sIbT): New.
 348         (b_T_mode): Likewise.
 349         (dis386): Replace sIb with sIbT on "pushT".
 350         (x86_64_table): Replace sIb with Ib on "aam" and "aad".
 351         (OP_sI): Handle b_T_mode.  Properly sign-extend byte.
 352
 353 2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>
 354
 355         * i386-init.h: Regenerated.
 356         * i386-tbl.h: Regenerated
 357
 358 2011-01-17  Quentin Neill  <quentin.neill@amd.com>
 359
 360         * i386-dis.c (REG_XOP_TBM_01): New.
 361         (REG_XOP_TBM_02): New.
 362         (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
 363         (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
 364         entries, and add bextr instruction.
 365
 366         * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
 367         (cpu_flags): Add CpuTBM.
 368
 369         * i386-opc.h (CpuTBM) New.
 370         (i386_cpu_flags): Add bit cputbm.
 371
 372         * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
 373         blcs, blsfill, blsic, t1mskc, and tzmsk.
 374
 375 2011-01-12  DJ Delorie  <dj@redhat.com>
 376
 377         * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
 378
 379 2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>
 380
 381         * mips-dis.c (print_insn_args): Adjust the value to print the real
 382         offset for "+c" argument.
 383
 384 2011-01-10  Nick Clifton  <nickc@redhat.com>
 385
 386         * po/da.po: Updated Danish translation.
 387
 388 2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
 389
 390         * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
 391
 392 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 393
 394         * i386-dis.c (REG_VEX_38F3): New.
 395         (PREFIX_0FBC): Likewise.
 396         (PREFIX_VEX_38F2): Likewise.
 397         (PREFIX_VEX_38F3_REG_1): Likewise.
 398         (PREFIX_VEX_38F3_REG_2): Likewise.
 399         (PREFIX_VEX_38F3_REG_3): Likewise.
 400         (PREFIX_VEX_38F7): Likewise.
 401         (VEX_LEN_38F2_P_0): Likewise.
 402         (VEX_LEN_38F3_R_1_P_0): Likewise.
 403         (VEX_LEN_38F3_R_2_P_0): Likewise.
 404         (VEX_LEN_38F3_R_3_P_0): Likewise.
 405         (VEX_LEN_38F7_P_0): Likewise.
 406         (dis386_twobyte): Use PREFIX_0FBC.
 407         (reg_table): Add REG_VEX_38F3.
 408         (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
 409         PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
 410         PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
 411         (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
 412         PREFIX_VEX_38F7.
 413         (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
 414         VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
 415         VEX_LEN_38F7_P_0.
 416
 417         * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
 418         (cpu_flags): Add CpuBMI.
 419
 420         * i386-opc.h (CpuBMI): New.
 421         (i386_cpu_flags): Add cpubmi.
 422
 423         * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
 424         * i386-init.h: Regenerated.
 425         * i386-tbl.h: Likewise.
 426
 427 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 428
 429         * i386-dis.c (VexGdq): New.
 430         (OP_VEX): Handle dq_mode.
 431
 432 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 433
 434         * i386-gen.c (process_copyright): Update copyright to 2011.
 435
 436 For older changes see ChangeLog-2010
 437 \f
 438 Local Variables:
 439 mode: change-log
 440 left-margin: 8
 441 fill-column: 74
 442 version-control: never
 443 End: