1 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
4 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
5 feature test for "s1e1rp" and "s1e1wp".
7 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
9 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
10 (aarch64_sys_ins_reg_supported_p): New.
12 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
14 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
15 with aarch64_sys_ins_reg_has_xt.
16 (aarch64_ext_sysins_op): Likewise.
17 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
19 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
20 (aarch64_sys_regs_dc): Likewise.
21 (aarch64_sys_regs_at): Likewise.
22 (aarch64_sys_regs_tlbi): Likewise.
23 (aarch64_sys_ins_reg_has_xt): New.
25 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
27 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
28 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
29 (aarch64_pstatefields): Add "uao".
30 (aarch64_pstatefield_supported_p): Add checks for "uao".
32 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
34 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
35 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
36 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
37 (aarch64_sys_reg_supported_p): Add architecture feature tests for
40 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
42 * aarch64-asm-2.c: Regenerate.
43 * aarch64-dis-2.c: Regenerate.
44 * aarch64-tbl.h (aarch64_feature_ras): New.
46 (aarch64_opcode_table): Add "esb".
48 2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
50 * i386-dis.c (MOD_0F01_REG_5): New.
51 (RM_0F01_REG_5): Likewise.
52 (reg_table): Use MOD_0F01_REG_5.
53 (mod_table): Add MOD_0F01_REG_5.
54 (rm_table): Add RM_0F01_REG_5.
55 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
56 (cpu_flags): Add CpuOSPKE.
57 * i386-opc.h (CpuOSPKE): New.
58 (i386_cpu_flags): Add cpuospke.
59 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
60 * i386-init.h: Regenerated.
61 * i386-tbl.h: Likewise.
63 2015-12-07 DJ Delorie <dj@redhat.com>
65 * rl78-decode.opc: Enable MULU for all ISAs.
66 * rl78-decode.c: Regenerate.
68 2015-12-07 Alan Modra <amodra@gmail.com>
70 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
73 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
75 * arc-dis.c (special_flag_p): Match full mnemonic.
76 * arc-opc.c (print_insn_arc): Check section size to read
77 appropriate number of bytes. Fix printing.
78 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
81 2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
83 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
86 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
88 * aarch64-asm-2.c: Regenerate.
89 * aarch64-dis-2.c: Regenerate.
90 * aarch64-opc-2.c: Regenerate.
91 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
92 (QL_INT2FP_H, QL_FP2INT_H): New.
93 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
96 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
97 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
98 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
99 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
100 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
101 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
104 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
106 * aarch64-opc.c (half_conv_t): New.
107 (expand_fp_imm): Replace is_dp flag with the parameter size to
108 specify the number of bytes for the required expansion. Treat
109 a 16-bit expansion like a 32-bit expansion. Add check for an
110 unsupported size request. Update comment.
111 (aarch64_print_operand): Update to support 16-bit floating point
112 values. Update for changes to expand_fp_imm.
114 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
116 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
119 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
121 * aarch64-asm-2.c: Regenerate.
122 * aarch64-dis-2.c: Regenerate.
123 * aarch64-opc-2.c: Regenerate.
124 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
127 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
129 * aarch64-asm-2.c: Regenerate.
130 * aarch64-asm.c (convert_bfc_to_bfm): New.
131 (convert_to_real): Add case for OP_BFC.
132 * aarch64-dis-2.c: Regenerate.
133 * aarch64-dis.c: (convert_bfm_to_bfc): New.
134 (convert_to_alias): Add case for OP_BFC.
135 * aarch64-opc-2.c: Regenerate.
136 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
137 to allow width operand in three-operand instructions.
138 * aarch64-tbl.h (QL_BF1): New.
139 (aarch64_feature_v8_2): New.
141 (aarch64_opcode_table): Add "bfc".
143 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
145 * aarch64-asm-2.c: Regenerate.
146 * aarch64-dis-2.c: Regenerate.
147 * aarch64-dis.c: Weaken assert.
148 * aarch64-gen.c: Include the instruction in the list of its
151 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
153 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
154 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
157 2015-11-23 Tristan Gingold <gingold@adacore.com>
159 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
161 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
163 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
164 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
165 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
166 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
167 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
168 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
169 cnthv_ctl_el2, cnthv_cval_el2.
170 (aarch64_sys_reg_supported_p): Update for the new system
173 2015-11-20 Nick Clifton <nickc@redhat.com>
176 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
178 2015-11-20 Nick Clifton <nickc@redhat.com>
180 * po/zh_CN.po: Updated simplified Chinese translation.
182 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
184 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
185 of MSR PAN immediate operand.
187 2015-11-16 Nick Clifton <nickc@redhat.com>
189 * rx-dis.c (condition_names): Replace always and never with
190 invalid, since the always/never conditions can never be legal.
192 2015-11-13 Tristan Gingold <gingold@adacore.com>
194 * configure: Regenerate.
196 2015-11-11 Alan Modra <amodra@gmail.com>
197 Peter Bergner <bergner@vnet.ibm.com>
199 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
200 Add PPC_OPCODE_VSX3 to the vsx entry.
201 (powerpc_init_dialect): Set default dialect to power9.
202 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
203 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
204 extract_l1 insert_xtq6, extract_xtq6): New static functions.
205 (insert_esync): Test for illegal L operand value.
206 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
207 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
208 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
209 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
210 PPCVSX3): New defines.
211 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
212 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
213 <mcrxr>: Use XBFRARB_MASK.
214 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
215 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
216 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
217 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
218 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
219 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
220 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
221 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
222 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
223 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
224 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
225 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
226 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
227 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
228 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
229 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
230 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
231 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
232 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
233 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
234 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
235 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
236 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
237 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
238 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
239 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
240 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
241 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
242 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
243 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
244 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
245 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
247 2015-11-02 Nick Clifton <nickc@redhat.com>
249 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
251 * rx-decode.c: Regenerate.
253 2015-11-02 Nick Clifton <nickc@redhat.com>
255 * rx-decode.opc (rx_disp): If the displacement is zero, set the
256 type to RX_Operand_Zero_Indirect.
257 * rx-decode.c: Regenerate.
258 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
260 2015-10-28 Yao Qi <yao.qi@linaro.org>
262 * aarch64-dis.c (aarch64_decode_insn): Add one argument
263 noaliases_p. Update comments. Pass noaliases_p rather than
264 no_aliases to aarch64_opcode_decode.
265 (print_insn_aarch64_word): Pass no_aliases to
268 2015-10-27 Vinay <Vinay.G@kpit.com>
271 * rl78-decode.opc (MOV): Added offset to DE register in index
273 * rl78-decode.c: Regenerate.
275 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
278 * rl78-decode.opc: Add 's' print operator to instructions that
279 access system registers.
280 * rl78-decode.c: Regenerate.
281 * rl78-dis.c (print_insn_rl78_common): Decode all system
284 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
287 * rl78-decode.opc: Add 'a' print operator to mov instructions
288 using stack pointer plus index addressing.
289 * rl78-decode.c: Regenerate.
291 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
293 * s390-opc.c: Fix comment.
294 * s390-opc.txt: Change instruction type for troo, trot, trto, and
295 trtt to RRF_U0RER since the second parameter does not need to be a
298 2015-10-08 Nick Clifton <nickc@redhat.com>
300 * arc-dis.c (print_insn_arc): Initiallise insn array.
302 2015-10-07 Yao Qi <yao.qi@linaro.org>
304 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
305 'name' rather than 'template'.
306 * aarch64-opc.c (aarch64_print_operand): Likewise.
308 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
310 * arc-dis.c: Revamped file for ARC support
311 * arc-dis.h: Likewise.
312 * arc-ext.c: Likewise.
313 * arc-ext.h: Likewise.
314 * arc-opc.c: Likewise.
315 * arc-fxi.h: New file.
316 * arc-regs.h: Likewise.
317 * arc-tbl.h: Likewise.
319 2015-10-02 Yao Qi <yao.qi@linaro.org>
321 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
322 argument insn type to aarch64_insn. Rename to ...
323 (aarch64_decode_insn): ... it.
324 (print_insn_aarch64_word): Caller updated.
326 2015-10-02 Yao Qi <yao.qi@linaro.org>
328 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
329 (print_insn_aarch64_word): Caller updated.
331 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
333 * s390-mkopc.c (main): Parse htm and vx flag.
334 * s390-opc.txt: Mark instructions from the hardware transactional
335 memory and vector facilities with the "htm"/"vx" flag.
337 2015-09-28 Nick Clifton <nickc@redhat.com>
339 * po/de.po: Updated German translation.
341 2015-09-28 Tom Rix <tom@bumblecow.com>
343 * ppc-opc.c (PPC500): Mark some opcodes as invalid
345 2015-09-23 Nick Clifton <nickc@redhat.com>
347 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
349 * tic30-dis.c (print_branch): Likewise.
350 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
351 value before left shifting.
352 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
353 * hppa-dis.c (print_insn_hppa): Likewise.
354 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
356 * msp430-dis.c (msp430_singleoperand): Likewise.
357 (msp430_doubleoperand): Likewise.
358 (print_insn_msp430): Likewise.
359 * nds32-asm.c (parse_operand): Likewise.
360 * sh-opc.h (MASK): Likewise.
361 * v850-dis.c (get_operand_value): Likewise.
363 2015-09-22 Nick Clifton <nickc@redhat.com>
365 * rx-decode.opc (bwl): Use RX_Bad_Size.
367 (ubwl): Likewise. Rename to ubw.
368 (uBWL): Rename to uBW.
369 Replace all references to uBWL with uBW.
370 * rx-decode.c: Regenerate.
371 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
372 (opsize_names): Likewise.
373 (print_insn_rx): Detect and report RX_Bad_Size.
375 2015-09-22 Anton Blanchard <anton@samba.org>
377 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
379 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
381 * sparc-dis.c (print_insn_sparc): Handle the privileged register
384 2015-08-24 Jan Stancek <jstancek@redhat.com>
386 * i386-dis.c (print_insn): Fix decoding of three byte operands.
388 2015-08-21 Alexander Fomin <alexander.fomin@intel.com>
391 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
392 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
393 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
394 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
395 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
396 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
397 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
398 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
399 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
400 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
401 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
402 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
403 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
404 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
405 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
406 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
407 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
408 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
409 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
410 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
411 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
412 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
413 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
414 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
415 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
416 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
417 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
418 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
419 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
420 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
421 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
422 (vex_w_table): Replace terminals with MOD_TABLE entries for
423 most of mask instructions.
425 2015-08-17 Alan Modra <amodra@gmail.com>
427 * cgen.sh: Trim trailing space from cgen output.
428 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
429 (print_dis_table): Likewise.
430 * opc2c.c (dump_lines): Likewise.
431 (orig_filename): Warning fix.
432 * ia64-asmtab.c: Regenerate.
434 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
436 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
437 and higher with ARM instruction set will now mark the 26-bit
438 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
439 (arm_opcodes): Fix for unpredictable nop being recognized as a
442 2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
444 * micromips-opc.c (micromips_opcodes): Re-order table so that move
445 based on 'or' is first.
446 * mips-opc.c (mips_builtin_opcodes): Ditto.
448 2015-08-11 Nick Clifton <nickc@redhat.com>
451 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
454 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
456 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
458 2015-08-07 Amit Pawar <Amit.Pawar@amd.com>
460 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
461 * i386-init.h: Regenerated.
463 2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
466 * i386-dis.c (MOD_0FC3): New.
467 (PREFIX_0FC3): Renamed to ...
468 (PREFIX_MOD_0_0FC3): This.
469 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
470 (prefix_table): Replace Ma with Ev on movntiS.
471 (mod_table): Add MOD_0FC3.
473 2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
475 * configure: Regenerated.
477 2015-07-23 Alan Modra <amodra@gmail.com>
480 * i386-dis.c (get64): Avoid signed integer overflow.
482 2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
485 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
486 "EXEvexHalfBcstXmmq" for the second operand.
487 (EVEX_W_0F79_P_2): Likewise.
488 (EVEX_W_0F7A_P_2): Likewise.
489 (EVEX_W_0F7B_P_2): Likewise.
491 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
493 * arm-dis.c (print_insn_coprocessor): Added support for quarter
494 float bitfield format.
495 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
496 quarter float bitfield format.
498 2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
500 * configure: Regenerated.
502 2015-07-03 Alan Modra <amodra@gmail.com>
504 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
505 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
506 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
508 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
509 Cesar Philippidis <cesar@codesourcery.com>
511 * nios2-dis.c (nios2_extract_opcode): New.
512 (nios2_disassembler_state): New.
513 (nios2_find_opcode_hash): Use mach parameter to select correct
515 (nios2_print_insn_arg): Extend to support new R2 argument letters
517 (print_insn_nios2): Check for 16-bit instruction at end of memory.
518 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
519 (NIOS2_NUM_OPCODES): Rename to...
520 (NIOS2_NUM_R1_OPCODES): This.
521 (nios2_r2_opcodes): New.
522 (NIOS2_NUM_R2_OPCODES): New.
523 (nios2_num_r2_opcodes): New.
524 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
525 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
526 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
527 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
528 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
530 2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
532 * i386-dis.c (OP_Mwaitx): New.
533 (rm_table): Add monitorx/mwaitx.
534 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
535 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
536 (operand_type_init): Add CpuMWAITX.
537 * i386-opc.h (CpuMWAITX): New.
538 (i386_cpu_flags): Add cpumwaitx.
539 * i386-opc.tbl: Add monitorx and mwaitx.
540 * i386-init.h: Regenerated.
541 * i386-tbl.h: Likewise.
543 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
545 * ppc-opc.c (insert_ls): Test for invalid LS operands.
546 (insert_esync): New function.
547 (LS, WC): Use insert_ls.
548 (ESYNC): Use insert_esync.
550 2015-06-22 Nick Clifton <nickc@redhat.com>
552 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
553 requested region lies beyond it.
554 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
555 looking for 32-bit insns.
556 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
558 * sh-dis.c (print_insn_sh): Likewise.
559 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
560 blocks of instructions.
561 * vax-dis.c (print_insn_vax): Check that the requested address
562 does not clash with the stop_vma.
564 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
566 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
567 * ppc-opc.c (FXM4): Add non-zero optional value.
570 (insert_fxm): Handle new default operand value.
571 (extract_fxm): Likewise.
572 (insert_tbr): Likewise.
573 (extract_tbr): Likewise.
575 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
577 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
579 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
581 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
583 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
585 * ppc-opc.c: Add comment accidentally removed by old commit.
588 2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
590 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
592 2015-06-04 Nick Clifton <nickc@redhat.com>
595 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
597 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
599 * arm-dis.c (arm_opcodes): Add "setpan".
600 (thumb_opcodes): Add "setpan".
602 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
604 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
607 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
609 * aarch64-tbl.h (aarch64_feature_rdma): New.
611 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
612 * aarch64-asm-2.c: Regenerate.
613 * aarch64-dis-2.c: Regenerate.
614 * aarch64-opc-2.c: Regenerate.
616 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
618 * aarch64-tbl.h (aarch64_feature_lor): New.
620 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
622 * aarch64-asm-2.c: Regenerate.
623 * aarch64-dis-2.c: Regenerate.
624 * aarch64-opc-2.c: Regenerate.
626 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
628 * aarch64-opc.c (F_ARCHEXT): New.
629 (aarch64_sys_regs): Add "pan".
630 (aarch64_sys_reg_supported_p): New.
631 (aarch64_pstatefields): Add "pan".
632 (aarch64_pstatefield_supported_p): New.
634 2015-06-01 Jan Beulich <jbeulich@suse.com>
636 * i386-tbl.h: Regenerate.
638 2015-06-01 Jan Beulich <jbeulich@suse.com>
640 * i386-dis.c (print_insn): Swap rounding mode specifier and
641 general purpose register in Intel mode.
643 2015-06-01 Jan Beulich <jbeulich@suse.com>
645 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
646 * i386-tbl.h: Regenerate.
648 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
650 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
651 * i386-init.h: Regenerated.
653 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
656 * i386-dis.c: Add comments for '@'.
657 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
658 (enum x86_64_isa): New.
660 (print_i386_disassembler_options): Add amd64 and intel64.
661 (print_insn): Handle amd64 and intel64.
663 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
664 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
665 * i386-opc.h (AMD64): New.
666 (CpuIntel64): Likewise.
667 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
668 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
669 Mark direct call/jmp without Disp16|Disp32 as Intel64.
670 * i386-init.h: Regenerated.
671 * i386-tbl.h: Likewise.
673 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
675 * ppc-opc.c (IH) New define.
676 (powerpc_opcodes) <wait>: Do not enable for POWER7.
677 <tlbie>: Add RS operand for POWER7.
678 <slbia>: Add IH operand for POWER6.
680 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
682 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
685 * i386-tbl.h: Regenerated.
687 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
689 * configure.ac: Support bfd_iamcu_arch.
690 * disassemble.c (disassembler): Support bfd_iamcu_arch.
691 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
692 CPU_IAMCU_COMPAT_FLAGS.
693 (cpu_flags): Add CpuIAMCU.
694 * i386-opc.h (CpuIAMCU): New.
695 (i386_cpu_flags): Add cpuiamcu.
696 * configure: Regenerated.
697 * i386-init.h: Likewise.
698 * i386-tbl.h: Likewise.
700 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
703 * i386-dis.c (X86_64_E8): New.
704 (X86_64_E9): Likewise.
705 Update comments on 'T', 'U', 'V'. Add comments for '^'.
706 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
707 (x86_64_table): Add X86_64_E8 and X86_64_E9.
708 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
710 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
713 2015-04-30 DJ Delorie <dj@redhat.com>
715 * disassemble.c (disassembler): Choose suitable disassembler based
717 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
718 it to decode mul/div insns.
719 * rl78-decode.c: Regenerate.
720 * rl78-dis.c (print_insn_rl78): Rename to...
721 (print_insn_rl78_common): ...this, take ISA parameter.
722 (print_insn_rl78): New.
723 (print_insn_rl78_g10): New.
724 (print_insn_rl78_g13): New.
725 (print_insn_rl78_g14): New.
726 (rl78_get_disassembler): New.
728 2015-04-29 Nick Clifton <nickc@redhat.com>
730 * po/fr.po: Updated French translation.
732 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
734 * ppc-opc.c (DCBT_EO): New define.
735 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
739 <waitrsv>: Do not enable for POWER7 and later.
740 <waitimpl>: Likewise.
741 <dcbt>: Default to the two operand form of the instruction for all
742 "old" cpus. For "new" cpus, use the operand ordering that matches
743 whether the cpu is server or embedded.
746 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
748 * s390-opc.c: New instruction type VV0UU2.
749 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
752 2015-04-23 Jan Beulich <jbeulich@suse.com>
754 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
755 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
756 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
757 (vfpclasspd, vfpclassps): Add %XZ.
759 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
761 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
762 (PREFIX_UD_REPZ): Likewise.
763 (PREFIX_UD_REPNZ): Likewise.
764 (PREFIX_UD_DATA): Likewise.
765 (PREFIX_UD_ADDR): Likewise.
766 (PREFIX_UD_LOCK): Likewise.
768 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
770 * i386-dis.c (prefix_requirement): Removed.
771 (print_insn): Don't set prefix_requirement. Check
772 dp->prefix_requirement instead of prefix_requirement.
774 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
777 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
778 (PREFIX_MOD_0_0FC7_REG_6): This.
779 (PREFIX_MOD_3_0FC7_REG_6): New.
780 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
781 (prefix_table): Replace PREFIX_0FC7_REG_6 with
782 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
783 PREFIX_MOD_3_0FC7_REG_7.
784 (mod_table): Replace PREFIX_0FC7_REG_6 with
785 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
786 PREFIX_MOD_3_0FC7_REG_7.
788 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
790 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
791 (PREFIX_MANDATORY_REPNZ): Likewise.
792 (PREFIX_MANDATORY_DATA): Likewise.
793 (PREFIX_MANDATORY_ADDR): Likewise.
794 (PREFIX_MANDATORY_LOCK): Likewise.
795 (PREFIX_MANDATORY): Likewise.
796 (PREFIX_UD_SHIFT): Set to 8
797 (PREFIX_UD_REPZ): Updated.
798 (PREFIX_UD_REPNZ): Likewise.
799 (PREFIX_UD_DATA): Likewise.
800 (PREFIX_UD_ADDR): Likewise.
801 (PREFIX_UD_LOCK): Likewise.
802 (PREFIX_IGNORED_SHIFT): New.
803 (PREFIX_IGNORED_REPZ): Likewise.
804 (PREFIX_IGNORED_REPNZ): Likewise.
805 (PREFIX_IGNORED_DATA): Likewise.
806 (PREFIX_IGNORED_ADDR): Likewise.
807 (PREFIX_IGNORED_LOCK): Likewise.
808 (PREFIX_OPCODE): Likewise.
809 (PREFIX_IGNORED): Likewise.
810 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
811 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
812 (three_byte_table): Likewise.
813 (mod_table): Likewise.
814 (mandatory_prefix): Renamed to ...
815 (prefix_requirement): This.
816 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
817 Update PREFIX_90 entry.
818 (get_valid_dis386): Check prefix_requirement to see if a prefix
820 (print_insn): Replace mandatory_prefix with prefix_requirement.
822 2015-04-15 Renlin Li <renlin.li@arm.com>
824 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
825 use it for ssat and ssat16.
826 (print_insn_thumb32): Add handle case for 'D' control code.
828 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
829 H.J. Lu <hongjiu.lu@intel.com>
831 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
832 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
833 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
834 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
835 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
836 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
837 Fill prefix_requirement field.
838 (struct dis386): Add prefix_requirement field.
839 (dis386): Fill prefix_requirement field.
840 (dis386_twobyte): Ditto.
841 (twobyte_has_mandatory_prefix_: Remove.
842 (reg_table): Fill prefix_requirement field.
843 (prefix_table): Ditto.
844 (x86_64_table): Ditto.
845 (three_byte_table): Ditto.
848 (vex_len_table): Ditto.
849 (vex_w_table): Ditto.
852 (print_insn): Use prefix_requirement.
853 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
854 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
857 2015-03-30 Mike Frysinger <vapier@gentoo.org>
859 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
861 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
863 * Makefile.in: Regenerated.
865 2015-03-25 Anton Blanchard <anton@samba.org>
867 * ppc-dis.c (disassemble_init_powerpc): Only initialise
868 powerpc_opcd_indices and vle_opcd_indices once.
870 2015-03-25 Anton Blanchard <anton@samba.org>
872 * ppc-opc.c (powerpc_opcodes): Add slbfee.
874 2015-03-24 Terry Guo <terry.guo@arm.com>
876 * arm-dis.c (opcode32): Updated to use new arm feature struct.
877 (opcode16): Likewise.
878 (coprocessor_opcodes): Replace bit with feature struct.
879 (neon_opcodes): Likewise.
880 (arm_opcodes): Likewise.
881 (thumb_opcodes): Likewise.
882 (thumb32_opcodes): Likewise.
883 (print_insn_coprocessor): Likewise.
884 (print_insn_arm): Likewise.
885 (select_arm_features): Follow new feature struct.
887 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
889 * i386-dis.c (rm_table): Add clzero.
890 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
891 Add CPU_CLZERO_FLAGS.
892 (cpu_flags): Add CpuCLZERO.
893 * i386-opc.h: Add CpuCLZERO.
894 * i386-opc.tbl: Add clzero.
895 * i386-init.h: Re-generated.
896 * i386-tbl.h: Re-generated.
898 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
900 * mips-opc.c (decode_mips_operand): Fix constraint issues
901 with u and y operands.
903 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
905 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
907 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
909 * s390-opc.c: Add new IBM z13 instructions.
910 * s390-opc.txt: Likewise.
912 2015-03-10 Renlin Li <renlin.li@arm.com>
914 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
915 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
917 * aarch64-asm-2.c: Regenerate.
918 * aarch64-dis-2.c: Likewise.
919 * aarch64-opc-2.c: Likewise.
921 2015-03-03 Jiong Wang <jiong.wang@arm.com>
923 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
925 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
927 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
929 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
930 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
932 2015-02-23 Vinay <Vinay.G@kpit.com>
934 * rl78-decode.opc (MOV): Added space between two operands for
935 'mov' instruction in index addressing mode.
936 * rl78-decode.c: Regenerate.
938 2015-02-19 Pedro Alves <palves@redhat.com>
940 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
942 2015-02-10 Pedro Alves <palves@redhat.com>
943 Tom Tromey <tromey@redhat.com>
945 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
946 microblaze_and, microblaze_xor.
947 * microblaze-opc.h (opcodes): Adjust.
949 2015-01-28 James Bowman <james.bowman@ftdichip.com>
951 * Makefile.am: Add FT32 files.
952 * configure.ac: Handle FT32.
953 * disassemble.c (disassembler): Call print_insn_ft32.
954 * ft32-dis.c: New file.
955 * ft32-opc.c: New file.
956 * Makefile.in: Regenerate.
957 * configure: Regenerate.
958 * po/POTFILES.in: Regenerate.
960 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
962 * nds32-asm.c (keyword_sr): Add new system registers.
964 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
966 * s390-dis.c (s390_extract_operand): Support vector register
968 (s390_print_insn_with_opcode): Support new operands types and add
969 new handling of optional operands.
970 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
971 and include opcode/s390.h instead.
972 (struct op_struct): New field `flags'.
973 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
974 (dumpTable): Dump flags.
975 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
977 * s390-opc.c: Add new operands types, instruction formats, and
979 (s390_opformats): Add new formats for .insn.
980 * s390-opc.txt: Add new instructions.
982 2015-01-01 Alan Modra <amodra@gmail.com>
984 Update year range in copyright notice of all files.
986 For older changes see ChangeLog-2014
988 Copyright (C) 2015 Free Software Foundation, Inc.
990 Copying and distribution of this file, with or without modification,
991 are permitted in any medium without royalty provided the copyright
992 notice and this notice are preserved.
998 version-control: never