opcodes/ChangeLog

   1 2020-08-26  David Faust  <david.faust@oracle.com>
   2
   3         * bpf-desc.c: Regenerate.
   4         * bpf-desc.h: Likewise.
   5         * bpf-opc.c: Likewise.
   6         * bpf-opc.h: Likewise.
   7         * disassemble.c (disassemble_init_for_target): Set bits for xBPF
   8         ISA when appropriate.
   9
  10 2020-08-25  Alan Modra  <amodra@gmail.com>
  11
  12         PR 26504
  13         * vax-dis.c (parse_disassembler_options): Always add at least one
  14         to entry_addr_total_slots.
  15
  16 2020-08-24  Cooper Qu  <cooper.qu@linux.alibaba.com>
  17
  18         * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
  19         in other CPUs to speed up disassembling.
  20         * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
  21         Change plsli.u16 to plsli.16, change sync's operand format.
  22
  23 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
  24
  25         * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
  26
  27 2020-08-21  Nick Clifton  <nickc@redhat.com>
  28
  29         * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
  30         symbols.
  31
  32 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
  33
  34         * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
  35
  36 2020-08-19  Alan Modra  <amodra@gmail.com>
  37
  38         * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
  39         vcmpuq and xvtlsbb.
  40
  41 2020-08-18  Peter Bergner  <bergner@linux.ibm.com>
  42
  43         * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
  44         <xvcvbf16spn>: ...to this.
  45
  46 2020-08-12  Alex Coplan  <alex.coplan@arm.com>
  47
  48         * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
  49
  50 2020-08-12  Nick Clifton  <nickc@redhat.com>
  51
  52         * po/sr.po: Updated Serbian translation.
  53
  54 2020-08-11  Alan Modra  <amodra@gmail.com>
  55
  56         * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
  57
  58 2020-08-10  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  59
  60         * aarch64-opc.c (aarch64_print_operand):
  61         (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
  62         (aarch64_sys_reg_supported_p): Function removed.
  63         (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
  64         (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
  65         into this function.
  66
  67 2020-08-10  Alan Modra  <amodra@gmail.com>
  68
  69         * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
  70         instructions.
  71
  72 2020-08-10  Alan Modra  <amodra@gmail.com>
  73
  74         * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
  75         Enable icbt for power5, miso for power8.
  76
  77 2020-08-10  Alan Modra  <amodra@gmail.com>
  78
  79         * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
  80         mtvsrd, and similarly for mfvsrd.
  81
  82 2020-08-04  Christian Groessler  <chris@groessler.org>
  83             Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
  84
  85         * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
  86         opcodes (special "out" to absolute address).
  87         * z8k-opc.h: Regenerate.
  88
  89 2020-07-30  H.J. Lu  <hongjiu.lu@intel.com>
  90
  91         PR gas/26305
  92         * i386-opc.h (Prefix_Disp8): New.
  93         (Prefix_Disp16): Likewise.
  94         (Prefix_Disp32): Likewise.
  95         (Prefix_Load): Likewise.
  96         (Prefix_Store): Likewise.
  97         (Prefix_VEX): Likewise.
  98         (Prefix_VEX3): Likewise.
  99         (Prefix_EVEX): Likewise.
 100         (Prefix_REX): Likewise.
 101         (Prefix_NoOptimize): Likewise.
 102         * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes.  Add {disp16}.
 103         * i386-tbl.h: Regenerated.
 104
 105 2020-07-29  Andreas Arnez  <arnez@linux.ibm.com>
 106
 107         * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
 108         default case with abort() instead of printing an error message and
 109         continuing, to avoid a maybe-uninitialized warning.
 110
 111 2020-07-24  Nick Clifton  <nickc@redhat.com>
 112
 113         * po/de.po: Updated German translation.
 114
 115 2020-07-21  Jan Beulich  <jbeulich@suse.com>
 116
 117         * i386-dis.c (OP_E_memory): Revert previous change.
 118
 119 2020-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 120
 121         PR gas/26237
 122         * i386-dis.c (OP_E_memory): Don't display eiz with no scale
 123         without base nor index registers.
 124
 125 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-dis.c (putop): Move 'V' and 'W' handling.
 128
 129 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 130
 131         * i386-dis.c (dis386): Adjust 'V' description. Use P-based
 132         construct for push/pop of register.
 133         (putop): Honor cond when handling 'P'. Drop handling of plain
 134         'V'.
 135
 136 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 137
 138         * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
 139         description. Drop '&' description. Use P for push of immediate,
 140         pushf/popf, enter, and leave. Use %LP for lret/retf.
 141         (dis386_twobyte): Use P for push/pop of fs/gs.
 142         (reg_table): Use P for push/pop. Use @ for near call/jmp.
 143         (x86_64_table): Use P for far call/jmp.
 144         (putop): Drop handling of 'U' and '&'. Move and adjust handling
 145         of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
 146         labels.
 147         (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
 148         and dqw_mode (unconditional).
 149
 150 2020-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 151
 152         PR gas/26237
 153         * i386-dis.c (OP_E_memory): Without base nor index registers,
 154         32-bit displacement to 64 bits.
 155
 156 2020-07-14  Claudiu Zissulescu  <claziss@gmail.com>
 157
 158         * arc-dis.c (print_insn_arc): Detect and emit a warning when a
 159         faulty double register pair is detected.
 160
 161 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 162
 163         * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
 164
 165 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 166
 167         * i386-dis.c (OP_R, Rm): Delete.
 168         (MOD_0F24, MOD_0F26): Rename to ...
 169         (X86_64_0F24, X86_64_0F26): ... respectively.
 170         (dis386): Update 'L' and 'Z' comments.
 171         (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
 172         table references.
 173         (mod_table): Move opcode 0F24 and 0F26 entries ...
 174         (x86_64_table): ... here.
 175         (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
 176         'Z' case block.
 177
 178 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 179
 180         * i386-dis.c (Rd, Rdq, MaskR): Delete.
 181         (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
 182         MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
 183         MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
 184         MOD_EVEX_0F387C): New enumerators.
 185         (reg_table): Use Edq for rdssp.
 186         (prefix_table): Use Edq for incssp.
 187         (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
 188         kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
 189         ktest*, and kshift*. Use Edq / MaskE for kmov*.
 190         * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
 191         * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
 192         0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
 193         * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
 194         0F3828_P_1 and 0F3838_P_1.
 195         * i386-dis-evex-w.h: Reference mod_table[] for opcodes
 196         0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
 197
 198 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 199
 200         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
 201         PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
 202         PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
 203         PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
 204         PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
 205         PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
 206         (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
 207         VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
 208         VEX_LEN_0F38F3_R_3_P_0): Rename to ...
 209         (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
 210         VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
 211         (reg_table, prefix_table, three_byte_table, vex_table,
 212         vex_len_table, mod_table, rm_table): Replace / remove respective
 213         entries.
 214         (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
 215         of PREFIX_DATA in used_prefixes.
 216
 217 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 218
 219         * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
 220         MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
 221         MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
 222         MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
 223         (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
 224         MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
 225         (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
 226         VEX_W_0F3A33_L_0): Delete.
 227         (dis386): Adjust "BW" description.
 228         (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
 229         0F3A31, 0F3A32, and 0F3A33.
 230         (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
 231         entries.
 232         (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
 233         entries.
 234
 235 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 236
 237         * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
 238         PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
 239         PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
 240         PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
 241         PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
 242         PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
 243         PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
 244         PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
 245         PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
 246         PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
 247         PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
 248         PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
 249         PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
 250         PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
 251         PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
 252         PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
 253         PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
 254         PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
 255         PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
 256         PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
 257         PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
 258         PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
 259         PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
 260         PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
 261         PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
 262         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 263         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 264         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
 265         PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
 266         PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 267         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 268         PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
 269         PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
 270         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 271         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 272         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 273         PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
 274         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 275         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 276         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
 277         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 278         PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
 279         PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
 280         PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
 281         PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
 282         PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
 283         PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
 284         PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
 285         PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
 286         PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
 287         PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
 288         PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
 289         PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
 290         PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
 291         PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
 292         PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
 293         PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
 294         PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 295         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 296         PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
 297         PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
 298         PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
 299         PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
 300         PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
 301         PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
 302         PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
 303         PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
 304         PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
 305         PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
 306         PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
 307         PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
 308         PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
 309         PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
 310         PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
 311         PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
 312         PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
 313         PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
 314         PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
 315         PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
 316         PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
 317         PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
 318         PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
 319         PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
 320         PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
 321         PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
 322         PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
 323         PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
 324         PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
 325         PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
 326         PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
 327         PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
 328         PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
 329         PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
 330         PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
 331         PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
 332         PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
 333         PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
 334         PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
 335         PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
 336         PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
 337         PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
 338         PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
 339         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
 340         PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
 341         PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
 342         PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 343         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 344         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 345         PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
 346         PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
 347         PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 348         PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
 349         PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
 350         PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
 351         PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
 352         PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
 353         PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 354         PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
 355         PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
 356         PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
 357         PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
 358         PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
 359         PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
 360         PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
 361         PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
 362         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
 363         PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
 364         PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
 365         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
 366         PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
 367         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 368         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
 369         PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
 370         PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
 371         PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
 372         PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
 373         PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
 374         PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
 375         PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
 376         PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
 377         PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
 378         PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
 379         PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
 380         PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
 381         PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
 382         PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
 383         PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
 384         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
 385         PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
 386         PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
 387         PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
 388         PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
 389         PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
 390         PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
 391         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 392         PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 393         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
 394         (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
 395         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 396         MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
 397         MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
 398         MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
 399         MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
 400         MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 401         MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 402         MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 403         MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 404         MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
 405         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
 406         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
 407         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
 408         MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
 409         VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
 410         VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
 411         VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
 412         VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
 413         VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
 414         VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
 415         VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
 416         VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
 417         VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
 418         VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
 419         VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
 420         VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
 421         VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
 422         EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
 423         EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
 424         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
 425         EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
 426         EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
 427         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
 428         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
 429         EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
 430         EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
 431         EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
 432         EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
 433         EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
 434         EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
 435         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
 436         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
 437         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
 438         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 439         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 440         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 441         EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
 442         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
 443         EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
 444         EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
 445         EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
 446         EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
 447         EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
 448         EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
 449         VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
 450         VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
 451         VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
 452         VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
 453         VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
 454         VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
 455         VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
 456         VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
 457         VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
 458         VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
 459         VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
 460         VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
 461         VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
 462         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
 463         VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
 464         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
 465         VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
 466         VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
 467         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
 468         EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
 469         EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
 470         EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
 471         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
 472         EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 473         EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
 474         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
 475         EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
 476         EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
 477         EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
 478         EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 479         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
 480         EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
 481         EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 482         EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 483         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
 484         EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
 485         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 486         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
 487         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
 488         EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 489         EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
 490         EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
 491         EVEX_W_0F3A72_P_2): Rename to ...
 492         (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
 493         MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
 494         MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
 495         MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
 496         MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
 497         MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
 498         MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
 499         MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
 500         MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
 501         MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
 502         MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
 503         VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
 504         VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
 505         VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
 506         VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
 507         VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
 508         VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
 509         VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
 510         VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
 511         VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
 512         EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 513         EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 514         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 515         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 516         EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
 517         EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
 518         EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
 519         EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
 520         EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
 521         EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
 522         EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
 523         EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
 524         EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
 525         EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 526         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
 527         EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 528         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
 529         EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
 530         EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
 531         EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
 532         EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 533         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
 534         EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
 535         EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 536         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
 537         VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
 538         VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
 539         VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
 540         VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
 541         VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
 542         VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
 543         VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
 544         VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
 545         VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
 546         VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
 547         VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
 548         VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
 549         VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
 550         EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
 551         EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
 552         EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
 553         EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
 554         EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
 555         EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
 556         EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
 557         EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
 558         EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
 559         EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
 560         EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
 561         EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
 562         EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
 563         EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
 564         respectively.
 565         (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
 566         vex_w_table, mod_table): Replace / remove respective entries.
 567         (print_insn): Move up dp->prefix_requirement handling. Handle
 568         PREFIX_DATA.
 569         * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
 570         i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
 571         Replace / remove respective entries.
 572
 573 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 574
 575         * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 576         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
 577         (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
 578         vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
 579         Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
 580         the latter two.
 581         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
 582         0F2C, 0F2D, 0F2E, and 0F2F.
 583         * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
 584         0F2F table entries.
 585
 586 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 587
 588         * i386-dis.c (OP_VexR, VexScalarR): New.
 589         (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
 590         XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
 591         need_vex_reg): Delete.
 592         (prefix_table): Replace VexScalar by VexScalarR and
 593         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
 594         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
 595         (vex_len_table): Replace EXqVexScalarS by EXqS.
 596         (get_valid_dis386): Don't set need_vex_reg.
 597         (print_insn): Don't initialize need_vex_reg.
 598         (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
 599         q_scalar_swap_mode cases.
 600         (OP_EX): Don't check for d_scalar_swap_mode and
 601         q_scalar_swap_mode.
 602         (OP_VEX): Done check need_vex_reg.
 603         * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
 604         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
 605         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
 606
 607 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 608
 609         * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
 610         (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
 611         VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
 612         VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
 613         (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
 614         VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
 615         VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
 616         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
 617         (vex_table): Replace Vex128 by Vex.
 618         (vex_len_table): Likewise. Adjust referenced enum names.
 619         (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
 620         referenced enum names.
 621         (OP_VEX): Drop vex128_mode and vex256_mode cases.
 622         * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
 623
 624 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 625
 626         * i386-dis.c (dis386): "LW" description now applies to "DQ".
 627         (putop): Handle "DQ". Don't handle "LW" anymore.
 628         (prefix_table, mod_table): Replace %LW by %DQ.
 629         * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
 630
 631 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 632
 633         * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
 634         dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
 635         d_scalar_swap_mode case handling. Move shift adjsutment into
 636         the case its applicable to.
 637
 638 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 639
 640         * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
 641         (EXbScalar, EXwScalar): Fold to ...
 642         (EXbwUnit): ... this.
 643         (b_scalar_mode, w_scalar_mode): Fold to ...
 644         (bw_unit_mode): ... this.
 645         (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
 646         w_scalar_mode handling by bw_unit_mode one.
 647         * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
 648         ...
 649         * i386-dis-evex-prefix.h: ... here.
 650
 651 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 652
 653         * i386-dis.c (PCMPESTR_Fixup): Delete.
 654         (dis386): Adjust "LQ" description.
 655         (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
 656         cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
 657         PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
 658         vpcmpestrm, and vpcmpestri.
 659         (putop): Honor "cond" when handling LQ.
 660         * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
 661         vcvtsi2ss and vcvtusi2ss.
 662         * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
 663         vcvtsi2sd and vcvtusi2sd.
 664
 665 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 666
 667         * i386-dis.c (VCMP_Fixup, VCMP): Delete.
 668         (simd_cmp_op): Add const.
 669         (vex_cmp_op): Move up and drop initial 8 entries. Add const.
 670         (CMP_Fixup): Handle VEX case.
 671         (prefix_table): Replace VCMP by CMP.
 672         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
 673
 674 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 675
 676         * i386-dis.c (MOVBE_Fixup): Delete.
 677         (Mv): Define.
 678         (prefix_table): Use Mv for movbe entries.
 679
 680 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 681
 682         * i386-dis.c (CRC32_Fixup): Delete.
 683         (prefix_table): Use Eb/Ev for crc32 entries.
 684
 685 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 686
 687         * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
 688         Conditionalize invocations of "USED_REX (0)".
 689
 690 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 691
 692         * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
 693         CH, DH, BH, AX, DX): Delete.
 694         (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
 695         eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
 696         dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
 697
 698 2020-07-10  Lili Cui  <lili.cui@intel.com>
 699
 700         * i386-dis.c (TMM): New.
 701         (EXtmm): Likewise.
 702         (VexTmm): Likewise.
 703         (MVexSIBMEM): Likewise.
 704         (tmm_mode): Likewise.
 705         (vex_sibmem_mode): Likewise.
 706         (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
 707         (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
 708         (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
 709         (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
 710         (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
 711         (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
 712         (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
 713         (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
 714         (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
 715         (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
 716         (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
 717         (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
 718         (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
 719         (PREFIX_VEX_0F3849_X86_64): Likewise.
 720         (PREFIX_VEX_0F384B_X86_64): Likewise.
 721         (PREFIX_VEX_0F385C_X86_64): Likewise.
 722         (PREFIX_VEX_0F385E_X86_64): Likewise.
 723         (X86_64_VEX_0F3849): Likewise.
 724         (X86_64_VEX_0F384B): Likewise.
 725         (X86_64_VEX_0F385C): Likewise.
 726         (X86_64_VEX_0F385E): Likewise.
 727         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
 728         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
 729         (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
 730         (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
 731         (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
 732         (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
 733         (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
 734         (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
 735         (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
 736         (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
 737         (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
 738         (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
 739         (VEX_W_0F3849_X86_64_P_0): Likewise.
 740         (VEX_W_0F3849_X86_64_P_2): Likewise.
 741         (VEX_W_0F3849_X86_64_P_3): Likewise.
 742         (VEX_W_0F384B_X86_64_P_1): Likewise.
 743         (VEX_W_0F384B_X86_64_P_2): Likewise.
 744         (VEX_W_0F384B_X86_64_P_3): Likewise.
 745         (VEX_W_0F385C_X86_64_P_1): Likewise.
 746         (VEX_W_0F385E_X86_64_P_0): Likewise.
 747         (VEX_W_0F385E_X86_64_P_1): Likewise.
 748         (VEX_W_0F385E_X86_64_P_2): Likewise.
 749         (VEX_W_0F385E_X86_64_P_3): Likewise.
 750         (names_tmm): Likewise.
 751         (att_names_tmm): Likewise.
 752         (intel_operand_size): Handle void_mode.
 753         (OP_XMM): Handle tmm_mode.
 754         (OP_EX): Likewise.
 755         (OP_VEX): Likewise.
 756         * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
 757         CpuAMX_BF16 and CpuAMX_TILE.
 758         (operand_type_shorthands): Add RegTMM.
 759         (operand_type_init): Likewise.
 760         (operand_types): Add Tmmword.
 761         (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
 762         (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
 763         * i386-opc.h (CpuAMX_INT8): New.
 764         (CpuAMX_BF16): Likewise.
 765         (CpuAMX_TILE): Likewise.
 766         (SIBMEM): Likewise.
 767         (Tmmword): Likewise.
 768         (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
 769         (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
 770         (i386_operand_type): Add tmmword.
 771         * i386-opc.tbl: Add AMX instructions.
 772         * i386-reg.tbl: Add AMX registers.
 773         * i386-init.h: Regenerated.
 774         * i386-tbl.h: Likewise.
 775
 776 2020-07-08  Jan Beulich  <jbeulich@suse.com>
 777
 778         * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
 779         (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
 780         Rename to ...
 781         (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 782         REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
 783         respectively.
 784         (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
 785         VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
 786         VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
 787         VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
 788         VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
 789         VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
 790         VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
 791         VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
 792         VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
 793         VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
 794         VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
 795         VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
 796         VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
 797         VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
 798         VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
 799         VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
 800         VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
 801         VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
 802         VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
 803         VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
 804         VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
 805         VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
 806         VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
 807         VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
 808         VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
 809         VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
 810         VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
 811         VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
 812         VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
 813         VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
 814         VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
 815         VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
 816         VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
 817         VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
 818         VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
 819         VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
 820         (reg_table): Re-order XOP entries. Adjust their operands.
 821         (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
 822         08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
 823         08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
 824         09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
 825         09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
 826         09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
 827         entries by references ...
 828         (vex_len_table): ... to resepctive new entries here. For several
 829         new and existing entries reference ...
 830         (vex_w_table): ... new entries here.
 831         (mod_table): New MOD_VEX_0FXOP_09_12 entry.
 832
 833 2020-07-08  Jan Beulich  <jbeulich@suse.com>
 834
 835         * i386-dis.c (XMVexScalarI4): Define.
 836         (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
 837         VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
 838         VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
 839         (vex_len_table): Move scalar FMA4 entries ...
 840         (prefix_table): ... here.
 841         (OP_REG_VexI4): Handle scalar_mode.
 842         * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
 843         * i386-tbl.h: Re-generate.
 844
 845 2020-07-08  Jan Beulich  <jbeulich@suse.com>
 846
 847         * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
 848         Vex_2src_2): Delete.
 849         (OP_VexW, VexW): New.
 850         (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
 851         for shifts and rotates by register.
 852
 853 2020-07-08  Jan Beulich  <jbeulich@suse.com>
 854
 855         * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
 856         VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
 857         OP_EX_VexReg): Delete.
 858         (OP_VexI4, VexI4): New.
 859         (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
 860         (prefix_table): ... here.
 861         (print_insn): Drop setting of vex_w_done.
 862
 863 2020-07-08  Jan Beulich  <jbeulich@suse.com>
 864
 865         * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
 866         (prefix_table, vex_len_table): Replace operands for FMA4 insns.
 867         (xop_table): Replace operands of 4-operand insns.
 868         (OP_REG_VexI4): Move VEX.W based operand swaping here.
 869
 870 2020-07-07  Claudiu Zissulescu  <claziss@synopsys.com>
 871
 872         * arc-opc.c (insert_rbd): New function.
 873         (RBD): Define.
 874         (RBDdup): Likewise.
 875         * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
 876         instructions.
 877
 878 2020-07-07  Jan Beulich  <jbeulich@suse.com>
 879
 880         * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
 881         EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
 882         EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
 883         EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
 884         Delete.
 885         (putop): Handle "BW".
 886         * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
 887         0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
 888         and 0F3A3F ...
 889         * i386-dis-evex-prefix.h: ... here.
 890
 891 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 892
 893         * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
 894         (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
 895         VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
 896         VEX_W_0FXOP_09_83): New enumerators.
 897         (xop_table): Reference the above.
 898         (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
 899         (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
 900         VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
 901         (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
 902
 903 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 904
 905         * i386-dis.c (EVEX_W_0F3838_P_1,
 906         EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
 907         EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
 908         EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
 909         EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
 910         EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
 911         (putop): Centralize management of last[]. Delete SAVE_LAST.
 912         * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
 913         0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
 914         0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
 915         * i386-dis-evex-prefix.h: here.
 916
 917 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 918
 919         * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
 920         MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
 921         MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
 922         MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
 923         enumerators.
 924         (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
 925         EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
 926         EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
 927         EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
 928         (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
 929         EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
 930         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
 931         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
 932         these, respectively.
 933         * i386-dis-evex-len.h: Adjust comments.
 934         * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
 935         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
 936         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
 937         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
 938         MOD_EVEX_0F385B_P_2_W_1 table entries.
 939         * i386-dis-evex-w.h: Reference mod_table[] for
 940         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
 941         EVEX_W_0F385B_P_2.
 942
 943 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 944
 945         * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
 946         vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
 947         EXymm.
 948         (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
 949         Likewise. Mark 256-bit entries invalid.
 950
 951 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 952
 953         * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
 954         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
 955         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
 956         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
 957         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
 958         PREFIX_EVEX_0F382B): Delete.
 959         (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
 960         EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
 961         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
 962         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
 963         EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
 964         to ...
 965         (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
 966         EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
 967         EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
 968         EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
 969         respectively.
 970         * i386-dis-evex.h (evex_table): Reference VEX_W table entries
 971         for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
 972         0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
 973         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
 974         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
 975         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
 976         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
 977         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
 978         PREFIX_EVEX_0F382B): Remove table entries.
 979         * i386-dis-evex-w.h: Reference VEX table entries for opcodes
 980         0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
 981         0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
 982
 983 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 984
 985         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
 986         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
 987         enumerators.
 988         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
 989         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
 990         EVEX_LEN_0F3A01_P_2_W_1 table entries.
 991         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
 992         entries.
 993
 994 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 995
 996         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
 997         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
 998         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
 999         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1000         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1001         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1002         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1003         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1004         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1005         entries.
1006
1007 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1008
1009         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1010         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1011         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1012         respectively.
1013         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1014         entries.
1015         * i386-dis-evex.h (evex_table): Reference VEX table entry for
1016         opcode 0F3A1D.
1017         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1018         entry.
1019         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1020
1021 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1022
1023         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1024         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1025         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1026         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1027         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1028         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1029         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1030         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1031         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1032         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1033         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1034         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1035         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1036         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1037         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1038         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1039         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1040         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1041         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1042         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1043         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1044         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1045         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1046         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1047         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1048         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1049         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1050         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1051         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1052         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1053         (prefix_table): Add EXxEVexR to FMA table entries.
1054         (OP_Rounding): Move abort() invocation.
1055         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1056         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1057         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1058         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1059         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1060         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1061         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1062         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1063         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1064         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1065         0F3ACE, 0F3ACF.
1066         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1067         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1068         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1069         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1070         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1071         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1072         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1073         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1074         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1075         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1076         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1077         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1078         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1079         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1080         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1081         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1082         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1083         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1084         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1085         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1086         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1087         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1088         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1089         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1090         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1091         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1092         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1093         Delete table entries.
1094         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1095         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1096         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1097         Likewise.
1098
1099 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1100
1101         * i386-dis.c (EXqScalarS): Delete.
1102         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1103         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1104
1105 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1106
1107         * i386-dis.c (safe-ctype.h): Include.
1108         (EXdScalar, EXqScalar): Delete.
1109         (d_scalar_mode, q_scalar_mode): Delete.
1110         (prefix_table, vex_len_table): Use EXxmm_md in place of
1111         EXdScalar and EXxmm_mq in place of EXqScalar.
1112         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1113         d_scalar_mode and q_scalar_mode.
1114         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1115         (vmovsd): Use EXxmm_mq.
1116
1117 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
1118
1119         PR 26204
1120         * arc-dis.c: Fix spelling mistake.
1121         * po/opcodes.pot: Regenerate.
1122
1123 2020-07-06  Nick Clifton  <nickc@redhat.com>
1124
1125         * po/pt_BR.po: Updated Brazilian Portugugese translation.
1126         * po/uk.po: Updated Ukranian translation.
1127
1128 2020-07-04  Nick Clifton  <nickc@redhat.com>
1129
1130         * configure: Regenerate.
1131         * po/opcodes.pot: Regenerate.
1132
1133 2020-07-04  Nick Clifton  <nickc@redhat.com>
1134
1135         Binutils 2.35 branch created.
1136
1137 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
1138
1139         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1140         * i386-opc.h (VexSwapSources): New.
1141         (i386_opcode_modifier): Add vexswapsources.
1142         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1143         with two source operands swapped.
1144         * i386-tbl.h: Regenerated.
1145
1146 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
1147
1148         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
1149         unprivileged CSR can also be initialized.
1150
1151 2020-06-29  Alan Modra  <amodra@gmail.com>
1152
1153         * arm-dis.c: Use C style comments.
1154         * cr16-opc.c: Likewise.
1155         * ft32-dis.c: Likewise.
1156         * moxie-opc.c: Likewise.
1157         * tic54x-dis.c: Likewise.
1158         * s12z-opc.c: Remove useless comment.
1159         * xgate-dis.c: Likewise.
1160
1161 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
1162
1163         * i386-opc.tbl: Add a blank line.
1164
1165 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
1166
1167         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1168         (VecSIB128): Renamed to ...
1169         (VECSIB128): This.
1170         (VecSIB256): Renamed to ...
1171         (VECSIB256): This.
1172         (VecSIB512): Renamed to ...
1173         (VECSIB512): This.
1174         (VecSIB): Renamed to ...
1175         (SIB): This.
1176         (i386_opcode_modifier): Replace vecsib with sib.
1177         * i386-opc.tbl (VecSIB128): New.
1178         (VecSIB256): Likewise.
1179         (VecSIB512): Likewise.
1180         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1181         and VecSIB512, respectively.
1182
1183 2020-06-26  Jan Beulich  <jbeulich@suse.com>
1184
1185         * i386-dis.c: Adjust description of I macro.
1186         (x86_64_table): Drop use of I.
1187         (float_mem): Replace use of I.
1188         (putop): Remove handling of I. Adjust setting/clearing of "alt".
1189
1190 2020-06-26  Jan Beulich  <jbeulich@suse.com>
1191
1192         * i386-dis.c: (print_insn): Avoid straight assignment to
1193         priv.orig_sizeflag when processing -M sub-options.
1194
1195 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1196
1197         * i386-dis.c: Adjust description of J macro.
1198         (dis386, x86_64_table, mod_table): Replace J.
1199         (putop): Remove handling of J.
1200
1201 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1202
1203         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1204
1205 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1206
1207         * i386-dis.c: Adjust description of "LQ" macro.
1208         (dis386_twobyte): Use LQ for sysret.
1209         (putop): Adjust handling of LQ.
1210
1211 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
1212
1213         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1214         * riscv-dis.c: Include elfxx-riscv.h.
1215
1216 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
1217
1218         * i386-dis.c (prefix_table): Revert the last vmgexit change.
1219
1220 2020-06-17  Lili Cui  <lili.cui@intel.com>
1221
1222         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1223
1224 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
1225
1226         PR gas/26115
1227         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1228         * i386-opc.tbl: Likewise.
1229         * i386-tbl.h: Regenerated.
1230
1231 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
1232
1233         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1234
1235 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
1236
1237         * aarch64-opc.c (SYSREG): New macro for describing system registers.
1238         (SR_CORE): Likewise.
1239         (SR_FEAT): Likewise.
1240         (SR_RNG): Likewise.
1241         (SR_V8_1): Likewise.
1242         (SR_V8_2): Likewise.
1243         (SR_V8_3): Likewise.
1244         (SR_V8_4): Likewise.
1245         (SR_PAN): Likewise.
1246         (SR_RAS): Likewise.
1247         (SR_SSBS): Likewise.
1248         (SR_SVE): Likewise.
1249         (SR_ID_PFR2): Likewise.
1250         (SR_PROFILE): Likewise.
1251         (SR_MEMTAG): Likewise.
1252         (SR_SCXTNUM): Likewise.
1253         (aarch64_sys_regs): Refactor to store feature information in the table.
1254         (aarch64_sys_reg_supported_p): Collapse logic for system registers
1255         that now describe their own features.
1256         (aarch64_pstatefield_supported_p): Likewise.
1257
1258 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
1259
1260         * i386-dis.c (prefix_table): Fix a typo in comments.
1261
1262 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1263
1264         * i386-dis.c (rex_ignored): Delete.
1265         (ckprefix): Drop rex_ignored initialization.
1266         (get_valid_dis386): Drop setting of rex_ignored.
1267         (print_insn): Drop checking of rex_ignored. Don't record data
1268         size prefix as used with VEX-and-alike encodings.
1269
1270 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1271
1272         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1273         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1274         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1275         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1276         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1277         VEX_0F12, and VEX_0F16.
1278         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1279         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1280         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1281         from movlps and movhlps. New MOD_0F12_PREFIX_2,
1282         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1283         MOD_VEX_0F16_PREFIX_2 entries.
1284
1285 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1286
1287         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1288         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1289         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1290         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1291         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1292         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1293         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1294         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1295         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1296         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1297         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1298         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1299         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1300         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1301         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1302         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1303         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1304         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1305         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1306         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1307         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1308         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1309         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1310         EVEX_W_0FC6_P_2): Delete.
1311         (print_insn): Add EVEX.W vs embedded prefix consistency check
1312         to prefix validation.
1313         * i386-dis-evex.h (evex_table): Don't further descend for
1314         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1315         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1316         and 0F2B.
1317         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1318         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1319         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1320         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1321         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1322         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1323         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1324         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1325         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1326         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1327         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1328         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1329         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1330         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1331         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1332         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1333         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1334         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1335         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1336         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1337         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1338         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1339         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1340         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1341         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1342         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1343         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1344
1345 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1346
1347         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1348         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1349         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1350         vmovmskpX.
1351         (print_insn): Drop pointless check against bad_opcode. Split
1352         prefix validation into legacy and VEX-and-alike parts.
1353         (putop): Re-work 'X' macro handling.
1354
1355 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1356
1357         * i386-dis.c (MOD_0F51): Rename to ...
1358         (MOD_0F50): ... this.
1359
1360 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
1361
1362         * arm-dis.c (arm_opcodes): Add dfb.
1363         (thumb32_opcodes): Add dfb.
1364
1365 2020-06-08  Jan Beulich  <jbeulich@suse.com>
1366
1367         * i386-opc.h (reg_entry): Const-qualify reg_name field.
1368
1369 2020-06-06  Alan Modra  <amodra@gmail.com>
1370
1371         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1372
1373 2020-06-05  Alan Modra  <amodra@gmail.com>
1374
1375         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
1376         size is large enough.
1377
1378 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
1379
1380         * disassemble.c (disassemble_init_for_target): Set endian_code for
1381         bpf targets.
1382         * bpf-desc.c: Regenerate.
1383         * bpf-opc.c: Likewise.
1384         * bpf-dis.c: Likewise.
1385
1386 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
1387
1388         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1389         (cgen_put_insn_value): Likewise.
1390         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1391         * cgen-dis.in (print_insn): Likewise.
1392         * cgen-ibld.in (insert_1): Likewise.
1393         (insert_1): Likewise.
1394         (insert_insn_normal): Likewise.
1395         (extract_1): Likewise.
1396         * bpf-dis.c: Regenerate.
1397         * bpf-ibld.c: Likewise.
1398         * bpf-ibld.c: Likewise.
1399         * cgen-dis.in: Likewise.
1400         * cgen-ibld.in: Likewise.
1401         * cgen-opc.c: Likewise.
1402         * epiphany-dis.c: Likewise.
1403         * epiphany-ibld.c: Likewise.
1404         * fr30-dis.c: Likewise.
1405         * fr30-ibld.c: Likewise.
1406         * frv-dis.c: Likewise.
1407         * frv-ibld.c: Likewise.
1408         * ip2k-dis.c: Likewise.
1409         * ip2k-ibld.c: Likewise.
1410         * iq2000-dis.c: Likewise.
1411         * iq2000-ibld.c: Likewise.
1412         * lm32-dis.c: Likewise.
1413         * lm32-ibld.c: Likewise.
1414         * m32c-dis.c: Likewise.
1415         * m32c-ibld.c: Likewise.
1416         * m32r-dis.c: Likewise.
1417         * m32r-ibld.c: Likewise.
1418         * mep-dis.c: Likewise.
1419         * mep-ibld.c: Likewise.
1420         * mt-dis.c: Likewise.
1421         * mt-ibld.c: Likewise.
1422         * or1k-dis.c: Likewise.
1423         * or1k-ibld.c: Likewise.
1424         * xc16x-dis.c: Likewise.
1425         * xc16x-ibld.c: Likewise.
1426         * xstormy16-dis.c: Likewise.
1427         * xstormy16-ibld.c: Likewise.
1428
1429 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
1430
1431         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1432         (print_insn_): Handle instruction endian.
1433         * bpf-dis.c: Regenerate.
1434         * bpf-desc.c: Regenerate.
1435         * epiphany-dis.c: Likewise.
1436         * epiphany-desc.c: Likewise.
1437         * fr30-dis.c: Likewise.
1438         * fr30-desc.c: Likewise.
1439         * frv-dis.c: Likewise.
1440         * frv-desc.c: Likewise.
1441         * ip2k-dis.c: Likewise.
1442         * ip2k-desc.c: Likewise.
1443         * iq2000-dis.c: Likewise.
1444         * iq2000-desc.c: Likewise.
1445         * lm32-dis.c: Likewise.
1446         * lm32-desc.c: Likewise.
1447         * m32c-dis.c: Likewise.
1448         * m32c-desc.c: Likewise.
1449         * m32r-dis.c: Likewise.
1450         * m32r-desc.c: Likewise.
1451         * mep-dis.c: Likewise.
1452         * mep-desc.c: Likewise.
1453         * mt-dis.c: Likewise.
1454         * mt-desc.c: Likewise.
1455         * or1k-dis.c: Likewise.
1456         * or1k-desc.c: Likewise.
1457         * xc16x-dis.c: Likewise.
1458         * xc16x-desc.c: Likewise.
1459         * xstormy16-dis.c: Likewise.
1460         * xstormy16-desc.c: Likewise.
1461
1462 2020-06-03  Nick Clifton  <nickc@redhat.com>
1463
1464         * po/sr.po: Updated Serbian translation.
1465
1466 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
1467
1468         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1469         (riscv_get_priv_spec_class): Likewise.
1470
1471 2020-06-01  Alan Modra  <amodra@gmail.com>
1472
1473         * bpf-desc.c: Regenerate.
1474
1475 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
1476             David Faust <david.faust@oracle.com>
1477
1478         * bpf-desc.c: Regenerate.
1479         * bpf-opc.h: Likewise.
1480         * bpf-opc.c: Likewise.
1481         * bpf-dis.c: Likewise.
1482
1483 2020-05-28  Alan Modra  <amodra@gmail.com>
1484
1485         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1486         values.
1487
1488 2020-05-28  Alan Modra  <amodra@gmail.com>
1489
1490         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1491         immediates.
1492         (print_insn_ns32k): Revert last change.
1493
1494 2020-05-28  Nick Clifton  <nickc@redhat.com>
1495
1496         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1497         static.
1498
1499 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
1500
1501         Fix extraction of signed constants in nios2 disassembler (again).
1502
1503         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1504         extractions of signed fields.
1505
1506 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
1507
1508         * s390-opc.txt: Relocate vector load/store instructions with
1509         additional alignment parameter and change architecture level
1510         constraint from z14 to z13.
1511
1512 2020-05-21  Alan Modra  <amodra@gmail.com>
1513
1514         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1515         * sparc-dis.c: Likewise.
1516         * tic4x-dis.c: Likewise.
1517         * xtensa-dis.c: Likewise.
1518         * bpf-desc.c: Regenerate.
1519         * epiphany-desc.c: Regenerate.
1520         * fr30-desc.c: Regenerate.
1521         * frv-desc.c: Regenerate.
1522         * ip2k-desc.c: Regenerate.
1523         * iq2000-desc.c: Regenerate.
1524         * lm32-desc.c: Regenerate.
1525         * m32c-desc.c: Regenerate.
1526         * m32r-desc.c: Regenerate.
1527         * mep-asm.c: Regenerate.
1528         * mep-desc.c: Regenerate.
1529         * mt-desc.c: Regenerate.
1530         * or1k-desc.c: Regenerate.
1531         * xc16x-desc.c: Regenerate.
1532         * xstormy16-desc.c: Regenerate.
1533
1534 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
1535
1536         * riscv-opc.c (riscv_ext_version_table): The table used to store
1537         all information about the supported spec and the corresponding ISA
1538         versions.  Currently, only Zicsr is supported to verify the
1539         correctness of Z sub extension settings.  Others will be supported
1540         in the future patches.
1541         (struct isa_spec_t, isa_specs): List for all supported ISA spec
1542         classes and the corresponding strings.
1543         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
1544         spec class by giving a ISA spec string.
1545         * riscv-opc.c (struct priv_spec_t): New structure.
1546         (struct priv_spec_t priv_specs): List for all supported privilege spec
1547         classes and the corresponding strings.
1548         (riscv_get_priv_spec_class): New function.  Get the corresponding
1549         privilege spec class by giving a spec string.
1550         (riscv_get_priv_spec_name): New function.  Get the corresponding
1551         privilege spec string by giving a CSR version class.
1552         * riscv-dis.c: Updated since DECLARE_CSR is changed.
1553         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1554         according to the chosen version.  Build a hash table riscv_csr_hash to
1555         store the valid CSR for the chosen pirv verison.  Dump the direct
1556         CSR address rather than it's name if it is invalid.
1557         (parse_riscv_dis_option_without_args): New function.  Parse the options
1558         without arguments.
1559         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1560         parse the options without arguments first, and then handle the options
1561         with arguments.  Add the new option -Mpriv-spec, which has argument.
1562         * riscv-dis.c (print_riscv_disassembler_options): Add description
1563         about the new OBJDUMP option.
1564
1565 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
1566
1567         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1568         WC values on POWER10 sync, dcbf  and wait instructions.
1569         (insert_pl, extract_pl): New functions.
1570         (L2OPT, LS, WC): Use insert_ls and extract_ls.
1571         (LS3): New , 3-bit L for sync.
1572         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1573         (SC2, PL): New, 2-bit SC and PL for sync and wait.
1574         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1575         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1576         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1577         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1578         <wait>: Enable PL operand on POWER10.
1579         <dcbf>: Enable L3OPT operand on POWER10.
1580         <sync>: Enable SC2 operand on POWER10.
1581
1582 2020-05-19  Stafford Horne  <shorne@gmail.com>
1583
1584         PR 25184
1585         * or1k-asm.c: Regenerate.
1586         * or1k-desc.c: Regenerate.
1587         * or1k-desc.h: Regenerate.
1588         * or1k-dis.c: Regenerate.
1589         * or1k-ibld.c: Regenerate.
1590         * or1k-opc.c: Regenerate.
1591         * or1k-opc.h: Regenerate.
1592         * or1k-opinst.c: Regenerate.
1593
1594 2020-05-11  Alan Modra  <amodra@gmail.com>
1595
1596         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1597         xsmaxcqp, xsmincqp.
1598
1599 2020-05-11  Alan Modra  <amodra@gmail.com>
1600
1601         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1602         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1603
1604 2020-05-11  Alan Modra  <amodra@gmail.com>
1605
1606         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1607
1608 2020-05-11  Alan Modra  <amodra@gmail.com>
1609
1610         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1611         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1612
1613 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
1614
1615         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1616         mnemonics.
1617
1618 2020-05-11  Alan Modra  <amodra@gmail.com>
1619
1620         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1621         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1622         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1623         (prefix_opcodes): Add xxeval.
1624
1625 2020-05-11  Alan Modra  <amodra@gmail.com>
1626
1627         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1628         xxgenpcvwm, xxgenpcvdm.
1629
1630 2020-05-11  Alan Modra  <amodra@gmail.com>
1631
1632         * ppc-opc.c (MP, VXVAM_MASK): Define.
1633         (VXVAPS_MASK): Use VXVA_MASK.
1634         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1635         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1636         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1637         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1638
1639 2020-05-11  Alan Modra  <amodra@gmail.com>
1640             Peter Bergner  <bergner@linux.ibm.com>
1641
1642         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1643         New functions.
1644         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1645         YMSK2, XA6a, XA6ap, XB6a entries.
1646         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1647         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1648         (PPCVSX4): Define.
1649         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1650         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1651         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1652         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1653         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1654         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1655         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1656         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1657         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1658         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1659         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1660         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1661         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1662         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1663
1664 2020-05-11  Alan Modra  <amodra@gmail.com>
1665
1666         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1667         (insert_xts, extract_xts): New functions.
1668         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1669         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1670         (VXRC_MASK, VXSH_MASK): Define.
1671         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1672         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1673         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1674         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1675         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1676         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1677         xxblendvh, xxblendvw, xxblendvd, xxpermx.
1678
1679 2020-05-11  Alan Modra  <amodra@gmail.com>
1680
1681         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1682         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1683         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1684         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1685         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1686
1687 2020-05-11  Alan Modra  <amodra@gmail.com>
1688
1689         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1690         (XTP, DQXP, DQXP_MASK): Define.
1691         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1692         (prefix_opcodes): Add plxvp and pstxvp.
1693
1694 2020-05-11  Alan Modra  <amodra@gmail.com>
1695
1696         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1697         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1698         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1699
1700 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
1701
1702         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1703
1704 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
1705
1706         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1707         (L1OPT): Define.
1708         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1709
1710 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
1711
1712         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1713
1714 2020-05-11  Alan Modra  <amodra@gmail.com>
1715
1716         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1717
1718 2020-05-11  Alan Modra  <amodra@gmail.com>
1719
1720         * ppc-dis.c (ppc_opts): Add "power10" entry.
1721         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1722         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
1723
1724 2020-05-11  Nick Clifton  <nickc@redhat.com>
1725
1726         * po/fr.po: Updated French translation.
1727
1728 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
1729
1730         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1731         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1732         (operand_general_constraint_met_p): validate
1733         AARCH64_OPND_UNDEFINED.
1734         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1735         for FLD_imm16_2.
1736         * aarch64-asm-2.c: Regenerated.
1737         * aarch64-dis-2.c: Regenerated.
1738         * aarch64-opc-2.c: Regenerated.
1739
1740 2020-04-29  Nick Clifton  <nickc@redhat.com>
1741
1742         PR 22699
1743         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1744         and SETRC insns.
1745
1746 2020-04-29  Nick Clifton  <nickc@redhat.com>
1747
1748         * po/sv.po: Updated Swedish translation.
1749
1750 2020-04-29  Nick Clifton  <nickc@redhat.com>
1751
1752         PR 22699
1753         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
1754         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1755         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1756         IMM0_8U case.
1757
1758 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
1759
1760         PR 25848
1761         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1762         cmpi only on m68020up and cpu32.
1763
1764 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
1765
1766         * aarch64-asm.c (aarch64_ins_none): New.
1767         * aarch64-asm.h (ins_none): New declaration.
1768         * aarch64-dis.c (aarch64_ext_none): New.
1769         * aarch64-dis.h (ext_none): New declaration.
1770         * aarch64-opc.c (aarch64_print_operand): Update case for
1771         AARCH64_OPND_BARRIER_PSB.
1772         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1773         (AARCH64_OPERANDS): Update inserter/extracter for
1774         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1775         * aarch64-asm-2.c: Regenerated.
1776         * aarch64-dis-2.c: Regenerated.
1777         * aarch64-opc-2.c: Regenerated.
1778
1779 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
1780
1781         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1782         (aarch64_feature_ras, RAS): Likewise.
1783         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1784         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1785         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1786         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1787         * aarch64-asm-2.c: Regenerated.
1788         * aarch64-dis-2.c: Regenerated.
1789         * aarch64-opc-2.c: Regenerated.
1790
1791 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
1792
1793         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1794         (print_insn_neon): Support disassembly of conditional
1795         instructions.
1796
1797 2020-02-16  David Faust  <david.faust@oracle.com>
1798
1799         * bpf-desc.c: Regenerate.
1800         * bpf-desc.h: Likewise.
1801         * bpf-opc.c: Regenerate.
1802         * bpf-opc.h: Likewise.
1803
1804 2020-04-07  Lili Cui  <lili.cui@intel.com>
1805
1806         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1807         (prefix_table): New instructions (see prefixes above).
1808         (rm_table): Likewise
1809         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1810         CPU_ANY_TSXLDTRK_FLAGS.
1811         (cpu_flags): Add CpuTSXLDTRK.
1812         * i386-opc.h (enum): Add CpuTSXLDTRK.
1813         (i386_cpu_flags): Add cputsxldtrk.
1814         * i386-opc.tbl: Add XSUSPLDTRK insns.
1815         * i386-init.h: Regenerate.
1816         * i386-tbl.h: Likewise.
1817
1818 2020-04-02  Lili Cui  <lili.cui@intel.com>
1819
1820         * i386-dis.c (prefix_table): New instructions serialize.
1821         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1822         CPU_ANY_SERIALIZE_FLAGS.
1823         (cpu_flags): Add CpuSERIALIZE.
1824         * i386-opc.h (enum): Add CpuSERIALIZE.
1825         (i386_cpu_flags): Add cpuserialize.
1826         * i386-opc.tbl: Add SERIALIZE insns.
1827         * i386-init.h: Regenerate.
1828         * i386-tbl.h: Likewise.
1829
1830 2020-03-26  Alan Modra  <amodra@gmail.com>
1831
1832         * disassemble.h (opcodes_assert): Declare.
1833         (OPCODES_ASSERT): Define.
1834         * disassemble.c: Don't include assert.h.  Include opintl.h.
1835         (opcodes_assert): New function.
1836         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1837         (bfd_h8_disassemble): Reduce size of data array.  Correctly
1838         calculate maxlen.  Omit insn decoding when insn length exceeds
1839         maxlen.  Exit from nibble loop when looking for E, before
1840         accessing next data byte.  Move processing of E outside loop.
1841         Replace tests of maxlen in loop with assertions.
1842
1843 2020-03-26  Alan Modra  <amodra@gmail.com>
1844
1845         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
1846
1847 2020-03-25  Alan Modra  <amodra@gmail.com>
1848
1849         * z80-dis.c (suffix): Init mybuf.
1850
1851 2020-03-22  Alan Modra  <amodra@gmail.com>
1852
1853         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1854         successflly read from section.
1855
1856 2020-03-22  Alan Modra  <amodra@gmail.com>
1857
1858         * arc-dis.c (find_format): Use ISO C string concatenation rather
1859         than line continuation within a string.  Don't access needs_limm
1860         before testing opcode != NULL.
1861
1862 2020-03-22  Alan Modra  <amodra@gmail.com>
1863
1864         * ns32k-dis.c (print_insn_arg): Update comment.
1865         (print_insn_ns32k): Reduce size of index_offset array, and
1866         initialize, passing -1 to print_insn_arg for args that are not
1867         an index.  Don't exit arg loop early.  Abort on bad arg number.
1868
1869 2020-03-22  Alan Modra  <amodra@gmail.com>
1870
1871         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1872         * s12z-opc.c: Formatting.
1873         (operands_f): Return an int.
1874         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1875         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1876         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1877         (exg_sex_discrim): Likewise.
1878         (create_immediate_operand, create_bitfield_operand),
1879         (create_register_operand_with_size, create_register_all_operand),
1880         (create_register_all16_operand, create_simple_memory_operand),
1881         (create_memory_operand, create_memory_auto_operand): Don't
1882         segfault on malloc failure.
1883         (z_ext24_decode): Return an int status, negative on fail, zero
1884         on success.
1885         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1886         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1887         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1888         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1889         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1890         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1891         (loop_primitive_decode, shift_decode, psh_pul_decode),
1892         (bit_field_decode): Similarly.
1893         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
1894         to return value, update callers.
1895         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1896         Don't segfault on NULL operand.
1897         (decode_operation): Return OP_INVALID on first fail.
1898         (decode_s12z): Check all reads, returning -1 on fail.
1899
1900 2020-03-20  Alan Modra  <amodra@gmail.com>
1901
1902         * metag-dis.c (print_insn_metag): Don't ignore status from
1903         read_memory_func.
1904
1905 2020-03-20  Alan Modra  <amodra@gmail.com>
1906
1907         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1908         Initialize parts of buffer not written when handling a possible
1909         2-byte insn at end of section.  Don't attempt decoding of such
1910         an insn by the 4-byte machinery.
1911
1912 2020-03-20  Alan Modra  <amodra@gmail.com>
1913
1914         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1915         partially filled buffer.  Prevent lookup of 4-byte insns when
1916         only VLE 2-byte insns are possible due to section size.  Print
1917         ".word" rather than ".long" for 2-byte leftovers.
1918
1919 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
1920
1921         PR 25641
1922         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1923
1924 2020-03-13  Jan Beulich  <jbeulich@suse.com>
1925
1926         * i386-dis.c (X86_64_0D): Rename to ...
1927         (X86_64_0E): ... this.
1928
1929 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1930
1931         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1932         * Makefile.in: Regenerated.
1933
1934 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1935
1936         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1937         3-operand pseudos.
1938         * i386-tbl.h: Re-generate.
1939
1940 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1941
1942         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1943         vprot*, vpsha*, and vpshl*.
1944         * i386-tbl.h: Re-generate.
1945
1946 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1947
1948         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1949         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1950         * i386-tbl.h: Re-generate.
1951
1952 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1953
1954         * i386-gen.c (set_bitfield): Ignore zero-length field names.
1955         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1956         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1957         * i386-tbl.h: Re-generate.
1958
1959 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1960
1961         * i386-gen.c (struct template_arg, struct template_instance,
1962         struct template_param, struct template, templates,
1963         parse_template, expand_templates): New.
1964         (process_i386_opcodes): Various local variables moved to
1965         expand_templates. Call parse_template and expand_templates.
1966         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1967         * i386-tbl.h: Re-generate.
1968
1969 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1970
1971         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1972         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1973         register and memory source templates. Replace VexW= by VexW*
1974         where applicable.
1975         * i386-tbl.h: Re-generate.
1976
1977 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1978
1979         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1980         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1981         * i386-tbl.h: Re-generate.
1982
1983 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1984
1985         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1986         * i386-tbl.h: Re-generate.
1987
1988 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1989
1990         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1991         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1992         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1993         VexW0 on SSE2AVX variants.
1994         (vmovq): Drop NoRex64 from XMM/XMM variants.
1995         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1996         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1997         applicable use VexW0.
1998         * i386-tbl.h: Re-generate.
1999
2000 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2001
2002         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2003         * i386-opc.h (Rex64): Delete.
2004         (struct i386_opcode_modifier): Remove rex64 field.
2005         * i386-opc.tbl (crc32): Drop Rex64.
2006         Replace Rex64 with Size64 everywhere else.
2007         * i386-tbl.h: Re-generate.
2008
2009 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2010
2011         * i386-dis.c (OP_E_memory): Exclude recording of used address
2012         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2013         addressed memory operands for MPX insns.
2014
2015 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2016
2017         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2018         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2019         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2020         (ptwrite): Split into non-64-bit and 64-bit forms.
2021         * i386-tbl.h: Re-generate.
2022
2023 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2024
2025         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2026         template.
2027         * i386-tbl.h: Re-generate.
2028
2029 2020-03-04  Jan Beulich  <jbeulich@suse.com>
2030
2031         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2032         (prefix_table): Move vmmcall here. Add vmgexit.
2033         (rm_table): Replace vmmcall entry by prefix_table[] escape.
2034         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2035         (cpu_flags): Add CpuSEV_ES entry.
2036         * i386-opc.h (CpuSEV_ES): New.
2037         (union i386_cpu_flags): Add cpusev_es field.
2038         * i386-opc.tbl (vmgexit): New.
2039         * i386-init.h, i386-tbl.h: Re-generate.
2040
2041 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2042
2043         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2044         with MnemonicSize.
2045         * i386-opc.h (IGNORESIZE): New.
2046         (DEFAULTSIZE): Likewise.
2047         (IgnoreSize): Removed.
2048         (DefaultSize): Likewise.
2049         (MnemonicSize): New.
2050         (i386_opcode_modifier): Replace ignoresize/defaultsize with
2051         mnemonicsize.
2052         * i386-opc.tbl (IgnoreSize): New.
2053         (DefaultSize): Likewise.
2054         * i386-tbl.h: Regenerated.
2055
2056 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
2057
2058         PR 25627
2059         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2060         instructions.
2061
2062 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2063
2064         PR gas/25622
2065         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2066         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2067         * i386-tbl.h: Regenerated.
2068
2069 2020-02-26  Alan Modra  <amodra@gmail.com>
2070
2071         * aarch64-asm.c: Indent labels correctly.
2072         * aarch64-dis.c: Likewise.
2073         * aarch64-gen.c: Likewise.
2074         * aarch64-opc.c: Likewise.
2075         * alpha-dis.c: Likewise.
2076         * i386-dis.c: Likewise.
2077         * nds32-asm.c: Likewise.
2078         * nfp-dis.c: Likewise.
2079         * visium-dis.c: Likewise.
2080
2081 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
2082
2083         * arc-regs.h (int_vector_base): Make it available for all ARC
2084         CPUs.
2085
2086 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
2087
2088         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2089         changed.
2090
2091 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
2092
2093         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2094         c.mv/c.li if rs1 is zero.
2095
2096 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
2097
2098         * i386-gen.c (cpu_flag_init): Replace CpuABM with
2099         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
2100         CPU_POPCNT_FLAGS.
2101         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
2102         * i386-opc.h (CpuABM): Removed.
2103         (CpuPOPCNT): New.
2104         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
2105         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2106         popcnt.  Remove CpuABM from lzcnt.
2107         * i386-init.h: Regenerated.
2108         * i386-tbl.h: Likewise.
2109
2110 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2111
2112         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2113         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2114         VexW1 instead of open-coding them.
2115         * i386-tbl.h: Re-generate.
2116
2117 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2118
2119         * i386-opc.tbl (AddrPrefixOpReg): Define.
2120         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2121         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2122         templates. Drop NoRex64.
2123         * i386-tbl.h: Re-generate.
2124
2125 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2126
2127         PR gas/6518
2128         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2129         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2130         into Intel syntax instance (with Unpsecified) and AT&T one
2131         (without).
2132         (vcvtneps2bf16): Likewise, along with folding the two so far
2133         separate ones.
2134         * i386-tbl.h: Re-generate.
2135
2136 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2137
2138         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2139         CPU_ANY_SSE4A_FLAGS.
2140
2141 2020-02-17  Alan Modra  <amodra@gmail.com>
2142
2143         * i386-gen.c (cpu_flag_init): Correct last change.
2144
2145 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2146
2147         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
2148         CPU_ANY_SSE4_FLAGS.
2149
2150 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
2151
2152         * i386-opc.tbl (movsx): Remove Intel syntax comments.
2153         (movzx): Likewise.
2154
2155 2020-02-14  Jan Beulich  <jbeulich@suse.com>
2156
2157         PR gas/25438
2158         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2159         destination for Cpu64-only variant.
2160         (movzx): Fold patterns.
2161         * i386-tbl.h: Re-generate.
2162
2163 2020-02-13  Jan Beulich  <jbeulich@suse.com>
2164
2165         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2166         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2167         CPU_ANY_SSE4_FLAGS entry.
2168         * i386-init.h: Re-generate.
2169
2170 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2171
2172         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2173         with Unspecified, making the present one AT&T syntax only.
2174         * i386-tbl.h: Re-generate.
2175
2176 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2177
2178         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2179         * i386-tbl.h: Re-generate.
2180
2181 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2182
2183         PR gas/24546
2184         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2185         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2186         Amd64 and Intel64 templates.
2187         (call, jmp): Likewise for far indirect variants. Dro
2188         Unspecified.
2189         * i386-tbl.h: Re-generate.
2190
2191 2020-02-11  Jan Beulich  <jbeulich@suse.com>
2192
2193         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2194         * i386-opc.h (ShortForm): Delete.
2195         (struct i386_opcode_modifier): Remove shortform field.
2196         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2197         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2198         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2199         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2200         Drop ShortForm.
2201         * i386-tbl.h: Re-generate.
2202
2203 2020-02-11  Jan Beulich  <jbeulich@suse.com>
2204
2205         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2206         fucompi): Drop ShortForm from operand-less templates.
2207         * i386-tbl.h: Re-generate.
2208
2209 2020-02-11  Alan Modra  <amodra@gmail.com>
2210
2211         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2212         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2213         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2214         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2215         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2216
2217 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
2218
2219         * arm-dis.c (print_insn_cde): Define 'V' parse character.
2220         (cde_opcodes): Add VCX* instructions.
2221
2222 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
2223             Matthew Malcomson  <matthew.malcomson@arm.com>
2224
2225         * arm-dis.c (struct cdeopcode32): New.
2226         (CDE_OPCODE): New macro.
2227         (cde_opcodes): New disassembly table.
2228         (regnames): New option to table.
2229         (cde_coprocs): New global variable.
2230         (print_insn_cde): New
2231         (print_insn_thumb32): Use print_insn_cde.
2232         (parse_arm_disassembler_options): Parse coprocN args.
2233
2234 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
2235
2236         PR gas/25516
2237         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2238         with ISA64.
2239         * i386-opc.h (AMD64): Removed.
2240         (Intel64): Likewose.
2241         (AMD64): New.
2242         (INTEL64): Likewise.
2243         (INTEL64ONLY): Likewise.
2244         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2245         * i386-opc.tbl (Amd64): New.
2246         (Intel64): Likewise.
2247         (Intel64Only): Likewise.
2248         Replace AMD64 with Amd64.  Update sysenter/sysenter with
2249         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
2250         * i386-tbl.h: Regenerated.
2251
2252 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
2253
2254         PR 25469
2255         * z80-dis.c: Add support for GBZ80 opcodes.
2256
2257 2020-02-04  Alan Modra  <amodra@gmail.com>
2258
2259         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2260
2261 2020-02-03  Alan Modra  <amodra@gmail.com>
2262
2263         * m32c-ibld.c: Regenerate.
2264
2265 2020-02-01  Alan Modra  <amodra@gmail.com>
2266
2267         * frv-ibld.c: Regenerate.
2268
2269 2020-01-31  Jan Beulich  <jbeulich@suse.com>
2270
2271         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2272         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2273         (OP_E_memory): Replace xmm_mdq_mode case label by
2274         vex_scalar_w_dq_mode one.
2275         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2276
2277 2020-01-31  Jan Beulich  <jbeulich@suse.com>
2278
2279         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2280         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2281         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2282         (intel_operand_size): Drop vex_w_dq_mode case label.
2283
2284 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
2285
2286         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2287         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2288
2289 2020-01-30  Alan Modra  <amodra@gmail.com>
2290
2291         * m32c-ibld.c: Regenerate.
2292
2293 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
2294
2295         * bpf-opc.c: Regenerate.
2296
2297 2020-01-30  Jan Beulich  <jbeulich@suse.com>
2298
2299         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2300         (dis386): Use them to replace C2/C3 table entries.
2301         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2302         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2303         ones. Use Size64 instead of DefaultSize on Intel64 ones.
2304         * i386-tbl.h: Re-generate.
2305
2306 2020-01-30  Jan Beulich  <jbeulich@suse.com>
2307
2308         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2309         forms.
2310         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2311         DefaultSize.
2312         * i386-tbl.h: Re-generate.
2313
2314 2020-01-30  Alan Modra  <amodra@gmail.com>
2315
2316         * tic4x-dis.c (tic4x_dp): Make unsigned.
2317
2318 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
2319             Jan Beulich  <jbeulich@suse.com>
2320
2321         PR binutils/25445
2322         * i386-dis.c (MOVSXD_Fixup): New function.
2323         (movsxd_mode): New enum.
2324         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2325         (intel_operand_size): Handle movsxd_mode.
2326         (OP_E_register): Likewise.
2327         (OP_G): Likewise.
2328         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2329         register on movsxd.  Add movsxd with 16-bit destination register
2330         for AMD64 and Intel64 ISAs.
2331         * i386-tbl.h: Regenerated.
2332
2333 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
2334
2335         PR 25403
2336         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2337         * aarch64-asm-2.c: Regenerate
2338         * aarch64-dis-2.c: Likewise.
2339         * aarch64-opc-2.c: Likewise.
2340
2341 2020-01-21  Jan Beulich  <jbeulich@suse.com>
2342
2343         * i386-opc.tbl (sysret): Drop DefaultSize.
2344         * i386-tbl.h: Re-generate.
2345
2346 2020-01-21  Jan Beulich  <jbeulich@suse.com>
2347
2348         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2349         Dword.
2350         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2351         * i386-tbl.h: Re-generate.
2352
2353 2020-01-20  Nick Clifton  <nickc@redhat.com>
2354
2355         * po/de.po: Updated German translation.
2356         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2357         * po/uk.po: Updated Ukranian translation.
2358
2359 2020-01-20  Alan Modra  <amodra@gmail.com>
2360
2361         * hppa-dis.c (fput_const): Remove useless cast.
2362
2363 2020-01-20  Alan Modra  <amodra@gmail.com>
2364
2365         * arm-dis.c (print_insn_arm): Wrap 'T' value.
2366
2367 2020-01-18  Nick Clifton  <nickc@redhat.com>
2368
2369         * configure: Regenerate.
2370         * po/opcodes.pot: Regenerate.
2371
2372 2020-01-18  Nick Clifton  <nickc@redhat.com>
2373
2374         Binutils 2.34 branch created.
2375
2376 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
2377
2378         * opintl.h: Fix spelling error (seperate).
2379
2380 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
2381
2382         * i386-opc.tbl: Add {vex} pseudo prefix.
2383         * i386-tbl.h: Regenerated.
2384
2385 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
2386
2387         PR 25376
2388         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2389         (neon_opcodes): Likewise.
2390         (select_arm_features): Make sure we enable MVE bits when selecting
2391         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
2392         any architecture.
2393
2394 2020-01-16  Jan Beulich  <jbeulich@suse.com>
2395
2396         * i386-opc.tbl: Drop stale comment from XOP section.
2397
2398 2020-01-16  Jan Beulich  <jbeulich@suse.com>
2399
2400         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2401         (extractps): Add VexWIG to SSE2AVX forms.
2402         * i386-tbl.h: Re-generate.
2403
2404 2020-01-16  Jan Beulich  <jbeulich@suse.com>
2405
2406         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2407         Size64 from and use VexW1 on SSE2AVX forms.
2408         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2409         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2410         * i386-tbl.h: Re-generate.
2411
2412 2020-01-15  Alan Modra  <amodra@gmail.com>
2413
2414         * tic4x-dis.c (tic4x_version): Make unsigned long.
2415         (optab, optab_special, registernames): New file scope vars.
2416         (tic4x_print_register): Set up registernames rather than
2417         malloc'd registertable.
2418         (tic4x_disassemble): Delete optable and optable_special.  Use
2419         optab and optab_special instead.  Throw away old optab,
2420         optab_special and registernames when info->mach changes.
2421
2422 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
2423
2424         PR 25377
2425         * z80-dis.c (suffix): Use .db instruction to generate double
2426         prefix.
2427
2428 2020-01-14  Alan Modra  <amodra@gmail.com>
2429
2430         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
2431         values to unsigned before shifting.
2432
2433 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
2434
2435         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2436         flow instructions.
2437         (print_insn_thumb16, print_insn_thumb32): Likewise.
2438         (print_insn): Initialize the insn info.
2439         * i386-dis.c (print_insn): Initialize the insn info fields, and
2440         detect jumps.
2441
2442 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
2443
2444         * arc-opc.c (C_NE): Make it required.
2445
2446 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
2447
2448         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2449         reserved register name.
2450
2451 2020-01-13  Alan Modra  <amodra@gmail.com>
2452
2453         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2454         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2455
2456 2020-01-13  Alan Modra  <amodra@gmail.com>
2457
2458         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
2459         result of wasm_read_leb128 in a uint64_t and check that bits
2460         are not lost when copying to other locals.  Use uint32_t for
2461         most locals.  Use PRId64 when printing int64_t.
2462
2463 2020-01-13  Alan Modra  <amodra@gmail.com>
2464
2465         * score-dis.c: Formatting.
2466         * score7-dis.c: Formatting.
2467
2468 2020-01-13  Alan Modra  <amodra@gmail.com>
2469
2470         * score-dis.c (print_insn_score48): Use unsigned variables for
2471         unsigned values.  Don't left shift negative values.
2472         (print_insn_score32): Likewise.
2473         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2474
2475 2020-01-13  Alan Modra  <amodra@gmail.com>
2476
2477         * tic4x-dis.c (tic4x_print_register): Remove dead code.
2478
2479 2020-01-13  Alan Modra  <amodra@gmail.com>
2480
2481         * fr30-ibld.c: Regenerate.
2482
2483 2020-01-13  Alan Modra  <amodra@gmail.com>
2484
2485         * xgate-dis.c (print_insn): Don't left shift signed value.
2486         (ripBits): Formatting, use 1u.
2487
2488 2020-01-10  Alan Modra  <amodra@gmail.com>
2489
2490         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2491         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
2492
2493 2020-01-10  Alan Modra  <amodra@gmail.com>
2494
2495         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2496         and XRREG value earlier to avoid a shift with negative exponent.
2497         * m10200-dis.c (disassemble): Similarly.
2498
2499 2020-01-09  Nick Clifton  <nickc@redhat.com>
2500
2501         PR 25224
2502         * z80-dis.c (ld_ii_ii): Use correct cast.
2503
2504 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
2505
2506         PR 25224
2507         * z80-dis.c (ld_ii_ii): Use character constant when checking
2508         opcode byte value.
2509
2510 2020-01-09  Jan Beulich  <jbeulich@suse.com>
2511
2512         * i386-dis.c (SEP_Fixup): New.
2513         (SEP): Define.
2514         (dis386_twobyte): Use it for sysenter/sysexit.
2515         (enum x86_64_isa): Change amd64 enumerator to value 1.
2516         (OP_J): Compare isa64 against intel64 instead of amd64.
2517         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2518         forms.
2519         * i386-tbl.h: Re-generate.
2520
2521 2020-01-08  Alan Modra  <amodra@gmail.com>
2522
2523         * z8k-dis.c: Include libiberty.h
2524         (instr_data_s): Make max_fetched unsigned.
2525         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2526         Don't exceed byte_info bounds.
2527         (output_instr): Make num_bytes unsigned.
2528         (unpack_instr): Likewise for nibl_count and loop.
2529         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2530         idx unsigned.
2531         * z8k-opc.h: Regenerate.
2532
2533 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
2534
2535         * arc-tbl.h (llock): Use 'LLOCK' as class.
2536         (llockd): Likewise.
2537         (scond): Use 'SCOND' as class.
2538         (scondd): Likewise.
2539         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2540         (scondd): Likewise.
2541
2542 2020-01-06  Alan Modra  <amodra@gmail.com>
2543
2544         * m32c-ibld.c: Regenerate.
2545
2546 2020-01-06  Alan Modra  <amodra@gmail.com>
2547
2548         PR 25344
2549         * z80-dis.c (suffix): Don't use a local struct buffer copy.
2550         Peek at next byte to prevent recursion on repeated prefix bytes.
2551         Ensure uninitialised "mybuf" is not accessed.
2552         (print_insn_z80): Don't zero n_fetch and n_used here,..
2553         (print_insn_z80_buf): ..do it here instead.
2554
2555 2020-01-04  Alan Modra  <amodra@gmail.com>
2556
2557         * m32r-ibld.c: Regenerate.
2558
2559 2020-01-04  Alan Modra  <amodra@gmail.com>
2560
2561         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2562
2563 2020-01-04  Alan Modra  <amodra@gmail.com>
2564
2565         * crx-dis.c (match_opcode): Avoid shift left of signed value.
2566
2567 2020-01-04  Alan Modra  <amodra@gmail.com>
2568
2569         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2570
2571 2020-01-03  Jan Beulich  <jbeulich@suse.com>
2572
2573         * aarch64-tbl.h (aarch64_opcode_table): Use
2574         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2575
2576 2020-01-03  Jan Beulich  <jbeulich@suse.com>
2577
2578         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2579         forms of SUDOT and USDOT.
2580
2581 2020-01-03  Jan Beulich  <jbeulich@suse.com>
2582
2583         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2584         uzip{1,2}.
2585         * opcodes/aarch64-dis-2.c: Re-generate.
2586
2587 2020-01-03  Jan Beulich  <jbeulich@suse.com>
2588
2589         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2590         FMMLA encoding.
2591         * opcodes/aarch64-dis-2.c: Re-generate.
2592
2593 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
2594
2595         * z80-dis.c: Add support for eZ80 and Z80 instructions.
2596
2597 2020-01-01  Alan Modra  <amodra@gmail.com>
2598
2599         Update year range in copyright notice of all files.
2600
2601 For older changes see ChangeLog-2019
2602 \f
2603 Copyright (C) 2020 Free Software Foundation, Inc.
2604
2605 Copying and distribution of this file, with or without modification,
2606 are permitted in any medium without royalty provided the copyright
2607 notice and this notice are preserved.
2608
2609 Local Variables:
2610 mode: change-log
2611 left-margin: 8
2612 fill-column: 74
2613 version-control: never
2614 End: