opcodes/ChangeLog

   1 2014-10-09  Jose E. Marchesi  &lt;jose.marchesi@oracle.com&gt;
   2
   3         * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
   4         `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
   5         Annotate table with HWCAP2 bits.
   6         Add instructions xmontmul, xmontsqr, xmpmul.
   7         (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
   8         r,i,%mwait' and `rd %mwait,r' instructions.
   9         Add rd/wr instructions for accessing the %mcdper ancillary state
  10         register.
  11         (sparc-opcodes): Add sparc5/vis4.0 instructions:
  12         subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
  13         fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
  14         fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
  15         fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
  16         fpsubus16, and faligndatai.
  17         * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
  18         ancillary state register to the table.
  19         (print_insn_sparc): Handle the %mcdper ancillary state register.
  20         (print_insn_sparc): Handle new operand type '}'.
  21
  22 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
  23
  24         * i386-dis.c (MOD_0F20): Removed.
  25         (MOD_0F21): Likewise.
  26         (MOD_0F22): Likewise.
  27         (MOD_0F23): Likewise.
  28         (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
  29         MOD_0F23 with "movZ".
  30         (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
  31         (OP_R): Check mod/rm byte and call OP_E_register.
  32
  33 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
  34
  35         * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
  36         keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
  37         keyword_aridxi): Add audio ISA extension.
  38         (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
  39         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
  40         keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
  41         for nds32-dis.c using.
  42         (build_opcode_syntax): Remove dead code.
  43         (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
  44         parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
  45         parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
  46         operand parser.
  47         * nds32-asm.h: Declare.
  48         * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
  49         decoding by switch.
  50
  51 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
  52             Matthew Fortune  <matthew.fortune@imgtec.com>
  53
  54         * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
  55         mips64r6.
  56         (parse_mips_dis_option): Allow MSA and virtualization support for
  57         mips64r6.
  58         (mips_print_arg_state): Add fields dest_regno and seen_dest.
  59         (mips_seen_register): New function.
  60         (print_insn_arg): Refactored code to use mips_seen_register
  61         function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
  62         OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
  63         the register rather than aborting.
  64         (print_insn_args): Add length argument.  Add code to correctly
  65         calculate the instruction address for pc relative instructions.
  66         (validate_insn_args): New static function.
  67         (print_insn_mips): Prevent jalx disassembling for r6.  Use
  68         validate_insn_args.
  69         (print_insn_micromips): Use validate_insn_args.
  70         all the arguments are valid.
  71         * mips-formats.h (PREV_CHECK): New define.
  72         * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
  73         -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
  74         (RD_pc): New define.
  75         (FS): New define.
  76         (I37): New define.
  77         (I69): New define.
  78         (mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
  79         MIPS R6 instructions from MIPS R2 instructions.
  80
  81 2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
  82
  83         * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
  84         (putop): Handle "%LP".
  85
  86 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
  87
  88         * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
  89         * aarch64-dis-2.c: Update auto-generated file.
  90
  91 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
  92
  93         * aarch64-tbl.h (QL_R4NIL): New qualifiers.
  94         (aarch64_feature_lse): New feature added.
  95         (LSE): New Added.
  96         (aarch64_opcode_table): New LSE instructions added.  Improve
  97         descriptions for ldarb/ldarh/ldar.
  98         (aarch64_opcode_table): Describe PAIRREG.
  99         * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
 100         * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
 101         (aarch64_print_operand): Recognize PAIRREG.
 102         (operand_general_constraint_met_p): Check reg pair constraints for CASP
 103         instructions.
 104         * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
 105         (do_special_decoding): Recognize F_LSE_SZ.
 106         * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
 107
 108 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
 109
 110         * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
 111         (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
 112         "sdbbp", "syscall" and "wait".
 113
 114 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
 115             Maciej W. Rozycki  <macro@codesourcery.com>
 116
 117         * arm-dis.c (print_arm_address): Negate the GPR-relative offset
 118         returned if the U bit is set.
 119
 120 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 121
 122         * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
 123         48-bit "li" encoding.
 124
 125 2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 126
 127         * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
 128         (s390_print_insn_with_opcode, opcode_mask_more_specific): New
 129         static functions, code was moved from...
 130         (print_insn_s390): ...here.
 131         (s390_extract_operand): Adjust comment.  Change type of first
 132         parameter from 'unsigned char *' to 'const bfd_byte *'.
 133         (union operand_value): New.
 134         (s390_extract_operand): Change return type to union operand_value.
 135         Also avoid integer overflow in sign-extension.
 136         (s390_print_insn_with_opcode): Adjust to changed return value from
 137         s390_extract_operand().  Change "%i" printf format to "%u" for
 138         unsigned values.
 139         (init_disasm): Simplify initialization of opc_index[].  This also
 140         fixes an access after the last element of s390_opcodes[].
 141         (print_insn_s390): Simplify the opcode search loop.
 142         Check architecture mask against all searched opcodes, not just the
 143         first matching one.
 144         (s390_print_insn_with_opcode): Drop function pointer dereferences
 145         without effect.
 146         (print_insn_s390): Likewise.
 147         (s390_insn_length): Simplify formula for return value.
 148         (s390_print_insn_with_opcode): Avoid special handling for the
 149         separator before the first operand.  Use new local variable
 150         'flags' in place of 'operand->flags'.
 151
 152 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 153
 154         * bfin-dis.c (struct private): Change int's to bfd_boolean's.
 155         (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 156         decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
 157         Change assignment of 1 to priv->comment to TRUE.
 158         (print_insn_bfin): Change legal to a bfd_boolean.  Change
 159         assignment of 0/1 with priv comment and parallel and legal
 160         to FALSE/TRUE.
 161
 162 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 163
 164         * bfin-dis.c (OUT): Define.
 165         (decode_CC2stat_0): Declare new op_names array.
 166         Replace multiple if statements with a single one.
 167
 168 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 169
 170         * bfin-dis.c (struct private): Add iw0.
 171         (_print_insn_bfin): Assign iw0 to priv.iw0.
 172         (print_insn_bfin): Drop ifetch and use priv.iw0.
 173
 174 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 175
 176         * bfin-dis.c (comment, parallel): Move from global scope ...
 177         (struct private): ... to this new struct.
 178         (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
 179         decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
 180         decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
 181         decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 182         decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 183         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 184         decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
 185         print_insn_bfin): Declare private struct.  Use priv's comment and
 186         parallel members.
 187
 188 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 189
 190         * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
 191         (_print_insn_bfin): Add check for unaligned pc.
 192
 193 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 194
 195         * bfin-dis.c (ifetch): New function.
 196         (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
 197         -1 when it errors.
 198
 199 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 200
 201         * micromips-opc.c (COD): Rename throughout to...
 202         (CM): New define, update to use INSN_COPROC_MOVE.
 203         (LCD): Rename throughout to...
 204         (LC): New define, update to use INSN_LOAD_COPROC.
 205         * mips-opc.c: Likewise.
 206
 207 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 208
 209         * micromips-opc.c (COD, LCD) New macros.
 210         (cfc1, ctc1): Remove FP_S attribute.
 211         (dmfc1, mfc1, mfhc1): Add LCD attribute.
 212         (dmtc1, mtc1, mthc1): Add COD attribute.
 213         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
 214
 215 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 216             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 217             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 218             Sergey Lega  <sergey.s.lega@intel.com>
 219             Anna Tikhonova  <anna.tikhonova@intel.com>
 220             Ilya Tocar  <ilya.tocar@intel.com>
 221             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 222             Ilya Verbin  <ilya.verbin@intel.com>
 223             Kirill Yukhin  <kirill.yukhin@intel.com>
 224             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 225
 226         * i386-dis-evex.h: Updated.
 227         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 228         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
 229         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
 230         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 231         PREFIX_EVEX_0F3A67.
 232         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
 233         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
 234         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 235         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
 236         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
 237         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
 238         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
 239         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
 240         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
 241         (prefix_table): Add entries for new instructions.
 242         (vex_len_table): Ditto.
 243         (vex_w_table): Ditto.
 244         (OP_E_memory): Update xmmq_mode handling.
 245         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
 246         (cpu_flags): Add CpuAVX512DQ.
 247         * i386-init.h: Regenerared.
 248         * i386-opc.h (CpuAVX512DQ): New.
 249         (i386_cpu_flags): Add cpuavx512dq.
 250         * i386-opc.tbl: Add AVX512DQ instructions.
 251         * i386-tbl.h: Regenerate.
 252
 253 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 254             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 255             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 256             Sergey Lega  <sergey.s.lega@intel.com>
 257             Anna Tikhonova  <anna.tikhonova@intel.com>
 258             Ilya Tocar  <ilya.tocar@intel.com>
 259             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 260             Ilya Verbin  <ilya.verbin@intel.com>
 261             Kirill Yukhin  <kirill.yukhin@intel.com>
 262             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 263
 264         * i386-dis-evex.h: Add new instructions (prefixes bellow).
 265         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
 266         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
 267         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
 268         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
 269         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 270         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
 271         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
 272         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 273         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
 274         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 275         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
 276         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
 277         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 278         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
 279         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
 280         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
 281         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
 282         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
 283         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
 284         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
 285         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
 286         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
 287         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
 288         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 289         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
 290         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
 291         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
 292         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
 293         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 294         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
 295         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
 296         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
 297         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 298         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 299         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 300         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 301         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 302         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 303         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 304         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 305         (prefix_table): Add entries for new instructions.
 306         (vex_table) : Ditto.
 307         (vex_len_table): Ditto.
 308         (vex_w_table): Ditto.
 309         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 310         mask_bd_mode handling.
 311         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 312         handling.
 313         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 314         handling.
 315         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 316         (OP_EX): Add dqw_swap_mode handling.
 317         (OP_VEX): Add mask_bd_mode handling.
 318         (OP_Mask): Add mask_bd_mode handling.
 319         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 320         (cpu_flags): Add CpuAVX512BW.
 321         * i386-init.h: Regenerated.
 322         * i386-opc.h (CpuAVX512BW): New.
 323         (i386_cpu_flags): Add cpuavx512bw.
 324         * i386-opc.tbl: Add AVX512BW instructions.
 325         * i386-tbl.h: Regenerate.
 326
 327 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 328             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 329             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 330             Sergey Lega  <sergey.s.lega@intel.com>
 331             Anna Tikhonova  <anna.tikhonova@intel.com>
 332             Ilya Tocar  <ilya.tocar@intel.com>
 333             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 334             Ilya Verbin  <ilya.verbin@intel.com>
 335             Kirill Yukhin  <kirill.yukhin@intel.com>
 336             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 337
 338         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 339         * i386-tbl.h: Regenerate.
 340
 341 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 342             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 343             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 344             Sergey Lega  <sergey.s.lega@intel.com>
 345             Anna Tikhonova  <anna.tikhonova@intel.com>
 346             Ilya Tocar  <ilya.tocar@intel.com>
 347             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 348             Ilya Verbin  <ilya.verbin@intel.com>
 349             Kirill Yukhin  <kirill.yukhin@intel.com>
 350             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 351
 352         * i386-dis.c (intel_operand_size): Support 128/256 length in
 353         vex_vsib_q_w_dq_mode.
 354         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 355         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 356         (cpu_flags): Add CpuAVX512VL.
 357         * i386-init.h: Regenerated.
 358         * i386-opc.h (CpuAVX512VL): New.
 359         (i386_cpu_flags): Add cpuavx512vl.
 360         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 361         * i386-opc.tbl: Add AVX512VL instructions.
 362         * i386-tbl.h: Regenerate.
 363
 364 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 365
 366         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 367         * or1k-opinst.c: Regenerate.
 368
 369 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 370
 371         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 372         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 373
 374 2014-07-04  Alan Modra  <amodra@gmail.com>
 375
 376         * configure.ac: Rename from configure.in.
 377         * Makefile.in: Regenerate.
 378         * config.in: Regenerate.
 379
 380 2014-07-04  Alan Modra  <amodra@gmail.com>
 381
 382         * configure.in: Include bfd/version.m4.
 383         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 384         (BFD_VERSION): Delete.
 385         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 386         * configure: Regenerate.
 387         * Makefile.in: Regenerate.
 388
 389 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 390             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 391             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 392             Soundararajan  <Sounderarajan.D@atmel.com>
 393
 394         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 395         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 396         machine is not avrtiny.
 397
 398 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 399
 400         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 401         constants.
 402
 403 2014-06-12  Alan Modra  <amodra@gmail.com>
 404
 405         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 406         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 407
 408 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 409
 410         * i386-dis.c (fwait_prefix): New.
 411         (ckprefix): Set fwait_prefix.
 412         (print_insn): Properly print prefixes before fwait.
 413
 414 2014-06-07  Alan Modra  <amodra@gmail.com>
 415
 416         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 417
 418 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 419
 420         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 421         bfd's development.sh.
 422         * Makefile.in, configure: Regenerate.
 423
 424 2014-06-03  Nick Clifton  <nickc@redhat.com>
 425
 426         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 427         decide when extended addressing is being used.
 428
 429 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 430
 431         * sparc-opc.c (cas): Disable for LEON.
 432         (casl): Likewise.
 433
 434 2014-05-20  Alan Modra  <amodra@gmail.com>
 435
 436         * m68k-dis.c: Don't include setjmp.h.
 437
 438 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 439
 440         * i386-dis.c (ADDR16_PREFIX): Removed.
 441         (ADDR32_PREFIX): Likewise.
 442         (DATA16_PREFIX): Likewise.
 443         (DATA32_PREFIX): Likewise.
 444         (prefix_name): Updated.
 445         (print_insn): Simplify data and address size prefixes processing.
 446
 447 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 448
 449         * or1k-desc.c: Regenerated.
 450         * or1k-desc.h: Likewise.
 451         * or1k-opc.c: Likewise.
 452         * or1k-opc.h: Likewise.
 453         * or1k-opinst.c: Likewise.
 454
 455 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 456
 457         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 458         (I34): New define.
 459         (I36): New define.
 460         (I66): New define.
 461         (I68): New define.
 462         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 463         mips64r5.
 464         (parse_mips_dis_option): Update MSA and virtualization support to
 465         allow mips64r3 and mips64r5.
 466
 467 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 468
 469         * mips-opc.c (G3): Remove I4.
 470
 471 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 472
 473         PR binutils/16893
 474         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 475         (end_codep): Likewise.
 476         (mandatory_prefix): Likewise.
 477         (active_seg_prefix): Likewise.
 478         (ckprefix): Set active_seg_prefix to the active segment register
 479         prefix.
 480         (seg_prefix): Removed.
 481         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 482         for prefix index.  Ignore the index if it is invalid and the
 483         mandatory prefix isn't required.
 484         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 485         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 486         in used_prefixes here.  Don't print unused prefixes.  Check
 487         active_seg_prefix for the active segment register prefix.
 488         Restore the DFLAG bit in sizeflag if the data size prefix is
 489         unused.  Check the unused mandatory PREFIX_XXX prefixes
 490         (append_seg): Only print the segment register which gets used.
 491         (OP_E_memory): Check active_seg_prefix for the segment register
 492         prefix.
 493         (OP_OFF): Likewise.
 494         (OP_OFF64): Likewise.
 495         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 496
 497 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 498
 499         PR binutils/16886
 500         * config.in: Regenerated.
 501         * configure: Likewise.
 502         * configure.in: Check if sigsetjmp is available.
 503         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 504         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 505         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 506         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 507         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 508         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 509         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 510         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 511         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 512         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 513         (OPCODES_SIGSETJMP): Likewise.
 514         (OPCODES_SIGLONGJMP): Likewise.
 515         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 516         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 517         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 518         * xtensa-dis.c (dis_private): Replace jmp_buf with
 519         OPCODES_SIGJMP_BUF.
 520         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 521         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 522         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 523         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 524         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 525
 526 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 527
 528         PR binutils/16891
 529         * i386-dis.c (print_insn): Handle prefixes before fwait.
 530
 531 2014-04-26  Alan Modra  <amodra@gmail.com>
 532
 533         * po/POTFILES.in: Regenerate.
 534
 535 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 536
 537         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 538         to allow the MIPS XPA ASE.
 539         (parse_mips_dis_option): Process the -Mxpa option.
 540         * mips-opc.c (XPA): New define.
 541         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 542         locations of the ctc0 and cfc0 instructions.
 543
 544 2014-04-22  Christian Svensson  <blue@cmd.nu>
 545
 546         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 547         * configure.in: Likewise.
 548         * disassemble.c: Likewise.
 549         * or1k-asm.c: New file.
 550         * or1k-desc.c: New file.
 551         * or1k-desc.h: New file.
 552         * or1k-dis.c: New file.
 553         * or1k-ibld.c: New file.
 554         * or1k-opc.c: New file.
 555         * or1k-opc.h: New file.
 556         * or1k-opinst.c: New file.
 557         * Makefile.in: Regenerate.
 558         * configure: Regenerate.
 559         * openrisc-asm.c: Delete.
 560         * openrisc-desc.c: Delete.
 561         * openrisc-desc.h: Delete.
 562         * openrisc-dis.c: Delete.
 563         * openrisc-ibld.c: Delete.
 564         * openrisc-opc.c: Delete.
 565         * openrisc-opc.h: Delete.
 566         * or32-dis.c: Delete.
 567         * or32-opc.c: Delete.
 568
 569 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 570
 571         * i386-dis.c (rm_table): Add encls, enclu.
 572         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 573         (cpu_flags): Add CpuSE1.
 574         * i386-opc.h (enum): Add CpuSE1.
 575         (i386_cpu_flags): Add cpuse1.
 576         * i386-opc.tbl: Add encls, enclu.
 577         * i386-init.h: Regenerated.
 578         * i386-tbl.h: Likewise.
 579
 580 2014-04-02  Anthony Green  <green@moxielogic.com>
 581
 582         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 583         instructions, sex.b and sex.s.
 584
 585 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 586
 587         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 588         instructions.
 589
 590 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 591
 592         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 593         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 594         vscatterqps.
 595         * i386-tbl.h: Regenerate.
 596
 597 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 598
 599         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 600         %hstick_enable added.
 601
 602 2014-03-19  Nick Clifton  <nickc@redhat.com>
 603
 604         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 605         field of 3.
 606         (sbwl, ubwl, SCALE): Likewise.
 607         * rx-decode.c: Regenerate.
 608
 609 2014-03-12  Alan Modra  <amodra@gmail.com>
 610
 611         * Makefile.in: Regenerate.
 612
 613 2014-03-05  Alan Modra  <amodra@gmail.com>
 614
 615         Update copyright years.
 616
 617 2014-03-04  Heiher  <r@hev.cc>
 618
 619         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 620
 621 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 622
 623         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 624         so that they come after the Loongson extensions.
 625
 626 2014-03-03  Alan Modra  <amodra@gmail.com>
 627
 628         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 629
 630 2014-02-28  Alan Modra  <amodra@gmail.com>
 631
 632         * msp430-decode.c: Regenerate.
 633
 634 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 635
 636         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 637         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 638
 639 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 640
 641         * aarch64-opc.c (print_register_offset_address): Call
 642         get_int_reg_name to prepare the register name.
 643
 644 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 645
 646         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 647         * i386-tbl.h: Regenerate.
 648
 649 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 650
 651         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 652         (cpu_flags): Add CpuPREFETCHWT1.
 653         * i386-init.h: Regenerate.
 654         * i386-opc.h (CpuPREFETCHWT1): New.
 655         (i386_cpu_flags): Add cpuprefetchwt1.
 656         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 657         * i386-tbl.h: Regenerate.
 658
 659 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 660
 661         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 662         to CpuAVX512F.
 663         * i386-tbl.h: Regenerate.
 664
 665 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 666
 667         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 668         (output_opcode_modifier): Likewise.
 669         (output_operand_type): Likewise.
 670         * i386-init.h: Regenerated.
 671         * i386-tbl.h: Likewise.
 672
 673 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 674
 675         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 676         MOD_0FC7_REG_5.
 677         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 678         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 679         (prefix_table): Add clflusopt.
 680         (mod_table): Add xrstors, xsavec, xsaves.
 681         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 682         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 683         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 684         * i386-init.h: Regenerate.
 685         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 686         xsaves64, xsavec, xsavec64.
 687         * i386-tbl.h: Regenerate.
 688
 689 2014-02-10  Alan Modra  <amodra@gmail.com>
 690
 691         * po/POTFILES.in: Regenerate.
 692         * po/opcodes.pot: Regenerate.
 693
 694 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 695             Jan Beulich  <jbeulich@suse.com>
 696
 697         PR binutils/16490
 698         * i386-dis.c (OP_E_memory): Fix shift computation for
 699         vex_vsib_q_w_dq_mode.
 700
 701 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 702             Roland McGrath  <mcgrathr@google.com>
 703
 704         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 705         last_rex_prefix is -1.
 706
 707 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 708
 709         * i386-gen.c (process_copyright): Update copyright year to 2014.
 710
 711 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 712
 713         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 714
 715 For older changes see ChangeLog-2013
 716 \f
 717 Copyright (C) 2014 Free Software Foundation, Inc.
 718
 719 Copying and distribution of this file, with or without modification,
 720 are permitted in any medium without royalty provided the copyright
 721 notice and this notice are preserved.
 722
 723 Local Variables:
 724 mode: change-log
 725 left-margin: 8
 726 fill-column: 74
 727 version-control: never
 728 End: