opcodes/ChangeLog

   1 2017-05-24  Yao Qi  <yao.qi@linaro.org>
   2
   3         * disassemble.c (disassembler): Add arguments a, big and mach.
   4         Use them.
   5
   6 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         * i386-dis.c (NOTRACK_Fixup): New.
   9         (NOTRACK): Likewise.
  10         (NOTRACK_PREFIX): Likewise.
  11         (last_active_prefix): Likewise.
  12         (reg_table): Use NOTRACK on indirect call and jmp.
  13         (ckprefix): Set last_active_prefix.
  14         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
  15         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
  16         * i386-opc.h (NoTrackPrefixOk): New.
  17         (i386_opcode_modifier): Add notrackprefixok.
  18         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
  19         Add notrack.
  20         * i386-tbl.h: Regenerated.
  21
  22 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
  23
  24         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
  25         (X_IMM2): Define.
  26         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
  27         bfd_mach_sparc_v9m8.
  28         (print_insn_sparc): Handle new operand types.
  29         * sparc-opc.c (MASK_M8): Define.
  30         (v6): Add MASK_M8.
  31         (v6notlet): Likewise.
  32         (v7): Likewise.
  33         (v8): Likewise.
  34         (v9): Likewise.
  35         (v9a): Likewise.
  36         (v9b): Likewise.
  37         (v9c): Likewise.
  38         (v9d): Likewise.
  39         (v9e): Likewise.
  40         (v9v): Likewise.
  41         (v9m): Likewise.
  42         (v9andleon): Likewise.
  43         (m8): Define.
  44         (HWS_VM8): Define.
  45         (HWS2_VM8): Likewise.
  46         (sparc_opcode_archs): Add entry for "m8".
  47         (sparc_opcodes): Add OSA2017 and M8 instructions
  48         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
  49         fpx{ll,ra,rl}64x,
  50         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
  51         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
  52         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
  53         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
  54         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
  55         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
  56         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
  57         ASI_CORE_SELECT_COMMIT_NHT.
  58
  59 2017-05-18  Alan Modra  <amodra@gmail.com>
  60
  61         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
  62         * aarch64-dis.c: Likewise.
  63         * aarch64-gen.c: Likewise.
  64         * aarch64-opc.c: Likewise.
  65
  66 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
  67             Matthew Fortune  <matthew.fortune@imgtec.com>
  68
  69         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
  70         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
  71         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
  72         (print_insn_arg) <OP_REG28>: Add handler.
  73         (validate_insn_args) <OP_REG28>: Handle.
  74         (print_mips16_insn_arg): Handle MIPS16 instructions that require
  75         32-bit encoding and 9-bit immediates.
  76         (print_insn_mips16): Handle MIPS16 instructions that require
  77         32-bit encoding and MFC0/MTC0 operand decoding.
  78         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
  79         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
  80         (RD_C0, WR_C0, E2, E2MT): New macros.
  81         (mips16_opcodes): Add entries for MIPS16e2 instructions:
  82         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
  83         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
  84         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
  85         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
  86         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
  87         instructions, "swl", "swr", "sync" and its "sync_acquire",
  88         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
  89         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
  90         regular/extended entries for original MIPS16 ISA revision
  91         instructions whose extended forms are subdecoded in the MIPS16e2
  92         ISA revision: "li", "sll" and "srl".
  93
  94 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
  95
  96         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
  97         reference in CP0 move operand decoding.
  98
  99 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 100
 101         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 102         type to hexadecimal.
 103         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 104
 105 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 106
 107         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 108         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 109         "sync_rmb" and "sync_wmb" as aliases.
 110         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 111         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 112
 113 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 114
 115         * arc-dis.c (parse_option): Update quarkse_em option..
 116         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 117         QUARKSE1.
 118         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 119
 120 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 121
 122         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 123
 124 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 125
 126         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 127         register.
 128
 129 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 130
 131         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 132         and branches and not synthetic data instructions.
 133
 134 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 135
 136         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 137
 138 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 139
 140         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 141         * arc-opc.c (insert_r13el): New function.
 142         (R13_EL): Define.
 143         * arc-tbl.h: Add new enter/leave variants.
 144
 145 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 146
 147         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 148
 149 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 150
 151         * mips-dis.c (print_mips_disassembler_options): Add
 152         `no-aliases'.
 153
 154 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 155
 156         * mips16-opc.c (AL): New macro.
 157         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 158         of "ld" and "lw" as aliases.
 159
 160 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 161
 162         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 163         arguments.
 164
 165 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 166             Alan Modra  <amodra@gmail.com>
 167
 168         * ppc-opc.c (ELEV): Define.
 169         (vle_opcodes): Add se_rfgi and e_sc.
 170         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 171         for E200Z4.
 172
 173 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 174
 175         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 176
 177 2017-04-21  Nick Clifton  <nickc@redhat.com>
 178
 179         PR binutils/21380
 180         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 181         LD3R and LD4R.
 182
 183 2017-04-13  Alan Modra  <amodra@gmail.com>
 184
 185         * epiphany-desc.c: Regenerate.
 186         * fr30-desc.c: Regenerate.
 187         * frv-desc.c: Regenerate.
 188         * ip2k-desc.c: Regenerate.
 189         * iq2000-desc.c: Regenerate.
 190         * lm32-desc.c: Regenerate.
 191         * m32c-desc.c: Regenerate.
 192         * m32r-desc.c: Regenerate.
 193         * mep-desc.c: Regenerate.
 194         * mt-desc.c: Regenerate.
 195         * or1k-desc.c: Regenerate.
 196         * xc16x-desc.c: Regenerate.
 197         * xstormy16-desc.c: Regenerate.
 198
 199 2017-04-11  Alan Modra  <amodra@gmail.com>
 200
 201         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 202         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 203         PPC_OPCODE_TMR for e6500.
 204         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 205         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 206         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 207         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 208         (PPCHTM): Define as PPC_OPCODE_POWER8.
 209         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 210
 211 2017-04-10  Alan Modra  <amodra@gmail.com>
 212
 213         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 214         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 215         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 216         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 217
 218 2017-04-09  Pip Cet  <pipcet@gmail.com>
 219
 220         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 221         appropriate floating-point precision directly.
 222
 223 2017-04-07  Alan Modra  <amodra@gmail.com>
 224
 225         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 226         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 227         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 228         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 229         vector instructions with E6500 not PPCVEC2.
 230
 231 2017-04-06  Pip Cet  <pipcet@gmail.com>
 232
 233         * Makefile.am: Add wasm32-dis.c.
 234         * configure.ac: Add wasm32-dis.c to wasm32 target.
 235         * disassemble.c: Add wasm32 disassembler code.
 236         * wasm32-dis.c: New file.
 237         * Makefile.in: Regenerate.
 238         * configure: Regenerate.
 239         * po/POTFILES.in: Regenerate.
 240         * po/opcodes.pot: Regenerate.
 241
 242 2017-04-05  Pedro Alves  <palves@redhat.com>
 243
 244         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 245         * arm-dis.c (parse_arm_disassembler_options): Constify.
 246         * ppc-dis.c (powerpc_init_dialect): Constify local.
 247         * vax-dis.c (parse_disassembler_options): Constify.
 248
 249 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 250
 251         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 252         RISCV_GP_SYMBOL.
 253
 254 2017-03-30  Pip Cet  <pipcet@gmail.com>
 255
 256         * configure.ac: Add (empty) bfd_wasm32_arch target.
 257         * configure: Regenerate
 258         * po/opcodes.pot: Regenerate.
 259
 260 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 261
 262         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 263         OSA2015.
 264         * opcodes/sparc-opc.c (asi_table): New ASIs.
 265
 266 2017-03-29  Alan Modra  <amodra@gmail.com>
 267
 268         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 269         "raw" option.
 270         (lookup_powerpc): Don't special case -1 dialect.  Handle
 271         PPC_OPCODE_RAW.
 272         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 273         lookup_powerpc call, pass it on second.
 274
 275 2017-03-27  Alan Modra  <amodra@gmail.com>
 276
 277         PR 21303
 278         * ppc-dis.c (struct ppc_mopt): Comment.
 279         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 280
 281 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 282
 283         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 284         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 285         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 286         (insert_nps_misc_imm_offset): New function.
 287         (extract_nps_misc imm_offset): New function.
 288         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 289         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 290
 291 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 292
 293         * s390-mkopc.c (main): Remove vx2 check.
 294         * s390-opc.txt: Remove vx2 instruction flags.
 295
 296 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 297
 298         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 299         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 300         (insert_nps_imm_offset): New function.
 301         (extract_nps_imm_offset): New function.
 302         (insert_nps_imm_entry): New function.
 303         (extract_nps_imm_entry): New function.
 304
 305 2017-03-17  Alan Modra  <amodra@gmail.com>
 306
 307         PR 21248
 308         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 309         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 310         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 311
 312 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 313
 314         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 315         <c.andi>: Likewise.
 316         <c.addiw> Likewise.
 317
 318 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 319
 320         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 321
 322 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 323
 324         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 325         <srl> Likewise.
 326         <srai> Likewise.
 327         <sra> Likewise.
 328
 329 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 330
 331         * i386-gen.c (opcode_modifiers): Replace S with Load.
 332         * i386-opc.h (S): Removed.
 333         (Load): New.
 334         (i386_opcode_modifier): Replace s with load.
 335         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 336         and {evex}.  Replace S with Load.
 337         * i386-tbl.h: Regenerated.
 338
 339 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 340
 341         * i386-opc.tbl: Use CpuCET on rdsspq.
 342         * i386-tbl.h: Regenerated.
 343
 344 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 345
 346         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 347         <vsx>: Do not use PPC_OPCODE_VSX3;
 348
 349 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 350
 351         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 352
 353 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 354
 355         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 356         (MOD_0F1E_PREFIX_1): Likewise.
 357         (MOD_0F38F5_PREFIX_2): Likewise.
 358         (MOD_0F38F6_PREFIX_0): Likewise.
 359         (RM_0F1E_MOD_3_REG_7): Likewise.
 360         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 361         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 362         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 363         (PREFIX_0F1E): Likewise.
 364         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 365         (PREFIX_0F38F5): Likewise.
 366         (dis386_twobyte): Use PREFIX_0F1E.
 367         (reg_table): Add REG_0F1E_MOD_3.
 368         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 369         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 370         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 371         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 372         (three_byte_table): Use PREFIX_0F38F5.
 373         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 374         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 375         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 376         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 377         PREFIX_MOD_3_0F01_REG_5_RM_2.
 378         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 379         (cpu_flags): Add CpuCET.
 380         * i386-opc.h (CpuCET): New enum.
 381         (CpuUnused): Commented out.
 382         (i386_cpu_flags): Add cpucet.
 383         * i386-opc.tbl: Add Intel CET instructions.
 384         * i386-init.h: Regenerated.
 385         * i386-tbl.h: Likewise.
 386
 387 2017-03-06  Alan Modra  <amodra@gmail.com>
 388
 389         PR 21124
 390         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 391         (extract_raq, extract_ras, extract_rbx): New functions.
 392         (powerpc_operands): Use opposite corresponding insert function.
 393         (Q_MASK): Define.
 394         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 395         register restriction.
 396
 397 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 398
 399         * disassemble.c Include "safe-ctype.h".
 400         (disassemble_init_for_target): Handle s390 init.
 401         (remove_whitespace_and_extra_commas): New function.
 402         (disassembler_options_cmp): Likewise.
 403         * arm-dis.c: Include "libiberty.h".
 404         (NUM_ELEM): Delete.
 405         (regnames): Use long disassembler style names.
 406         Add force-thumb and no-force-thumb options.
 407         (NUM_ARM_REGNAMES): Rename from this...
 408         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 409         (get_arm_regname_num_options): Delete.
 410         (set_arm_regname_option): Likewise.
 411         (get_arm_regnames): Likewise.
 412         (parse_disassembler_options): Likewise.
 413         (parse_arm_disassembler_option): Rename from this...
 414         (parse_arm_disassembler_options): ...to this.  Make static.
 415         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 416         (print_insn): Use parse_arm_disassembler_options.
 417         (disassembler_options_arm): New function.
 418         (print_arm_disassembler_options): Handle updated regnames.
 419         * ppc-dis.c: Include "libiberty.h".
 420         (ppc_opts): Add "32" and "64" entries.
 421         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 422         (powerpc_init_dialect): Add break to switch statement.
 423         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 424         (disassembler_options_powerpc): New function.
 425         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 426         Remove printing of "32" and "64".
 427         * s390-dis.c: Include "libiberty.h".
 428         (init_flag): Remove unneeded variable.
 429         (struct s390_options_t): New structure type.
 430         (options): New structure.
 431         (init_disasm): Rename from this...
 432         (disassemble_init_s390): ...to this.  Add initializations for
 433         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 434         (print_insn_s390): Delete call to init_disasm.
 435         (disassembler_options_s390): New function.
 436         (print_s390_disassembler_options): Print using information from
 437         struct 'options'.
 438         * po/opcodes.pot: Regenerate.
 439
 440 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 441
 442         * i386-dis.c (PCMPESTR_Fixup): New.
 443         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 444         (prefix_table): Use PCMPESTR_Fixup.
 445         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 446         PCMPESTR_Fixup.
 447         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 448         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 449         Split 64-bit and non-64-bit variants.
 450         * opcodes/i386-tbl.h: Re-generate.
 451
 452 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 453
 454         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 455         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 456         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 457         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 458         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 459         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 460         (OP_SVE_V_HSD): New macros.
 461         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 462         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 463         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 464         (aarch64_opcode_table): Add new SVE instructions.
 465         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 466         for rotation operands.  Add new SVE operands.
 467         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 468         (ins_sve_quad_index): Likewise.
 469         (ins_imm_rotate): Split into...
 470         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 471         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 472         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 473         functions.
 474         (aarch64_ins_sve_addr_ri_s4): New function.
 475         (aarch64_ins_sve_quad_index): Likewise.
 476         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 477         * aarch64-asm-2.c: Regenerate.
 478         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 479         (ext_sve_quad_index): Likewise.
 480         (ext_imm_rotate): Split into...
 481         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 482         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 483         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 484         functions.
 485         (aarch64_ext_sve_addr_ri_s4): New function.
 486         (aarch64_ext_sve_quad_index): Likewise.
 487         (aarch64_ext_sve_index): Allow quad indices.
 488         (do_misc_decoding): Likewise.
 489         * aarch64-dis-2.c: Regenerate.
 490         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 491         aarch64_field_kinds.
 492         (OPD_F_OD_MASK): Widen by one bit.
 493         (OPD_F_NO_ZR): Bump accordingly.
 494         (get_operand_field_width): New function.
 495         * aarch64-opc.c (fields): Add new SVE fields.
 496         (operand_general_constraint_met_p): Handle new SVE operands.
 497         (aarch64_print_operand): Likewise.
 498         * aarch64-opc-2.c: Regenerate.
 499
 500 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 501
 502         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 503         (aarch64_feature_compnum): ...this.
 504         (SIMD_V8_3): Replace with...
 505         (COMPNUM): ...this.
 506         (CNUM_INSN): New macro.
 507         (aarch64_opcode_table): Use it for the complex number instructions.
 508
 509 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 510
 511         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 512
 513 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 514
 515         Add support for associating SPARC ASIs with an architecture level.
 516         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 517         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 518         decoding of SPARC ASIs.
 519
 520 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 521
 522         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 523         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 524
 525 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 526
 527         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 528         1 (instead of to itself). Correct typo.
 529
 530 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 531
 532         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 533         pseudoinstructions.
 534
 535 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 536
 537         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 538         (aarch64_sys_reg_supported_p): Handle them.
 539
 540 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 541
 542         * arc-opc.c (UIMM6_20R): Define.
 543         (SIMM12_20): Use above.
 544         (SIMM12_20R): Define.
 545         (SIMM3_5_S): Use above.
 546         (UIMM7_A32_11R_S): Define.
 547         (UIMM7_9_S): Use above.
 548         (UIMM3_13R_S): Define.
 549         (SIMM11_A32_7_S): Use above.
 550         (SIMM9_8R): Define.
 551         (UIMM10_A32_8_S): Use above.
 552         (UIMM8_8R_S): Define.
 553         (W6): Use above.
 554         (arc_relax_opcodes): Use all above defines.
 555
 556 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 557
 558         * arc-regs.h: Distinguish some of the registers different on
 559         ARC700 and HS38 cpus.
 560
 561 2017-02-14  Alan Modra  <amodra@gmail.com>
 562
 563         PR 21118
 564         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 565         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 566
 567 2017-02-11  Stafford Horne  <shorne@gmail.com>
 568             Alan Modra  <amodra@gmail.com>
 569
 570         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 571         Use insn_bytes_value and insn_int_value directly instead.  Don't
 572         free allocated memory until function exit.
 573
 574 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 575
 576         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 577
 578 2017-02-03  Nick Clifton  <nickc@redhat.com>
 579
 580         PR 21096
 581         * aarch64-opc.c (print_register_list): Ensure that the register
 582         list index will fir into the tb buffer.
 583         (print_register_offset_address): Likewise.
 584         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 585
 586 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 587
 588         PR 21056
 589         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 590         instructions when the previous fetch packet ends with a 32-bit
 591         instruction.
 592
 593 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 594
 595         * pru-opc.c: Remove vague reference to a future GDB port.
 596
 597 2017-01-20  Nick Clifton  <nickc@redhat.com>
 598
 599         * po/ga.po: Updated Irish translation.
 600
 601 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 602
 603         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 604
 605 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 606
 607         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 608         if FETCH_DATA returns 0.
 609         (m68k_scan_mask): Likewise.
 610         (print_insn_m68k): Update code to handle -1 return value.
 611
 612 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 613
 614         * m68k-dis.c (enum print_insn_arg_error): New.
 615         (NEXTBYTE): Replace -3 with
 616         PRINT_INSN_ARG_MEMORY_ERROR.
 617         (NEXTULONG): Likewise.
 618         (NEXTSINGLE): Likewise.
 619         (NEXTDOUBLE): Likewise.
 620         (NEXTDOUBLE): Likewise.
 621         (NEXTPACKED): Likewise.
 622         (FETCH_ARG): Likewise.
 623         (FETCH_DATA): Update comments.
 624         (print_insn_arg): Update comments. Replace magic numbers with
 625         enum.
 626         (match_insn_m68k): Likewise.
 627
 628 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 629
 630         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 631         * i386-dis-evex.h (evex_table): Updated.
 632         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 633         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 634         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 635         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 636         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 637         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 638         * i386-init.h: Regenerate.
 639         * i386-tbl.h: Ditto.
 640
 641 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 642
 643         * msp430-dis.c (msp430_singleoperand): Return -1 if
 644         msp430dis_opcode_signed returns false.
 645         (msp430_doubleoperand): Likewise.
 646         (msp430_branchinstr): Return -1 if
 647         msp430dis_opcode_unsigned returns false.
 648         (msp430x_calla_instr): Likewise.
 649         (print_insn_msp430): Likewise.
 650
 651 2017-01-05  Nick Clifton  <nickc@redhat.com>
 652
 653         PR 20946
 654         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 655         could not be matched.
 656         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 657         NULL.
 658
 659 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 660
 661         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 662         (aarch64_opcode_table): Use RCPC_INSN.
 663
 664 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 665
 666         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 667         extension.
 668         * riscv-opcodes/all-opcodes: Likewise.
 669
 670 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 671
 672         * riscv-dis.c (print_insn_args): Add fall through comment.
 673
 674 2017-01-03  Nick Clifton  <nickc@redhat.com>
 675
 676         * po/sr.po: New Serbian translation.
 677         * configure.ac (ALL_LINGUAS): Add sr.
 678         * configure: Regenerate.
 679
 680 2017-01-02  Alan Modra  <amodra@gmail.com>
 681
 682         * epiphany-desc.h: Regenerate.
 683         * epiphany-opc.h: Regenerate.
 684         * fr30-desc.h: Regenerate.
 685         * fr30-opc.h: Regenerate.
 686         * frv-desc.h: Regenerate.
 687         * frv-opc.h: Regenerate.
 688         * ip2k-desc.h: Regenerate.
 689         * ip2k-opc.h: Regenerate.
 690         * iq2000-desc.h: Regenerate.
 691         * iq2000-opc.h: Regenerate.
 692         * lm32-desc.h: Regenerate.
 693         * lm32-opc.h: Regenerate.
 694         * m32c-desc.h: Regenerate.
 695         * m32c-opc.h: Regenerate.
 696         * m32r-desc.h: Regenerate.
 697         * m32r-opc.h: Regenerate.
 698         * mep-desc.h: Regenerate.
 699         * mep-opc.h: Regenerate.
 700         * mt-desc.h: Regenerate.
 701         * mt-opc.h: Regenerate.
 702         * or1k-desc.h: Regenerate.
 703         * or1k-opc.h: Regenerate.
 704         * xc16x-desc.h: Regenerate.
 705         * xc16x-opc.h: Regenerate.
 706         * xstormy16-desc.h: Regenerate.
 707         * xstormy16-opc.h: Regenerate.
 708
 709 2017-01-02  Alan Modra  <amodra@gmail.com>
 710
 711         Update year range in copyright notice of all files.
 712
 713 For older changes see ChangeLog-2016
 714 \f
 715 Copyright (C) 2017 Free Software Foundation, Inc.
 716
 717 Copying and distribution of this file, with or without modification,
 718 are permitted in any medium without royalty provided the copyright
 719 notice and this notice are preserved.
 720
 721 Local Variables:
 722 mode: change-log
 723 left-margin: 8
 724 fill-column: 74
 725 version-control: never
 726 End: