b46c861032592c03baf2bf4e96222063c0487b2f
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
1 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
2
3 PR binutils/17898
4 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
5 (PREFIX_MOD_0_0FC7_REG_6): This.
6 (PREFIX_MOD_3_0FC7_REG_6): New.
7 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
8 (prefix_table): Replace PREFIX_0FC7_REG_6 with
9 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
10 PREFIX_MOD_3_0FC7_REG_7.
11 (mod_table): Replace PREFIX_0FC7_REG_6 with
12 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
13 PREFIX_MOD_3_0FC7_REG_7.
14
15 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
16
17 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
18 (PREFIX_MANDATORY_REPNZ): Likewise.
19 (PREFIX_MANDATORY_DATA): Likewise.
20 (PREFIX_MANDATORY_ADDR): Likewise.
21 (PREFIX_MANDATORY_LOCK): Likewise.
22 (PREFIX_MANDATORY): Likewise.
23 (PREFIX_UD_SHIFT): Set to 8
24 (PREFIX_UD_REPZ): Updated.
25 (PREFIX_UD_REPNZ): Likewise.
26 (PREFIX_UD_DATA): Likewise.
27 (PREFIX_UD_ADDR): Likewise.
28 (PREFIX_UD_LOCK): Likewise.
29 (PREFIX_IGNORED_SHIFT): New.
30 (PREFIX_IGNORED_REPZ): Likewise.
31 (PREFIX_IGNORED_REPNZ): Likewise.
32 (PREFIX_IGNORED_DATA): Likewise.
33 (PREFIX_IGNORED_ADDR): Likewise.
34 (PREFIX_IGNORED_LOCK): Likewise.
35 (PREFIX_OPCODE): Likewise.
36 (PREFIX_IGNORED): Likewise.
37 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
38 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
39 (three_byte_table): Likewise.
40 (mod_table): Likewise.
41 (mandatory_prefix): Renamed to ...
42 (prefix_requirement): This.
43 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
44 Update PREFIX_90 entry.
45 (get_valid_dis386): Check prefix_requirement to see if a prefix
46 should be ignored.
47 (print_insn): Replace mandatory_prefix with prefix_requirement.
48
49 2015-04-15 Renlin Li <renlin.li@arm.com>
50
51 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
52 use it for ssat and ssat16.
53 (print_insn_thumb32): Add handle case for 'D' control code.
54
55 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
56 H.J. Lu <hongjiu.lu@intel.com>
57
58 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
59 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
60 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
61 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
62 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
63 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
64 Fill prefix_requirement field.
65 (struct dis386): Add prefix_requirement field.
66 (dis386): Fill prefix_requirement field.
67 (dis386_twobyte): Ditto.
68 (twobyte_has_mandatory_prefix_: Remove.
69 (reg_table): Fill prefix_requirement field.
70 (prefix_table): Ditto.
71 (x86_64_table): Ditto.
72 (three_byte_table): Ditto.
73 (xop_table): Ditto.
74 (vex_table): Ditto.
75 (vex_len_table): Ditto.
76 (vex_w_table): Ditto.
77 (mod_table): Ditto.
78 (bad_opcode): Ditto.
79 (print_insn): Use prefix_requirement.
80 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
81 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
82 (float_reg): Ditto.
83
84 2015-03-30 Mike Frysinger <vapier@gentoo.org>
85
86 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
87
88 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
89
90 * Makefile.in: Regenerated.
91
92 2015-03-25 Anton Blanchard <anton@samba.org>
93
94 * ppc-dis.c (disassemble_init_powerpc): Only initialise
95 powerpc_opcd_indices and vle_opcd_indices once.
96
97 2015-03-25 Anton Blanchard <anton@samba.org>
98
99 * ppc-opc.c (powerpc_opcodes): Add slbfee.
100
101 2015-03-24 Terry Guo <terry.guo@arm.com>
102
103 * arm-dis.c (opcode32): Updated to use new arm feature struct.
104 (opcode16): Likewise.
105 (coprocessor_opcodes): Replace bit with feature struct.
106 (neon_opcodes): Likewise.
107 (arm_opcodes): Likewise.
108 (thumb_opcodes): Likewise.
109 (thumb32_opcodes): Likewise.
110 (print_insn_coprocessor): Likewise.
111 (print_insn_arm): Likewise.
112 (select_arm_features): Follow new feature struct.
113
114 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
115
116 * i386-dis.c (rm_table): Add clzero.
117 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
118 Add CPU_CLZERO_FLAGS.
119 (cpu_flags): Add CpuCLZERO.
120 * i386-opc.h: Add CpuCLZERO.
121 * i386-opc.tbl: Add clzero.
122 * i386-init.h: Re-generated.
123 * i386-tbl.h: Re-generated.
124
125 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
126
127 * mips-opc.c (decode_mips_operand): Fix constraint issues
128 with u and y operands.
129
130 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
131
132 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
133
134 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
135
136 * s390-opc.c: Add new IBM z13 instructions.
137 * s390-opc.txt: Likewise.
138
139 2015-03-10 Renlin Li <renlin.li@arm.com>
140
141 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
142 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
143 related alias.
144 * aarch64-asm-2.c: Regenerate.
145 * aarch64-dis-2.c: Likewise.
146 * aarch64-opc-2.c: Likewise.
147
148 2015-03-03 Jiong Wang <jiong.wang@arm.com>
149
150 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
151
152 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
153
154 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
155 arch_sh_up.
156 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
157 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
158
159 2015-02-23 Vinay <Vinay.G@kpit.com>
160
161 * rl78-decode.opc (MOV): Added space between two operands for
162 'mov' instruction in index addressing mode.
163 * rl78-decode.c: Regenerate.
164
165 2015-02-19 Pedro Alves <palves@redhat.com>
166
167 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
168
169 2015-02-10 Pedro Alves <palves@redhat.com>
170 Tom Tromey <tromey@redhat.com>
171
172 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
173 microblaze_and, microblaze_xor.
174 * microblaze-opc.h (opcodes): Adjust.
175
176 2015-01-28 James Bowman <james.bowman@ftdichip.com>
177
178 * Makefile.am: Add FT32 files.
179 * configure.ac: Handle FT32.
180 * disassemble.c (disassembler): Call print_insn_ft32.
181 * ft32-dis.c: New file.
182 * ft32-opc.c: New file.
183 * Makefile.in: Regenerate.
184 * configure: Regenerate.
185 * po/POTFILES.in: Regenerate.
186
187 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
188
189 * nds32-asm.c (keyword_sr): Add new system registers.
190
191 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
192
193 * s390-dis.c (s390_extract_operand): Support vector register
194 operands.
195 (s390_print_insn_with_opcode): Support new operands types and add
196 new handling of optional operands.
197 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
198 and include opcode/s390.h instead.
199 (struct op_struct): New field `flags'.
200 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
201 (dumpTable): Dump flags.
202 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
203 string.
204 * s390-opc.c: Add new operands types, instruction formats, and
205 instruction masks.
206 (s390_opformats): Add new formats for .insn.
207 * s390-opc.txt: Add new instructions.
208
209 2015-01-01 Alan Modra <amodra@gmail.com>
210
211 Update year range in copyright notice of all files.
212
213 For older changes see ChangeLog-2014
214 \f
215 Copyright (C) 2015 Free Software Foundation, Inc.
216
217 Copying and distribution of this file, with or without modification,
218 are permitted in any medium without royalty provided the copyright
219 notice and this notice are preserved.
220
221 Local Variables:
222 mode: change-log
223 left-margin: 8
224 fill-column: 74
225 version-control: never
226 End:
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