opcodes/ChangeLog

   1 2017-06-19  Nick Clifton  <nickc@redhat.com>
   2
   3         PR binutils/21614
   4         * score-dis.c (score_opcodes): Add sentinel.
   5
   6 2017-06-16  Alan Modra  <amodra@gmail.com>
   7
   8         * rx-decode.c: Regenerate.
   9
  10 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
  11
  12         PR binutils/21594
  13         * i386-dis.c (OP_E_register): Check valid bnd register.
  14         (OP_G): Likewise.
  15
  16 2017-06-15  Nick Clifton  <nickc@redhat.com>
  17
  18         PR binutils/21595
  19         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
  20         range value.
  21
  22 2017-06-15  Nick Clifton  <nickc@redhat.com>
  23
  24         PR binutils/21588
  25         * rl78-decode.opc (OP_BUF_LEN): Define.
  26         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
  27         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
  28         array.
  29         * rl78-decode.c: Regenerate.
  30
  31 2017-06-15  Nick Clifton  <nickc@redhat.com>
  32
  33         PR binutils/21586
  34         * bfin-dis.c (gregs): Clip index to prevent overflow.
  35         (regs): Likewise.
  36         (regs_lo): Likewise.
  37         (regs_hi): Likewise.
  38
  39 2017-06-14  Nick Clifton  <nickc@redhat.com>
  40
  41         PR binutils/21576
  42         * score7-dis.c (score_opcodes): Add sentinel.
  43
  44 2017-06-14  Yao Qi  <yao.qi@linaro.org>
  45
  46         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
  47         * arm-dis.c: Likewise.
  48         * ia64-dis.c: Likewise.
  49         * mips-dis.c: Likewise.
  50         * spu-dis.c: Likewise.
  51         * disassemble.h (print_insn_aarch64): New declaration, moved from
  52         include/dis-asm.h.
  53         (print_insn_big_arm, print_insn_big_mips): Likewise.
  54         (print_insn_i386, print_insn_ia64): Likewise.
  55         (print_insn_little_arm, print_insn_little_mips): Likewise.
  56
  57 2017-06-14  Nick Clifton  <nickc@redhat.com>
  58
  59         PR binutils/21587
  60         * rx-decode.opc: Include libiberty.h
  61         (GET_SCALE): New macro - validates access to SCALE array.
  62         (GET_PSCALE): New macro - validates access to PSCALE array.
  63         (DIs, SIs, S2Is, rx_disp): Use new macros.
  64         * rx-decode.c: Regenerate.
  65
  66 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  67
  68         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
  69
  70 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
  71
  72         * arc-dis.c (enforced_isa_mask): Declare.
  73         (cpu_types): Likewise.
  74         (parse_cpu_option): New function.
  75         (parse_disassembler_options): Use it.
  76         (print_insn_arc): Use enforced_isa_mask.
  77         (print_arc_disassembler_options): Document new options.
  78
  79 2017-05-24  Yao Qi  <yao.qi@linaro.org>
  80
  81         * alpha-dis.c: Include disassemble.h, don't include
  82         dis-asm.h.
  83         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
  84         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
  85         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
  86         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
  87         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
  88         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
  89         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
  90         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
  91         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
  92         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
  93         * moxie-dis.c, msp430-dis.c, mt-dis.c:
  94         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
  95         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
  96         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
  97         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
  98         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
  99         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 100         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 101         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 102         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 103         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 104         * z80-dis.c, z8k-dis.c: Likewise.
 105         * disassemble.h: New file.
 106
 107 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 108
 109         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 110         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 111
 112 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 113
 114         * disassemble.c (disassembler): Add arguments a, big and mach.
 115         Use them.
 116
 117 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 118
 119         * i386-dis.c (NOTRACK_Fixup): New.
 120         (NOTRACK): Likewise.
 121         (NOTRACK_PREFIX): Likewise.
 122         (last_active_prefix): Likewise.
 123         (reg_table): Use NOTRACK on indirect call and jmp.
 124         (ckprefix): Set last_active_prefix.
 125         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 126         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 127         * i386-opc.h (NoTrackPrefixOk): New.
 128         (i386_opcode_modifier): Add notrackprefixok.
 129         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 130         Add notrack.
 131         * i386-tbl.h: Regenerated.
 132
 133 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 134
 135         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 136         (X_IMM2): Define.
 137         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 138         bfd_mach_sparc_v9m8.
 139         (print_insn_sparc): Handle new operand types.
 140         * sparc-opc.c (MASK_M8): Define.
 141         (v6): Add MASK_M8.
 142         (v6notlet): Likewise.
 143         (v7): Likewise.
 144         (v8): Likewise.
 145         (v9): Likewise.
 146         (v9a): Likewise.
 147         (v9b): Likewise.
 148         (v9c): Likewise.
 149         (v9d): Likewise.
 150         (v9e): Likewise.
 151         (v9v): Likewise.
 152         (v9m): Likewise.
 153         (v9andleon): Likewise.
 154         (m8): Define.
 155         (HWS_VM8): Define.
 156         (HWS2_VM8): Likewise.
 157         (sparc_opcode_archs): Add entry for "m8".
 158         (sparc_opcodes): Add OSA2017 and M8 instructions
 159         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 160         fpx{ll,ra,rl}64x,
 161         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 162         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 163         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 164         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 165         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 166         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 167         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 168         ASI_CORE_SELECT_COMMIT_NHT.
 169
 170 2017-05-18  Alan Modra  <amodra@gmail.com>
 171
 172         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 173         * aarch64-dis.c: Likewise.
 174         * aarch64-gen.c: Likewise.
 175         * aarch64-opc.c: Likewise.
 176
 177 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 178             Matthew Fortune  <matthew.fortune@imgtec.com>
 179
 180         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 181         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 182         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 183         (print_insn_arg) <OP_REG28>: Add handler.
 184         (validate_insn_args) <OP_REG28>: Handle.
 185         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 186         32-bit encoding and 9-bit immediates.
 187         (print_insn_mips16): Handle MIPS16 instructions that require
 188         32-bit encoding and MFC0/MTC0 operand decoding.
 189         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 190         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 191         (RD_C0, WR_C0, E2, E2MT): New macros.
 192         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 193         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 194         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 195         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 196         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 197         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 198         instructions, "swl", "swr", "sync" and its "sync_acquire",
 199         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 200         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 201         regular/extended entries for original MIPS16 ISA revision
 202         instructions whose extended forms are subdecoded in the MIPS16e2
 203         ISA revision: "li", "sll" and "srl".
 204
 205 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 206
 207         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 208         reference in CP0 move operand decoding.
 209
 210 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 211
 212         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 213         type to hexadecimal.
 214         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 215
 216 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 217
 218         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 219         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 220         "sync_rmb" and "sync_wmb" as aliases.
 221         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 222         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 223
 224 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 225
 226         * arc-dis.c (parse_option): Update quarkse_em option..
 227         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 228         QUARKSE1.
 229         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 230
 231 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 232
 233         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 234
 235 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 236
 237         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 238         register.
 239
 240 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 241
 242         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 243         and branches and not synthetic data instructions.
 244
 245 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 246
 247         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 248
 249 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 250
 251         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 252         * arc-opc.c (insert_r13el): New function.
 253         (R13_EL): Define.
 254         * arc-tbl.h: Add new enter/leave variants.
 255
 256 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 257
 258         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 259
 260 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 261
 262         * mips-dis.c (print_mips_disassembler_options): Add
 263         `no-aliases'.
 264
 265 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 266
 267         * mips16-opc.c (AL): New macro.
 268         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 269         of "ld" and "lw" as aliases.
 270
 271 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 272
 273         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 274         arguments.
 275
 276 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 277             Alan Modra  <amodra@gmail.com>
 278
 279         * ppc-opc.c (ELEV): Define.
 280         (vle_opcodes): Add se_rfgi and e_sc.
 281         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 282         for E200Z4.
 283
 284 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 285
 286         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 287
 288 2017-04-21  Nick Clifton  <nickc@redhat.com>
 289
 290         PR binutils/21380
 291         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 292         LD3R and LD4R.
 293
 294 2017-04-13  Alan Modra  <amodra@gmail.com>
 295
 296         * epiphany-desc.c: Regenerate.
 297         * fr30-desc.c: Regenerate.
 298         * frv-desc.c: Regenerate.
 299         * ip2k-desc.c: Regenerate.
 300         * iq2000-desc.c: Regenerate.
 301         * lm32-desc.c: Regenerate.
 302         * m32c-desc.c: Regenerate.
 303         * m32r-desc.c: Regenerate.
 304         * mep-desc.c: Regenerate.
 305         * mt-desc.c: Regenerate.
 306         * or1k-desc.c: Regenerate.
 307         * xc16x-desc.c: Regenerate.
 308         * xstormy16-desc.c: Regenerate.
 309
 310 2017-04-11  Alan Modra  <amodra@gmail.com>
 311
 312         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 313         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 314         PPC_OPCODE_TMR for e6500.
 315         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 316         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 317         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 318         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 319         (PPCHTM): Define as PPC_OPCODE_POWER8.
 320         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 321
 322 2017-04-10  Alan Modra  <amodra@gmail.com>
 323
 324         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 325         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 326         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 327         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 328
 329 2017-04-09  Pip Cet  <pipcet@gmail.com>
 330
 331         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 332         appropriate floating-point precision directly.
 333
 334 2017-04-07  Alan Modra  <amodra@gmail.com>
 335
 336         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 337         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 338         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 339         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 340         vector instructions with E6500 not PPCVEC2.
 341
 342 2017-04-06  Pip Cet  <pipcet@gmail.com>
 343
 344         * Makefile.am: Add wasm32-dis.c.
 345         * configure.ac: Add wasm32-dis.c to wasm32 target.
 346         * disassemble.c: Add wasm32 disassembler code.
 347         * wasm32-dis.c: New file.
 348         * Makefile.in: Regenerate.
 349         * configure: Regenerate.
 350         * po/POTFILES.in: Regenerate.
 351         * po/opcodes.pot: Regenerate.
 352
 353 2017-04-05  Pedro Alves  <palves@redhat.com>
 354
 355         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 356         * arm-dis.c (parse_arm_disassembler_options): Constify.
 357         * ppc-dis.c (powerpc_init_dialect): Constify local.
 358         * vax-dis.c (parse_disassembler_options): Constify.
 359
 360 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 361
 362         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 363         RISCV_GP_SYMBOL.
 364
 365 2017-03-30  Pip Cet  <pipcet@gmail.com>
 366
 367         * configure.ac: Add (empty) bfd_wasm32_arch target.
 368         * configure: Regenerate
 369         * po/opcodes.pot: Regenerate.
 370
 371 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 372
 373         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 374         OSA2015.
 375         * opcodes/sparc-opc.c (asi_table): New ASIs.
 376
 377 2017-03-29  Alan Modra  <amodra@gmail.com>
 378
 379         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 380         "raw" option.
 381         (lookup_powerpc): Don't special case -1 dialect.  Handle
 382         PPC_OPCODE_RAW.
 383         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 384         lookup_powerpc call, pass it on second.
 385
 386 2017-03-27  Alan Modra  <amodra@gmail.com>
 387
 388         PR 21303
 389         * ppc-dis.c (struct ppc_mopt): Comment.
 390         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 391
 392 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 393
 394         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 395         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 396         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 397         (insert_nps_misc_imm_offset): New function.
 398         (extract_nps_misc imm_offset): New function.
 399         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 400         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 401
 402 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 403
 404         * s390-mkopc.c (main): Remove vx2 check.
 405         * s390-opc.txt: Remove vx2 instruction flags.
 406
 407 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 408
 409         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 410         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 411         (insert_nps_imm_offset): New function.
 412         (extract_nps_imm_offset): New function.
 413         (insert_nps_imm_entry): New function.
 414         (extract_nps_imm_entry): New function.
 415
 416 2017-03-17  Alan Modra  <amodra@gmail.com>
 417
 418         PR 21248
 419         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 420         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 421         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 422
 423 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 424
 425         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 426         <c.andi>: Likewise.
 427         <c.addiw> Likewise.
 428
 429 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 430
 431         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 432
 433 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 434
 435         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 436         <srl> Likewise.
 437         <srai> Likewise.
 438         <sra> Likewise.
 439
 440 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 441
 442         * i386-gen.c (opcode_modifiers): Replace S with Load.
 443         * i386-opc.h (S): Removed.
 444         (Load): New.
 445         (i386_opcode_modifier): Replace s with load.
 446         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 447         and {evex}.  Replace S with Load.
 448         * i386-tbl.h: Regenerated.
 449
 450 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         * i386-opc.tbl: Use CpuCET on rdsspq.
 453         * i386-tbl.h: Regenerated.
 454
 455 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 456
 457         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 458         <vsx>: Do not use PPC_OPCODE_VSX3;
 459
 460 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 461
 462         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 463
 464 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 465
 466         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 467         (MOD_0F1E_PREFIX_1): Likewise.
 468         (MOD_0F38F5_PREFIX_2): Likewise.
 469         (MOD_0F38F6_PREFIX_0): Likewise.
 470         (RM_0F1E_MOD_3_REG_7): Likewise.
 471         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 472         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 473         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 474         (PREFIX_0F1E): Likewise.
 475         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 476         (PREFIX_0F38F5): Likewise.
 477         (dis386_twobyte): Use PREFIX_0F1E.
 478         (reg_table): Add REG_0F1E_MOD_3.
 479         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 480         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 481         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 482         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 483         (three_byte_table): Use PREFIX_0F38F5.
 484         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 485         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 486         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 487         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 488         PREFIX_MOD_3_0F01_REG_5_RM_2.
 489         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 490         (cpu_flags): Add CpuCET.
 491         * i386-opc.h (CpuCET): New enum.
 492         (CpuUnused): Commented out.
 493         (i386_cpu_flags): Add cpucet.
 494         * i386-opc.tbl: Add Intel CET instructions.
 495         * i386-init.h: Regenerated.
 496         * i386-tbl.h: Likewise.
 497
 498 2017-03-06  Alan Modra  <amodra@gmail.com>
 499
 500         PR 21124
 501         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 502         (extract_raq, extract_ras, extract_rbx): New functions.
 503         (powerpc_operands): Use opposite corresponding insert function.
 504         (Q_MASK): Define.
 505         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 506         register restriction.
 507
 508 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 509
 510         * disassemble.c Include "safe-ctype.h".
 511         (disassemble_init_for_target): Handle s390 init.
 512         (remove_whitespace_and_extra_commas): New function.
 513         (disassembler_options_cmp): Likewise.
 514         * arm-dis.c: Include "libiberty.h".
 515         (NUM_ELEM): Delete.
 516         (regnames): Use long disassembler style names.
 517         Add force-thumb and no-force-thumb options.
 518         (NUM_ARM_REGNAMES): Rename from this...
 519         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 520         (get_arm_regname_num_options): Delete.
 521         (set_arm_regname_option): Likewise.
 522         (get_arm_regnames): Likewise.
 523         (parse_disassembler_options): Likewise.
 524         (parse_arm_disassembler_option): Rename from this...
 525         (parse_arm_disassembler_options): ...to this.  Make static.
 526         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 527         (print_insn): Use parse_arm_disassembler_options.
 528         (disassembler_options_arm): New function.
 529         (print_arm_disassembler_options): Handle updated regnames.
 530         * ppc-dis.c: Include "libiberty.h".
 531         (ppc_opts): Add "32" and "64" entries.
 532         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 533         (powerpc_init_dialect): Add break to switch statement.
 534         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 535         (disassembler_options_powerpc): New function.
 536         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 537         Remove printing of "32" and "64".
 538         * s390-dis.c: Include "libiberty.h".
 539         (init_flag): Remove unneeded variable.
 540         (struct s390_options_t): New structure type.
 541         (options): New structure.
 542         (init_disasm): Rename from this...
 543         (disassemble_init_s390): ...to this.  Add initializations for
 544         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 545         (print_insn_s390): Delete call to init_disasm.
 546         (disassembler_options_s390): New function.
 547         (print_s390_disassembler_options): Print using information from
 548         struct 'options'.
 549         * po/opcodes.pot: Regenerate.
 550
 551 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 552
 553         * i386-dis.c (PCMPESTR_Fixup): New.
 554         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 555         (prefix_table): Use PCMPESTR_Fixup.
 556         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 557         PCMPESTR_Fixup.
 558         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 559         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 560         Split 64-bit and non-64-bit variants.
 561         * opcodes/i386-tbl.h: Re-generate.
 562
 563 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 564
 565         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 566         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 567         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 568         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 569         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 570         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 571         (OP_SVE_V_HSD): New macros.
 572         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 573         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 574         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 575         (aarch64_opcode_table): Add new SVE instructions.
 576         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 577         for rotation operands.  Add new SVE operands.
 578         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 579         (ins_sve_quad_index): Likewise.
 580         (ins_imm_rotate): Split into...
 581         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 582         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 583         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 584         functions.
 585         (aarch64_ins_sve_addr_ri_s4): New function.
 586         (aarch64_ins_sve_quad_index): Likewise.
 587         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 588         * aarch64-asm-2.c: Regenerate.
 589         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 590         (ext_sve_quad_index): Likewise.
 591         (ext_imm_rotate): Split into...
 592         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 593         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 594         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 595         functions.
 596         (aarch64_ext_sve_addr_ri_s4): New function.
 597         (aarch64_ext_sve_quad_index): Likewise.
 598         (aarch64_ext_sve_index): Allow quad indices.
 599         (do_misc_decoding): Likewise.
 600         * aarch64-dis-2.c: Regenerate.
 601         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 602         aarch64_field_kinds.
 603         (OPD_F_OD_MASK): Widen by one bit.
 604         (OPD_F_NO_ZR): Bump accordingly.
 605         (get_operand_field_width): New function.
 606         * aarch64-opc.c (fields): Add new SVE fields.
 607         (operand_general_constraint_met_p): Handle new SVE operands.
 608         (aarch64_print_operand): Likewise.
 609         * aarch64-opc-2.c: Regenerate.
 610
 611 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 612
 613         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 614         (aarch64_feature_compnum): ...this.
 615         (SIMD_V8_3): Replace with...
 616         (COMPNUM): ...this.
 617         (CNUM_INSN): New macro.
 618         (aarch64_opcode_table): Use it for the complex number instructions.
 619
 620 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 621
 622         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 623
 624 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 625
 626         Add support for associating SPARC ASIs with an architecture level.
 627         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 628         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 629         decoding of SPARC ASIs.
 630
 631 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 632
 633         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 634         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 635
 636 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 637
 638         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 639         1 (instead of to itself). Correct typo.
 640
 641 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 642
 643         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 644         pseudoinstructions.
 645
 646 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 647
 648         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 649         (aarch64_sys_reg_supported_p): Handle them.
 650
 651 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 652
 653         * arc-opc.c (UIMM6_20R): Define.
 654         (SIMM12_20): Use above.
 655         (SIMM12_20R): Define.
 656         (SIMM3_5_S): Use above.
 657         (UIMM7_A32_11R_S): Define.
 658         (UIMM7_9_S): Use above.
 659         (UIMM3_13R_S): Define.
 660         (SIMM11_A32_7_S): Use above.
 661         (SIMM9_8R): Define.
 662         (UIMM10_A32_8_S): Use above.
 663         (UIMM8_8R_S): Define.
 664         (W6): Use above.
 665         (arc_relax_opcodes): Use all above defines.
 666
 667 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 668
 669         * arc-regs.h: Distinguish some of the registers different on
 670         ARC700 and HS38 cpus.
 671
 672 2017-02-14  Alan Modra  <amodra@gmail.com>
 673
 674         PR 21118
 675         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 676         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 677
 678 2017-02-11  Stafford Horne  <shorne@gmail.com>
 679             Alan Modra  <amodra@gmail.com>
 680
 681         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 682         Use insn_bytes_value and insn_int_value directly instead.  Don't
 683         free allocated memory until function exit.
 684
 685 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 686
 687         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 688
 689 2017-02-03  Nick Clifton  <nickc@redhat.com>
 690
 691         PR 21096
 692         * aarch64-opc.c (print_register_list): Ensure that the register
 693         list index will fir into the tb buffer.
 694         (print_register_offset_address): Likewise.
 695         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 696
 697 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 698
 699         PR 21056
 700         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 701         instructions when the previous fetch packet ends with a 32-bit
 702         instruction.
 703
 704 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 705
 706         * pru-opc.c: Remove vague reference to a future GDB port.
 707
 708 2017-01-20  Nick Clifton  <nickc@redhat.com>
 709
 710         * po/ga.po: Updated Irish translation.
 711
 712 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 713
 714         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 715
 716 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 717
 718         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 719         if FETCH_DATA returns 0.
 720         (m68k_scan_mask): Likewise.
 721         (print_insn_m68k): Update code to handle -1 return value.
 722
 723 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 724
 725         * m68k-dis.c (enum print_insn_arg_error): New.
 726         (NEXTBYTE): Replace -3 with
 727         PRINT_INSN_ARG_MEMORY_ERROR.
 728         (NEXTULONG): Likewise.
 729         (NEXTSINGLE): Likewise.
 730         (NEXTDOUBLE): Likewise.
 731         (NEXTDOUBLE): Likewise.
 732         (NEXTPACKED): Likewise.
 733         (FETCH_ARG): Likewise.
 734         (FETCH_DATA): Update comments.
 735         (print_insn_arg): Update comments. Replace magic numbers with
 736         enum.
 737         (match_insn_m68k): Likewise.
 738
 739 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 740
 741         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 742         * i386-dis-evex.h (evex_table): Updated.
 743         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 744         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 745         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 746         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 747         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 748         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 749         * i386-init.h: Regenerate.
 750         * i386-tbl.h: Ditto.
 751
 752 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 753
 754         * msp430-dis.c (msp430_singleoperand): Return -1 if
 755         msp430dis_opcode_signed returns false.
 756         (msp430_doubleoperand): Likewise.
 757         (msp430_branchinstr): Return -1 if
 758         msp430dis_opcode_unsigned returns false.
 759         (msp430x_calla_instr): Likewise.
 760         (print_insn_msp430): Likewise.
 761
 762 2017-01-05  Nick Clifton  <nickc@redhat.com>
 763
 764         PR 20946
 765         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 766         could not be matched.
 767         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 768         NULL.
 769
 770 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 771
 772         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 773         (aarch64_opcode_table): Use RCPC_INSN.
 774
 775 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 776
 777         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 778         extension.
 779         * riscv-opcodes/all-opcodes: Likewise.
 780
 781 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 782
 783         * riscv-dis.c (print_insn_args): Add fall through comment.
 784
 785 2017-01-03  Nick Clifton  <nickc@redhat.com>
 786
 787         * po/sr.po: New Serbian translation.
 788         * configure.ac (ALL_LINGUAS): Add sr.
 789         * configure: Regenerate.
 790
 791 2017-01-02  Alan Modra  <amodra@gmail.com>
 792
 793         * epiphany-desc.h: Regenerate.
 794         * epiphany-opc.h: Regenerate.
 795         * fr30-desc.h: Regenerate.
 796         * fr30-opc.h: Regenerate.
 797         * frv-desc.h: Regenerate.
 798         * frv-opc.h: Regenerate.
 799         * ip2k-desc.h: Regenerate.
 800         * ip2k-opc.h: Regenerate.
 801         * iq2000-desc.h: Regenerate.
 802         * iq2000-opc.h: Regenerate.
 803         * lm32-desc.h: Regenerate.
 804         * lm32-opc.h: Regenerate.
 805         * m32c-desc.h: Regenerate.
 806         * m32c-opc.h: Regenerate.
 807         * m32r-desc.h: Regenerate.
 808         * m32r-opc.h: Regenerate.
 809         * mep-desc.h: Regenerate.
 810         * mep-opc.h: Regenerate.
 811         * mt-desc.h: Regenerate.
 812         * mt-opc.h: Regenerate.
 813         * or1k-desc.h: Regenerate.
 814         * or1k-opc.h: Regenerate.
 815         * xc16x-desc.h: Regenerate.
 816         * xc16x-opc.h: Regenerate.
 817         * xstormy16-desc.h: Regenerate.
 818         * xstormy16-opc.h: Regenerate.
 819
 820 2017-01-02  Alan Modra  <amodra@gmail.com>
 821
 822         Update year range in copyright notice of all files.
 823
 824 For older changes see ChangeLog-2016
 825 \f
 826 Copyright (C) 2017 Free Software Foundation, Inc.
 827
 828 Copying and distribution of this file, with or without modification,
 829 are permitted in any medium without royalty provided the copyright
 830 notice and this notice are preserved.
 831
 832 Local Variables:
 833 mode: change-log
 834 left-margin: 8
 835 fill-column: 74
 836 version-control: never
 837 End: