opcodes/ChangeLog

   1 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
   2
   3         * s12z-opc.h: Add extern "C" bracketing to help
   4         users who wish to use this interface in c++ code.
   5
   6 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
   7
   8         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
   9         specifier.  Add entries for VLDR and VSTR of system registers.
  10         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
  11         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
  12         of %J and %K format specifier.
  13
  14 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  15
  16         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
  17         Add new entries for VSCCLRM instruction.
  18         (print_insn_coprocessor): Handle new %C format control code.
  19
  20 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  21
  22         * arm-dis.c (enum isa): New enum.
  23         (struct sopcode32): New structure.
  24         (coprocessor_opcodes): change type of entries to struct sopcode32 and
  25         set isa field of all current entries to ANY.
  26         (print_insn_coprocessor): Change type of insn to struct sopcode32.
  27         Only match an entry if its isa field allows the current mode.
  28
  29 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  30
  31         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
  32         CLRM.
  33         (print_insn_thumb32): Add logic to print %n CLRM register list.
  34
  35 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  36
  37         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
  38         and %Q patterns.
  39
  40 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  41
  42         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
  43         (print_insn_thumb32): Edit the switch case for %Z.
  44
  45 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  46
  47         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
  48
  49 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  50
  51         * arm-dis.c (thumb32_opcodes): New instruction bfl.
  52
  53 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  54
  55         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
  56
  57 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  58
  59         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
  60         Arm register with r13 and r15 unpredictable.
  61         (thumb32_opcodes): New instructions for bfx and bflx.
  62
  63 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  64
  65         * arm-dis.c (thumb32_opcodes): New instructions for bf.
  66
  67 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  68
  69         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
  70
  71 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
  72
  73         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
  74
  75 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  76
  77         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
  78
  79 2019-04-12  John Darrington <john@darrington.wattle.id.au>
  80
  81         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
  82         "optr". ("operator" is a reserved word in c++).
  83
  84 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
  85
  86         * aarch64-opc.c (aarch64_print_operand): Add case for
  87         AARCH64_OPND_Rt_SP.
  88         (verify_constraints): Likewise.
  89         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
  90         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
  91         to accept Rt|SP as first operand.
  92         (AARCH64_OPERANDS): Add new Rt_SP.
  93         * aarch64-asm-2.c: Regenerated.
  94         * aarch64-dis-2.c: Regenerated.
  95         * aarch64-opc-2.c: Regenerated.
  96
  97 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
  98
  99         * aarch64-asm-2.c: Regenerated.
 100         * aarch64-dis-2.c: Likewise.
 101         * aarch64-opc-2.c: Likewise.
 102         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 103
 104 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 105
 106         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 107
 108 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 109
 110         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 111         * i386-init.h: Regenerated.
 112
 113 2019-04-07  Alan Modra  <amodra@gmail.com>
 114
 115         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 116         op_separator to control printing of spaces, comma and parens
 117         rather than need_comma, need_paren and spaces vars.
 118
 119 2019-04-07  Alan Modra  <amodra@gmail.com>
 120
 121         PR 24421
 122         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 123         (print_insn_neon, print_insn_arm): Likewise.
 124
 125 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 126
 127         * i386-dis-evex.h (evex_table): Updated to support BF16
 128         instructions.
 129         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 130         and EVEX_W_0F3872_P_3.
 131         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 132         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 133         * i386-opc.h (enum): Add CpuAVX512_BF16.
 134         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 135         * i386-opc.tbl: Add AVX512 BF16 instructions.
 136         * i386-init.h: Regenerated.
 137         * i386-tbl.h: Likewise.
 138
 139 2019-04-05  Alan Modra  <amodra@gmail.com>
 140
 141         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 142         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 143         to favour printing of "-" branch hint when using the "y" bit.
 144         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 145
 146 2019-04-05  Alan Modra  <amodra@gmail.com>
 147
 148         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 149         opcode until first operand is output.
 150
 151 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 152
 153         PR gas/24349
 154         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 155         (valid_bo_post_v2): Add support for 'at' branch hints.
 156         (insert_bo): Only error on branch on ctr.
 157         (get_bo_hint_mask): New function.
 158         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 159         for inserting 'at' branch hints.
 160         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 161         for extracting 'at' branch hints.
 162         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 163         (BOE): Delete operand.
 164         (BOM, BOP): New operands.
 165         (RM): Update value.
 166         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 167         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 168         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 169         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 170         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 171         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 172         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 173         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 174         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 175         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 176         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 177         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 178         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 179         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 180         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 181         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 182         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 183         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 184         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 185         bttarl+>: New extended mnemonics.
 186
 187 2019-03-28  Alan Modra  <amodra@gmail.com>
 188
 189         PR 24390
 190         * ppc-opc.c (BTF): Define.
 191         (powerpc_opcodes): Use for mtfsb*.
 192         * ppc-dis.c (print_insn_powerpc): Print fields with both
 193         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 194
 195 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 196
 197         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 198         (mapping_symbol_for_insn): Implement new algorithm.
 199         (print_insn): Remove duplicate code.
 200
 201 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 202
 203         * aarch64-dis.c (print_insn_aarch64):
 204         Implement override.
 205
 206 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 207
 208         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 209         order.
 210
 211 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 212
 213         * aarch64-dis.c (last_stop_offset): New.
 214         (print_insn_aarch64): Use stop_offset.
 215
 216 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 217
 218         PR gas/24359
 219         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 220         CPU_ANY_AVX2_FLAGS.
 221         * i386-init.h: Regenerated.
 222
 223 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 224
 225         PR gas/24348
 226         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 227         vmovdqu16, vmovdqu32 and vmovdqu64.
 228         * i386-tbl.h: Regenerated.
 229
 230 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 231
 232         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 233         from vstrszb, vstrszh, and vstrszf.
 234
 235 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 236
 237         * s390-opc.txt: Add instruction descriptions.
 238
 239 2019-02-08  Jim Wilson  <jimw@sifive.com>
 240
 241         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 242         <bne>: Likewise.
 243
 244 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 245
 246         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 247
 248 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 249
 250         PR binutils/23212
 251         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 252         * aarch64-opc.c (verify_elem_sd): New.
 253         (fields): Add FLD_sz entr.
 254         * aarch64-tbl.h (_SIMD_INSN): New.
 255         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 256         fmulx scalar and vector by element isns.
 257
 258 2019-02-07  Nick Clifton  <nickc@redhat.com>
 259
 260         * po/sv.po: Updated Swedish translation.
 261
 262 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 263
 264         * s390-mkopc.c (main): Accept arch13 as cpu string.
 265         * s390-opc.c: Add new instruction formats and instruction opcode
 266         masks.
 267         * s390-opc.txt: Add new arch13 instructions.
 268
 269 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 270
 271         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 272         (aarch64_opcode): Change encoding for stg, stzg
 273         st2g and st2zg.
 274         * aarch64-asm-2.c: Regenerated.
 275         * aarch64-dis-2.c: Regenerated.
 276         * aarch64-opc-2.c: Regenerated.
 277
 278 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 279
 280         * aarch64-asm-2.c: Regenerated.
 281         * aarch64-dis-2.c: Likewise.
 282         * aarch64-opc-2.c: Likewise.
 283         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 284
 285 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 286             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 287
 288         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 289         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 290         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 291         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 292         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 293         case for ldstgv_indexed.
 294         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 295         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 296         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 297         * aarch64-asm-2.c: Regenerated.
 298         * aarch64-dis-2.c: Regenerated.
 299         * aarch64-opc-2.c: Regenerated.
 300
 301 2019-01-23  Nick Clifton  <nickc@redhat.com>
 302
 303         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 304
 305 2019-01-21  Nick Clifton  <nickc@redhat.com>
 306
 307         * po/de.po: Updated German translation.
 308         * po/uk.po: Updated Ukranian translation.
 309
 310 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 311         * mips-dis.c (mips_arch_choices): Fix typo in
 312         gs464, gs464e and gs264e descriptors.
 313
 314 2019-01-19  Nick Clifton  <nickc@redhat.com>
 315
 316         * configure: Regenerate.
 317         * po/opcodes.pot: Regenerate.
 318
 319 2018-06-24  Nick Clifton  <nickc@redhat.com>
 320
 321         2.32 branch created.
 322
 323 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 324
 325         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 326         if it is null.
 327         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 328         zero.
 329
 330 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 331
 332         * configure: Regenerate.
 333
 334 2019-01-07  Alan Modra  <amodra@gmail.com>
 335
 336         * configure: Regenerate.
 337         * po/POTFILES.in: Regenerate.
 338
 339 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 340
 341         * s12z-opc.c: New file.
 342         * s12z-opc.h: New file.
 343         * s12z-dis.c: Removed all code not directly related to display
 344         of instructions.  Used the interface provided by the new files
 345         instead.
 346         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 347         * Makefile.in: Regenerate.
 348         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 349         * configure: Regenerate.
 350
 351 2019-01-01  Alan Modra  <amodra@gmail.com>
 352
 353         Update year range in copyright notice of all files.
 354
 355 For older changes see ChangeLog-2018
 356 \f
 357 Copyright (C) 2019 Free Software Foundation, Inc.
 358
 359 Copying and distribution of this file, with or without modification,
 360 are permitted in any medium without royalty provided the copyright
 361 notice and this notice are preserved.
 362
 363 Local Variables:
 364 mode: change-log
 365 left-margin: 8
 366 fill-column: 74
 367 version-control: never
 368 End: