opcodes/ChangeLog

   1 2017-11-27  Nick Clifton  <nickc@redhat.com>
   2
   3         * po/zh_CN.po: Updated simplified Chinese translation.
   4
   5 2017-11-24  Jan Beulich  <jbeulich@suse.com>
   6
   7         * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
   8         "df" groups.
   9
  10 2017-11-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  11
  12         * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
  13         * i386-tbl.h: Regenerate.
  14
  15 2017-11-23  Jan Beulich  <jbeulich@suse.com>
  16
  17         * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
  18         the 16-bit addressing case.
  19
  20 2017-11-23  Jan Beulich  <jbeulich@suse.com>
  21
  22         * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
  23         (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
  24         * i386-opc.tbl (ud1, ud2b): Add operands.
  25         (ud0): New.
  26         * i386-tbl.h: Re-generate.
  27
  28 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  29
  30         * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
  31         * i386-tbl.h: Regenerate.
  32
  33 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  34
  35         * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
  36         * i386-tbl.h: Regenerate.
  37
  38 2017-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
  39
  40         *arc-opc (insert_rhv2): Check h-regs range.
  41
  42 2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>
  43
  44         * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
  45         * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
  46
  47 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  48
  49         * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
  50         and AARCH64_FEATURE_F16.
  51
  52 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  53
  54         * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
  55         (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
  56         (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
  57         (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
  58         (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
  59         (ldapur, ldapursw, stlur): New.
  60         * aarch64-dis-2.c: Regenerate.
  61
  62 2017-11-16  Jan Beulich  <jbeulich@suse.com>
  63
  64         (get_valid_dis386): Never flag bad opcode when
  65         vex.register_specifier is beyond 7. Always store all four
  66         bits of it. Move 16-/32-bit override in EVEX handling after
  67         all to be overridden bits have been set.
  68         (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
  69         Use rex to determine GPR register set.
  70         (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
  71         OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
  72
  73 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  74
  75         * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
  76         determine GPR register set.
  77
  78 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  79
  80         * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
  81         (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
  82         (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
  83         pass.
  84         (OP_REG_VexI4): Drop low 4 bits check.
  85
  86 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  87
  88         * i386-reg.tbl (axl): Remove Acc and Byte.
  89         * i386-tbl.h: Re-generate.
  90
  91 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
  94         (vex_len_table): Use VPCOM.
  95
  96 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
  99         (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
 100         * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
 101         vpcmpw): Move up.
 102         (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
 103         vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
 104         vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
 105         vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
 106         vpcmpnltuw): New.
 107         * i386-tbl.h: Re-generate.
 108
 109 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 110
 111         * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
 112         smov, ssca, stos, ssto, xlat): Drop Disp*.
 113         * i386-tbl.h: Re-generate.
 114
 115 2017-11-13  Jan Beulich  <jbeulich@suse.com>
 116
 117         * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
 118         xsaveopt64): Add No_qSuf.
 119         * i386-tbl.h: Re-generate.
 120
 121 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 122
 123         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
 124         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
 125         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
 126         sder32_el2, vncr_el2.
 127         (aarch64_sys_reg_supported_p): Likewise.
 128         (aarch64_pstatefields): Add dit register.
 129         (aarch64_pstatefield_supported_p): Likewise.
 130         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
 131         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
 132         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
 133         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
 134         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
 135         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
 136         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
 137
 138 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 139
 140         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
 141         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
 142         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
 143         (QL_STLW, QL_STLX): New.
 144
 145 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 146
 147         * aarch64-asm.h (ins_addr_offset): New.
 148         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
 149         (aarch64_ins_addr_offset): New.
 150         * aarch64-asm-2.c: Regenerate.
 151         * aarch64-dis.h (ext_addr_offset): New.
 152         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
 153         (aarch64_ext_addr_offset): New.
 154         * aarch64-dis-2.c: Regenerate.
 155         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
 156         FLD_imm4_2 and FLD_SM3_imm2.
 157         * aarch64-opc.c (fields): Add FLD_imm6_2,
 158         FLD_imm4_2 and FLD_SM3_imm2.
 159         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
 160         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
 161         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
 162         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
 163         * aarch64-tbl.h
 164         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
 165
 166 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
 167
 168         * aarch64-tbl.h
 169         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
 170         (aarch64_feature_sm4, aarch64_feature_sha3): New.
 171         (aarch64_feature_fp_16_v8_2): New.
 172         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
 173         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
 174         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
 175
 176 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
 177
 178         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
 179         (aarch64_feature_sha2, aarch64_feature_aes): New.
 180         (SHA2, AES): New.
 181         (AES_INSN, SHA2_INSN): New.
 182         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
 183         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
 184          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
 185         Change to SHA2_INS.
 186
 187 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
 188             Tamar Christina <tamar.christina@arm.com>
 189
 190         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
 191         FP16 instructions, including vfmal.f16 and vfmsl.f16.
 192
 193 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 194
 195         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
 196
 197 2017-11-07  Alan Modra  <amodra@gmail.com>
 198
 199         * opintl.h: Formatting, comment fixes.
 200         (gettext, ngettext): Redefine when ENABLE_NLS.
 201         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
 202         (_): Define using gettext.
 203         (textdomain, bindtextdomain): Use safer "do nothing".
 204
 205 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 206
 207         * arc-dis.c (print_hex): New variable.
 208         (parse_option): Check for hex option.
 209         (print_insn_arc): Use hexadecimal representation for short
 210         immediate values when requested.
 211         (print_arc_disassembler_options): Add hex option to the list.
 212
 213 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 214
 215         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
 216         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
 217         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
 218         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
 219         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 220         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 221         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 222         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 223         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 224         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 225         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 226         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 227         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 228         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 229         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 230         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 231         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 232         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 233         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 234         Changed opcodes.
 235         (prealloc, prefetch*): Place them before ld instruction.
 236         * arc-opc.c (skip_this_opcode): Add ARITH class.
 237
 238 2017-10-25  Alan Modra  <amodra@gmail.com>
 239
 240         PR 22348
 241         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 242         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 243         (imm4flag, size_changed): Likewise.
 244         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 245         (words, allWords, processing_argument_number): Likewise.
 246         (cst4flag, size_changed): Likewise.
 247         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 248         (crx_cst4_maps): Rename from cst4_maps.
 249         (crx_no_op_insn): Rename from no_op_insn.
 250
 251 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 252
 253         * riscv-opc.c (match_c_addi16sp) : New function.
 254         (match_c_addi4spn): New function.
 255         (match_c_lui): Don't allow 0-immediate encodings.
 256         (riscv_opcodes) <addi>: Use the above functions.
 257         <add>: Likewise.
 258         <c.addi4spn>: Likewise.
 259         <c.addi16sp>: Likewise.
 260
 261 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 262
 263         * i386-init.h: Regenerate
 264         * i386-tbl.h: Likewise
 265
 266 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 267
 268         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 269         (enum): Add EVEX_W_0F3854_P_2.
 270         * i386-dis-evex.h (evex_table): Updated.
 271         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 272         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 273         (cpu_flags): Add CpuAVX512_BITALG.
 274         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 275         (i386_cpu_flags): Add cpuavx512_bitalg..
 276         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 277         * i386-init.h: Regenerate.
 278         * i386-tbl.h: Likewise.
 279
 280 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 281
 282         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 283         * i386-dis-evex.h (evex_table): Updated.
 284         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 285         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 286         (cpu_flags): Add CpuAVX512_VNNI.
 287         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 288         (i386_cpu_flags): Add cpuavx512_vnni.
 289         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 290         * i386-init.h: Regenerate.
 291         * i386-tbl.h: Likewise.
 292
 293 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 294
 295         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 296         (enum): Remove VEX_LEN_0F3A44_P_2.
 297         (vex_len_table): Ditto.
 298         (enum): Remove VEX_W_0F3A44_P_2.
 299         (vew_w_table): Ditto.
 300         (prefix_table): Adjust instructions (see prefixes above).
 301         * i386-dis-evex.h (evex_table):
 302         Add new instructions (see prefixes above).
 303         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 304         (bitfield_cpu_flags): Ditto.
 305         * i386-opc.h (enum): Ditto.
 306         (i386_cpu_flags): Ditto.
 307         (CpuUnused): Comment out to avoid zero-width field problem.
 308         * i386-opc.tbl (vpclmulqdq): New instruction.
 309         * i386-init.h: Regenerate.
 310         * i386-tbl.h: Ditto.
 311
 312 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 313
 314         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 315         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 316         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 317         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 318         (vex_len_table): Ditto.
 319         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 320         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 321         (vew_w_table): Ditto.
 322         (prefix_table): Adjust instructions (see prefixes above).
 323         * i386-dis-evex.h (evex_table):
 324         Add new instructions (see prefixes above).
 325         * i386-gen.c (cpu_flag_init): Add VAES.
 326         (bitfield_cpu_flags): Ditto.
 327         * i386-opc.h (enum): Ditto.
 328         (i386_cpu_flags): Ditto.
 329         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 330         * i386-init.h: Regenerate.
 331         * i386-tbl.h: Ditto.
 332
 333 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 334
 335         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 336         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 337         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 338         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 339         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 340         (prefix_table): Updated (see prefixes above).
 341         (three_byte_table): Likewise.
 342         (vex_w_table): Likewise.
 343         * i386-dis-evex.h: Likewise.
 344         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 345         (cpu_flags): Add CpuGFNI.
 346         * i386-opc.h (enum): Add CpuGFNI.
 347         (i386_cpu_flags): Add cpugfni.
 348         * i386-opc.tbl: Add Intel GFNI instructions.
 349         * i386-init.h: Regenerate.
 350         * i386-tbl.h: Likewise.
 351
 352 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 353
 354         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 355         Define EXbScalar and EXwScalar for OP_EX.
 356         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 357         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 358         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 359         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 360         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 361         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 362         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 363         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 364         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 365         (OP_E_memory): Likewise.
 366         * i386-dis-evex.h: Updated.
 367         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 368         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 369         (cpu_flags): Add CpuAVX512_VBMI2.
 370         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 371         (i386_cpu_flags): Add cpuavx512_vbmi2.
 372         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 373         * i386-init.h: Regenerate.
 374         * i386-tbl.h: Likewise.
 375
 376 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 377
 378         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 379
 380 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 381
 382         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 383         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 384         K15. Add jmpix pattern.
 385
 386 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 387
 388         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 389
 390 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 391
 392         * s390-opc.c (INSTR_SI_RD): New macro.
 393         (INSTR_S_RD): Adjust example instruction.
 394         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 395         SI_RD.
 396
 397 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 398
 399         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 400         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 401         VLE multimple load/store instructions. Old e_ldm* variants are
 402         kept as aliases.
 403         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 404
 405 2017-09-27  Nick Clifton  <nickc@redhat.com>
 406
 407         PR 22179
 408         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 409         names for the fmv.x.s and fmv.s.x instructions respectively.
 410
 411 2017-09-26  do  <do@nerilex.org>
 412
 413         PR 22123
 414         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 415         be used on CPUs that have emacs support.
 416
 417 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 418
 419         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 420
 421 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 422
 423         * nds32-asm.c: Rename __BIT() to N32_BIT().
 424         * nds32-asm.h: Likewise.
 425         * nds32-dis.c: Likewise.
 426
 427 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 428
 429         * i386-dis.c (last_active_prefix): Removed.
 430         (ckprefix): Don't set last_active_prefix.
 431         (NOTRACK_Fixup): Don't check last_active_prefix.
 432
 433 2017-08-31  Nick Clifton  <nickc@redhat.com>
 434
 435         * po/fr.po: Updated French translation.
 436
 437 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 438
 439         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 440         fields.
 441
 442 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 443             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 444
 445         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 446         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 447         New entries efs2 and spe2.
 448         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 449         (SPE2_OPCD_SEGS): New macro.
 450         (spe2_opcd_indices): New.
 451         (disassemble_init_powerpc): Handle SPE2 opcodes.
 452         (lookup_spe2): New function.
 453         (print_insn_powerpc): call lookup_spe2.
 454         * ppc-opc.c (insert_evuimm1_ex0): New function.
 455         (extract_evuimm1_ex0): Likewise.
 456         (insert_evuimm_lt8): Likewise.
 457         (extract_evuimm_lt8): Likewise.
 458         (insert_off_spe2): Likewise.
 459         (extract_off_spe2): Likewise.
 460         (insert_Ddd): Likewise.
 461         (extract_Ddd): Likewise.
 462         (DD): New operand.
 463         (EVUIMM_LT8): Likewise.
 464         (EVUIMM_LT16): Adjust.
 465         (MMMM): New operand.
 466         (EVUIMM_1): Likewise.
 467         (EVUIMM_1_EX0): Likewise.
 468         (EVUIMM_2): Adjust.
 469         (NNN): New operand.
 470         (VX_OFF_SPE2): Likewise.
 471         (BBB): Likewise.
 472         (DDD): Likewise.
 473         (VX_MASK_DDD): New mask.
 474         (HH): New operand.
 475         (VX_RA_CONST): New macro.
 476         (VX_RA_CONST_MASK): Likewise.
 477         (VX_RB_CONST): Likewise.
 478         (VX_RB_CONST_MASK): Likewise.
 479         (VX_OFF_SPE2_MASK): Likewise.
 480         (VX_SPE_CRFD): Likewise.
 481         (VX_SPE_CRFD_MASK VX): Likewise.
 482         (VX_SPE2_CLR): Likewise.
 483         (VX_SPE2_CLR_MASK): Likewise.
 484         (VX_SPE2_SPLATB): Likewise.
 485         (VX_SPE2_SPLATB_MASK): Likewise.
 486         (VX_SPE2_OCTET): Likewise.
 487         (VX_SPE2_OCTET_MASK): Likewise.
 488         (VX_SPE2_DDHH): Likewise.
 489         (VX_SPE2_DDHH_MASK): Likewise.
 490         (VX_SPE2_HH): Likewise.
 491         (VX_SPE2_HH_MASK): Likewise.
 492         (VX_SPE2_EVMAR): Likewise.
 493         (VX_SPE2_EVMAR_MASK): Likewise.
 494         (PPCSPE2): Likewise.
 495         (PPCEFS2): Likewise.
 496         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 497         (powerpc_macros): Map old SPE instructions have new names
 498         with the same opcodes. Add SPE2 instructions which just are
 499         mapped to SPE2.
 500         (spe2_opcodes): Add SPE2 opcodes.
 501
 502 2017-08-23  Alan Modra  <amodra@gmail.com>
 503
 504         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 505         extract functions earlier, deleting forward declarations.
 506         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 507         RA_MASK.
 508
 509 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 510
 511         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 512
 513 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 514             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 515
 516         * ppc-opc.c (insert_evuimm2_ex0): New function.
 517         (extract_evuimm2_ex0): Likewise.
 518         (insert_evuimm4_ex0): Likewise.
 519         (extract_evuimm4_ex0): Likewise.
 520         (insert_evuimm8_ex0): Likewise.
 521         (extract_evuimm8_ex0): Likewise.
 522         (insert_evuimm_lt16): Likewise.
 523         (extract_evuimm_lt16): Likewise.
 524         (insert_rD_rS_even): Likewise.
 525         (extract_rD_rS_even): Likewise.
 526         (insert_off_lsp): Likewise.
 527         (extract_off_lsp): Likewise.
 528         (RD_EVEN): New operand.
 529         (RS_EVEN): Likewise.
 530         (RSQ): Adjust.
 531         (EVUIMM_LT16): New operand.
 532         (HTM_SI): Adjust.
 533         (EVUIMM_2_EX0): New operand.
 534         (EVUIMM_4): Adjust.
 535         (EVUIMM_4_EX0): New operand.
 536         (EVUIMM_8): Adjust.
 537         (EVUIMM_8_EX0): New operand.
 538         (WS): Adjust.
 539         (VX_OFF): New operand.
 540         (VX_LSP): New macro.
 541         (VX_LSP_MASK): Likewise.
 542         (VX_LSP_OFF_MASK): Likewise.
 543         (PPC_OPCODE_LSP): Likewise.
 544         (vle_opcodes): Add LSP opcodes.
 545         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 546
 547 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 548
 549         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 550         register operands in CRC instructions.
 551         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 552         comments.
 553
 554 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 555
 556         * disassemble.c (disassembler): Mark big and mach with
 557         ATTRIBUTE_UNUSED.
 558
 559 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 560
 561         * disassemble.c (disassembler): Remove arch/mach/endian
 562         assertions.
 563
 564 2017-07-25  Nick Clifton  <nickc@redhat.com>
 565
 566         PR 21739
 567         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 568         message.
 569         (insert_r0): Likewise.
 570         (insert_r1): Likewise.
 571         (insert_r2): Likewise.
 572         (insert_r3): Likewise.
 573         (insert_sp): Likewise.
 574         (insert_gp): Likewise.
 575         (insert_pcl): Likewise.
 576         (insert_blink): Likewise.
 577         (insert_ilink1): Likewise.
 578         (insert_ilink2): Likewise.
 579         (insert_ras): Likewise.
 580         (insert_rbs): Likewise.
 581         (insert_rcs): Likewise.
 582         (insert_simm3s): Likewise.
 583         (insert_rrange): Likewise.
 584         (insert_r13el): Likewise.
 585         (insert_fpel): Likewise.
 586         (insert_blinkel): Likewise.
 587         (insert_pclel): Likewise.
 588         (insert_nps_bitop_size_2b): Likewise.
 589         (insert_nps_imm_offset): Likewise.
 590         (insert_nps_imm_entry): Likewise.
 591         (insert_nps_size_16bit): Likewise.
 592         (insert_nps_##NAME##_pos): Likewise.
 593         (insert_nps_##NAME): Likewise.
 594         (insert_nps_bitop_ins_ext): Likewise.
 595         (insert_nps_##NAME): Likewise.
 596         (insert_nps_min_hofs): Likewise.
 597         (insert_nps_##NAME): Likewise.
 598         (insert_nps_rbdouble_64): Likewise.
 599         (insert_nps_misc_imm_offset): Likewise.
 600         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 601         option description.
 602
 603 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 604             Jiong Wang  <jiong.wang@arm.com>
 605
 606         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 607         correct the print.
 608         * aarch64-dis-2.c: Regenerated.
 609
 610 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 611
 612         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 613         table.
 614
 615 2017-07-20  Nick Clifton  <nickc@redhat.com>
 616
 617         * po/de.po: Updated German translation.
 618
 619 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 620
 621         * arc-regs.h (sec_stat): New aux register.
 622         (aux_kernel_sp): Likewise.
 623         (aux_sec_u_sp): Likewise.
 624         (aux_sec_k_sp): Likewise.
 625         (sec_vecbase_build): Likewise.
 626         (nsc_table_top): Likewise.
 627         (nsc_table_base): Likewise.
 628         (ersec_stat): Likewise.
 629         (aux_sec_except): Likewise.
 630
 631 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 632
 633         * arc-opc.c (extract_uimm12_20): New function.
 634         (UIMM12_20): New operand.
 635         (SIMM3_5_S): Adjust.
 636         * arc-tbl.h (sjli): Add new instruction.
 637
 638 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 639             John Eric Martin  <John.Martin@emmicro-us.com>
 640
 641         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 642         (UIMM3_23): Adjust accordingly.
 643         * arc-regs.h: Add/correct jli_base register.
 644         * arc-tbl.h (jli_s): Likewise.
 645
 646 2017-07-18  Nick Clifton  <nickc@redhat.com>
 647
 648         PR 21775
 649         * aarch64-opc.c: Fix spelling typos.
 650         * i386-dis.c: Likewise.
 651
 652 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 653
 654         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 655         max_addr_offset and octets variables to size_t.
 656
 657 2017-07-12  Alan Modra  <amodra@gmail.com>
 658
 659         * po/da.po: Update from translationproject.org/latest/opcodes/.
 660         * po/de.po: Likewise.
 661         * po/es.po: Likewise.
 662         * po/fi.po: Likewise.
 663         * po/fr.po: Likewise.
 664         * po/id.po: Likewise.
 665         * po/it.po: Likewise.
 666         * po/nl.po: Likewise.
 667         * po/pt_BR.po: Likewise.
 668         * po/ro.po: Likewise.
 669         * po/sv.po: Likewise.
 670         * po/tr.po: Likewise.
 671         * po/uk.po: Likewise.
 672         * po/vi.po: Likewise.
 673         * po/zh_CN.po: Likewise.
 674
 675 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 676             Alan Modra  <amodra@gmail.com>
 677
 678         * cgen.sh: Mark generated files read-only.
 679         * epiphany-asm.c: Regenerate.
 680         * epiphany-desc.c: Regenerate.
 681         * epiphany-desc.h: Regenerate.
 682         * epiphany-dis.c: Regenerate.
 683         * epiphany-ibld.c: Regenerate.
 684         * epiphany-opc.c: Regenerate.
 685         * epiphany-opc.h: Regenerate.
 686         * fr30-asm.c: Regenerate.
 687         * fr30-desc.c: Regenerate.
 688         * fr30-desc.h: Regenerate.
 689         * fr30-dis.c: Regenerate.
 690         * fr30-ibld.c: Regenerate.
 691         * fr30-opc.c: Regenerate.
 692         * fr30-opc.h: Regenerate.
 693         * frv-asm.c: Regenerate.
 694         * frv-desc.c: Regenerate.
 695         * frv-desc.h: Regenerate.
 696         * frv-dis.c: Regenerate.
 697         * frv-ibld.c: Regenerate.
 698         * frv-opc.c: Regenerate.
 699         * frv-opc.h: Regenerate.
 700         * ip2k-asm.c: Regenerate.
 701         * ip2k-desc.c: Regenerate.
 702         * ip2k-desc.h: Regenerate.
 703         * ip2k-dis.c: Regenerate.
 704         * ip2k-ibld.c: Regenerate.
 705         * ip2k-opc.c: Regenerate.
 706         * ip2k-opc.h: Regenerate.
 707         * iq2000-asm.c: Regenerate.
 708         * iq2000-desc.c: Regenerate.
 709         * iq2000-desc.h: Regenerate.
 710         * iq2000-dis.c: Regenerate.
 711         * iq2000-ibld.c: Regenerate.
 712         * iq2000-opc.c: Regenerate.
 713         * iq2000-opc.h: Regenerate.
 714         * lm32-asm.c: Regenerate.
 715         * lm32-desc.c: Regenerate.
 716         * lm32-desc.h: Regenerate.
 717         * lm32-dis.c: Regenerate.
 718         * lm32-ibld.c: Regenerate.
 719         * lm32-opc.c: Regenerate.
 720         * lm32-opc.h: Regenerate.
 721         * lm32-opinst.c: Regenerate.
 722         * m32c-asm.c: Regenerate.
 723         * m32c-desc.c: Regenerate.
 724         * m32c-desc.h: Regenerate.
 725         * m32c-dis.c: Regenerate.
 726         * m32c-ibld.c: Regenerate.
 727         * m32c-opc.c: Regenerate.
 728         * m32c-opc.h: Regenerate.
 729         * m32r-asm.c: Regenerate.
 730         * m32r-desc.c: Regenerate.
 731         * m32r-desc.h: Regenerate.
 732         * m32r-dis.c: Regenerate.
 733         * m32r-ibld.c: Regenerate.
 734         * m32r-opc.c: Regenerate.
 735         * m32r-opc.h: Regenerate.
 736         * m32r-opinst.c: Regenerate.
 737         * mep-asm.c: Regenerate.
 738         * mep-desc.c: Regenerate.
 739         * mep-desc.h: Regenerate.
 740         * mep-dis.c: Regenerate.
 741         * mep-ibld.c: Regenerate.
 742         * mep-opc.c: Regenerate.
 743         * mep-opc.h: Regenerate.
 744         * mt-asm.c: Regenerate.
 745         * mt-desc.c: Regenerate.
 746         * mt-desc.h: Regenerate.
 747         * mt-dis.c: Regenerate.
 748         * mt-ibld.c: Regenerate.
 749         * mt-opc.c: Regenerate.
 750         * mt-opc.h: Regenerate.
 751         * or1k-asm.c: Regenerate.
 752         * or1k-desc.c: Regenerate.
 753         * or1k-desc.h: Regenerate.
 754         * or1k-dis.c: Regenerate.
 755         * or1k-ibld.c: Regenerate.
 756         * or1k-opc.c: Regenerate.
 757         * or1k-opc.h: Regenerate.
 758         * or1k-opinst.c: Regenerate.
 759         * xc16x-asm.c: Regenerate.
 760         * xc16x-desc.c: Regenerate.
 761         * xc16x-desc.h: Regenerate.
 762         * xc16x-dis.c: Regenerate.
 763         * xc16x-ibld.c: Regenerate.
 764         * xc16x-opc.c: Regenerate.
 765         * xc16x-opc.h: Regenerate.
 766         * xstormy16-asm.c: Regenerate.
 767         * xstormy16-desc.c: Regenerate.
 768         * xstormy16-desc.h: Regenerate.
 769         * xstormy16-dis.c: Regenerate.
 770         * xstormy16-ibld.c: Regenerate.
 771         * xstormy16-opc.c: Regenerate.
 772         * xstormy16-opc.h: Regenerate.
 773
 774 2017-07-07  Alan Modra  <amodra@gmail.com>
 775
 776         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 777         * m32c-dis.c: Regenerate.
 778         * mep-dis.c: Regenerate.
 779
 780 2017-07-05  Borislav Petkov  <bp@suse.de>
 781
 782         * i386-dis.c: Enable ModRM.reg /6 aliases.
 783
 784 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 785
 786         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 787         with vmrs and vmsr.
 788
 789 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 790
 791         * configure: Regenerate.
 792
 793 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 794
 795         * po/opcodes.pot: Regenerate.
 796
 797 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 798
 799         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 800         entries to the MSA ASE instruction block.
 801
 802 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 803             Maciej W. Rozycki  <macro@imgtec.com>
 804
 805         * micromips-opc.c (XPA, XPAVZ): New macros.
 806         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 807         "mthgc0".
 808
 809 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 810             Maciej W. Rozycki  <macro@imgtec.com>
 811
 812         * micromips-opc.c (I36): New macro.
 813         (micromips_opcodes): Add "eretnc".
 814
 815 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 816             Andrew Bennett  <andrew.bennett@imgtec.com>
 817
 818         * mips-dis.c (mips_calculate_combination_ases): Handle the
 819         ASE_XPA_VIRT flag.
 820         (parse_mips_ase_option): New function.
 821         (parse_mips_dis_option): Factor out ASE option handling to the
 822         new function.  Call `mips_calculate_combination_ases'.
 823         * mips-opc.c (XPAVZ): New macro.
 824         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 825         "mfhgc0", "mthc0" and "mthgc0".
 826
 827 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 828
 829         * mips-dis.c (mips_calculate_combination_ases): New function.
 830         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 831         calculation to the new function.
 832         (set_default_mips_dis_options): Call the new function.
 833
 834 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 835
 836         * arc-dis.c (parse_disassembler_options): Use
 837         FOR_EACH_DISASSEMBLER_OPTION.
 838
 839 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 840
 841         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 842         disassembler option strings.
 843         (parse_cpu_option): Likewise.
 844
 845 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 846
 847         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 848         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 849         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 850         (aarch64_feature_dotprod, DOT_INSN): New.
 851         (udot, sdot): New.
 852         * aarch64-dis-2.c: Regenerated.
 853
 854 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 855
 856         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 857
 858 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 859             Matthew Fortune  <matthew.fortune@imgtec.com>
 860             Andrew Bennett  <andrew.bennett@imgtec.com>
 861
 862         * mips-formats.h (INT_BIAS): New macro.
 863         (INT_ADJ): Redefine in INT_BIAS terms.
 864         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 865         (mips_print_save_restore): New function.
 866         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 867         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 868         call.
 869         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 870         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 871         OP_SAVE_RESTORE_LIST handling, factored out from here.
 872         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 873         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 874         (mips_builtin_opcodes): Add "restore" and "save" entries.
 875         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 876         (IAMR2): New macro.
 877         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 878
 879 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 880
 881         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 882         alias; do not mark SLTI instruction as an alias.
 883
 884 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 885
 886         * i386-dis.c (RM_0FAE_REG_5): Removed.
 887         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 888         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 889         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 890         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 891         PREFIX_MOD_3_0F01_REG_5_RM_0.
 892         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 893         PREFIX_MOD_3_0FAE_REG_5.
 894         (mod_table): Update MOD_0FAE_REG_5.
 895         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 896         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 897         * i386-tbl.h: Regenerated.
 898
 899 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 900
 901         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 902         * i386-opc.tbl: Likewise.
 903         * i386-tbl.h: Regenerated.
 904
 905 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 906
 907         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 908         and "jmp{&|}".
 909         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 910         prefix.
 911
 912 2017-06-19  Nick Clifton  <nickc@redhat.com>
 913
 914         PR binutils/21614
 915         * score-dis.c (score_opcodes): Add sentinel.
 916
 917 2017-06-16  Alan Modra  <amodra@gmail.com>
 918
 919         * rx-decode.c: Regenerate.
 920
 921 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 922
 923         PR binutils/21594
 924         * i386-dis.c (OP_E_register): Check valid bnd register.
 925         (OP_G): Likewise.
 926
 927 2017-06-15  Nick Clifton  <nickc@redhat.com>
 928
 929         PR binutils/21595
 930         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 931         range value.
 932
 933 2017-06-15  Nick Clifton  <nickc@redhat.com>
 934
 935         PR binutils/21588
 936         * rl78-decode.opc (OP_BUF_LEN): Define.
 937         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 938         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 939         array.
 940         * rl78-decode.c: Regenerate.
 941
 942 2017-06-15  Nick Clifton  <nickc@redhat.com>
 943
 944         PR binutils/21586
 945         * bfin-dis.c (gregs): Clip index to prevent overflow.
 946         (regs): Likewise.
 947         (regs_lo): Likewise.
 948         (regs_hi): Likewise.
 949
 950 2017-06-14  Nick Clifton  <nickc@redhat.com>
 951
 952         PR binutils/21576
 953         * score7-dis.c (score_opcodes): Add sentinel.
 954
 955 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 956
 957         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 958         * arm-dis.c: Likewise.
 959         * ia64-dis.c: Likewise.
 960         * mips-dis.c: Likewise.
 961         * spu-dis.c: Likewise.
 962         * disassemble.h (print_insn_aarch64): New declaration, moved from
 963         include/dis-asm.h.
 964         (print_insn_big_arm, print_insn_big_mips): Likewise.
 965         (print_insn_i386, print_insn_ia64): Likewise.
 966         (print_insn_little_arm, print_insn_little_mips): Likewise.
 967
 968 2017-06-14  Nick Clifton  <nickc@redhat.com>
 969
 970         PR binutils/21587
 971         * rx-decode.opc: Include libiberty.h
 972         (GET_SCALE): New macro - validates access to SCALE array.
 973         (GET_PSCALE): New macro - validates access to PSCALE array.
 974         (DIs, SIs, S2Is, rx_disp): Use new macros.
 975         * rx-decode.c: Regenerate.
 976
 977 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 978
 979         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 980
 981 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 982
 983         * arc-dis.c (enforced_isa_mask): Declare.
 984         (cpu_types): Likewise.
 985         (parse_cpu_option): New function.
 986         (parse_disassembler_options): Use it.
 987         (print_insn_arc): Use enforced_isa_mask.
 988         (print_arc_disassembler_options): Document new options.
 989
 990 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 991
 992         * alpha-dis.c: Include disassemble.h, don't include
 993         dis-asm.h.
 994         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 995         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 996         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 997         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 998         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 999         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1000         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1001         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1002         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1003         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1004         * moxie-dis.c, msp430-dis.c, mt-dis.c:
1005         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1006         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1007         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1008         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1009         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1010         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1011         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1012         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1013         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1014         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1015         * z80-dis.c, z8k-dis.c: Likewise.
1016         * disassemble.h: New file.
1017
1018 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1019
1020         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1021         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1022
1023 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1024
1025         * disassemble.c (disassembler): Add arguments a, big and mach.
1026         Use them.
1027
1028 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
1029
1030         * i386-dis.c (NOTRACK_Fixup): New.
1031         (NOTRACK): Likewise.
1032         (NOTRACK_PREFIX): Likewise.
1033         (last_active_prefix): Likewise.
1034         (reg_table): Use NOTRACK on indirect call and jmp.
1035         (ckprefix): Set last_active_prefix.
1036         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1037         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1038         * i386-opc.h (NoTrackPrefixOk): New.
1039         (i386_opcode_modifier): Add notrackprefixok.
1040         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1041         Add notrack.
1042         * i386-tbl.h: Regenerated.
1043
1044 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
1045
1046         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1047         (X_IMM2): Define.
1048         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1049         bfd_mach_sparc_v9m8.
1050         (print_insn_sparc): Handle new operand types.
1051         * sparc-opc.c (MASK_M8): Define.
1052         (v6): Add MASK_M8.
1053         (v6notlet): Likewise.
1054         (v7): Likewise.
1055         (v8): Likewise.
1056         (v9): Likewise.
1057         (v9a): Likewise.
1058         (v9b): Likewise.
1059         (v9c): Likewise.
1060         (v9d): Likewise.
1061         (v9e): Likewise.
1062         (v9v): Likewise.
1063         (v9m): Likewise.
1064         (v9andleon): Likewise.
1065         (m8): Define.
1066         (HWS_VM8): Define.
1067         (HWS2_VM8): Likewise.
1068         (sparc_opcode_archs): Add entry for "m8".
1069         (sparc_opcodes): Add OSA2017 and M8 instructions
1070         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1071         fpx{ll,ra,rl}64x,
1072         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1073         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1074         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1075         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1076         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1077         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1078         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1079         ASI_CORE_SELECT_COMMIT_NHT.
1080
1081 2017-05-18  Alan Modra  <amodra@gmail.com>
1082
1083         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1084         * aarch64-dis.c: Likewise.
1085         * aarch64-gen.c: Likewise.
1086         * aarch64-opc.c: Likewise.
1087
1088 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1089             Matthew Fortune  <matthew.fortune@imgtec.com>
1090
1091         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1092         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1093         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1094         (print_insn_arg) <OP_REG28>: Add handler.
1095         (validate_insn_args) <OP_REG28>: Handle.
1096         (print_mips16_insn_arg): Handle MIPS16 instructions that require
1097         32-bit encoding and 9-bit immediates.
1098         (print_insn_mips16): Handle MIPS16 instructions that require
1099         32-bit encoding and MFC0/MTC0 operand decoding.
1100         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1101         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1102         (RD_C0, WR_C0, E2, E2MT): New macros.
1103         (mips16_opcodes): Add entries for MIPS16e2 instructions:
1104         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1105         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1106         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1107         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1108         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1109         instructions, "swl", "swr", "sync" and its "sync_acquire",
1110         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1111         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
1112         regular/extended entries for original MIPS16 ISA revision
1113         instructions whose extended forms are subdecoded in the MIPS16e2
1114         ISA revision: "li", "sll" and "srl".
1115
1116 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1117
1118         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1119         reference in CP0 move operand decoding.
1120
1121 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1122
1123         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1124         type to hexadecimal.
1125         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1126
1127 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1128
1129         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1130         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1131         "sync_rmb" and "sync_wmb" as aliases.
1132         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1133         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1134
1135 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1136
1137         * arc-dis.c (parse_option): Update quarkse_em option..
1138         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1139         QUARKSE1.
1140         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1141
1142 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1143
1144         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1145
1146 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1147
1148         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1149         register.
1150
1151 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1152
1153         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1154         and branches and not synthetic data instructions.
1155
1156 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1157
1158         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1159
1160 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1161
1162         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1163         * arc-opc.c (insert_r13el): New function.
1164         (R13_EL): Define.
1165         * arc-tbl.h: Add new enter/leave variants.
1166
1167 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1168
1169         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1170
1171 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1172
1173         * mips-dis.c (print_mips_disassembler_options): Add
1174         `no-aliases'.
1175
1176 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1177
1178         * mips16-opc.c (AL): New macro.
1179         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1180         of "ld" and "lw" as aliases.
1181
1182 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1183
1184         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1185         arguments.
1186
1187 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1188             Alan Modra  <amodra@gmail.com>
1189
1190         * ppc-opc.c (ELEV): Define.
1191         (vle_opcodes): Add se_rfgi and e_sc.
1192         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1193         for E200Z4.
1194
1195 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1196
1197         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1198
1199 2017-04-21  Nick Clifton  <nickc@redhat.com>
1200
1201         PR binutils/21380
1202         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1203         LD3R and LD4R.
1204
1205 2017-04-13  Alan Modra  <amodra@gmail.com>
1206
1207         * epiphany-desc.c: Regenerate.
1208         * fr30-desc.c: Regenerate.
1209         * frv-desc.c: Regenerate.
1210         * ip2k-desc.c: Regenerate.
1211         * iq2000-desc.c: Regenerate.
1212         * lm32-desc.c: Regenerate.
1213         * m32c-desc.c: Regenerate.
1214         * m32r-desc.c: Regenerate.
1215         * mep-desc.c: Regenerate.
1216         * mt-desc.c: Regenerate.
1217         * or1k-desc.c: Regenerate.
1218         * xc16x-desc.c: Regenerate.
1219         * xstormy16-desc.c: Regenerate.
1220
1221 2017-04-11  Alan Modra  <amodra@gmail.com>
1222
1223         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1224         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1225         PPC_OPCODE_TMR for e6500.
1226         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1227         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1228         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1229         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1230         (PPCHTM): Define as PPC_OPCODE_POWER8.
1231         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1232
1233 2017-04-10  Alan Modra  <amodra@gmail.com>
1234
1235         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1236         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1237         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1238         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1239
1240 2017-04-09  Pip Cet  <pipcet@gmail.com>
1241
1242         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1243         appropriate floating-point precision directly.
1244
1245 2017-04-07  Alan Modra  <amodra@gmail.com>
1246
1247         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1248         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1249         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1250         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1251         vector instructions with E6500 not PPCVEC2.
1252
1253 2017-04-06  Pip Cet  <pipcet@gmail.com>
1254
1255         * Makefile.am: Add wasm32-dis.c.
1256         * configure.ac: Add wasm32-dis.c to wasm32 target.
1257         * disassemble.c: Add wasm32 disassembler code.
1258         * wasm32-dis.c: New file.
1259         * Makefile.in: Regenerate.
1260         * configure: Regenerate.
1261         * po/POTFILES.in: Regenerate.
1262         * po/opcodes.pot: Regenerate.
1263
1264 2017-04-05  Pedro Alves  <palves@redhat.com>
1265
1266         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1267         * arm-dis.c (parse_arm_disassembler_options): Constify.
1268         * ppc-dis.c (powerpc_init_dialect): Constify local.
1269         * vax-dis.c (parse_disassembler_options): Constify.
1270
1271 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1272
1273         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1274         RISCV_GP_SYMBOL.
1275
1276 2017-03-30  Pip Cet  <pipcet@gmail.com>
1277
1278         * configure.ac: Add (empty) bfd_wasm32_arch target.
1279         * configure: Regenerate
1280         * po/opcodes.pot: Regenerate.
1281
1282 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1283
1284         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1285         OSA2015.
1286         * opcodes/sparc-opc.c (asi_table): New ASIs.
1287
1288 2017-03-29  Alan Modra  <amodra@gmail.com>
1289
1290         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1291         "raw" option.
1292         (lookup_powerpc): Don't special case -1 dialect.  Handle
1293         PPC_OPCODE_RAW.
1294         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1295         lookup_powerpc call, pass it on second.
1296
1297 2017-03-27  Alan Modra  <amodra@gmail.com>
1298
1299         PR 21303
1300         * ppc-dis.c (struct ppc_mopt): Comment.
1301         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1302
1303 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1304
1305         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1306         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1307         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1308         (insert_nps_misc_imm_offset): New function.
1309         (extract_nps_misc imm_offset): New function.
1310         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1311         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1312
1313 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1314
1315         * s390-mkopc.c (main): Remove vx2 check.
1316         * s390-opc.txt: Remove vx2 instruction flags.
1317
1318 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1319
1320         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1321         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1322         (insert_nps_imm_offset): New function.
1323         (extract_nps_imm_offset): New function.
1324         (insert_nps_imm_entry): New function.
1325         (extract_nps_imm_entry): New function.
1326
1327 2017-03-17  Alan Modra  <amodra@gmail.com>
1328
1329         PR 21248
1330         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1331         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1332         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1333
1334 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1335
1336         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1337         <c.andi>: Likewise.
1338         <c.addiw> Likewise.
1339
1340 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1341
1342         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1343
1344 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1345
1346         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1347         <srl> Likewise.
1348         <srai> Likewise.
1349         <sra> Likewise.
1350
1351 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1352
1353         * i386-gen.c (opcode_modifiers): Replace S with Load.
1354         * i386-opc.h (S): Removed.
1355         (Load): New.
1356         (i386_opcode_modifier): Replace s with load.
1357         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1358         and {evex}.  Replace S with Load.
1359         * i386-tbl.h: Regenerated.
1360
1361 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1362
1363         * i386-opc.tbl: Use CpuCET on rdsspq.
1364         * i386-tbl.h: Regenerated.
1365
1366 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1367
1368         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1369         <vsx>: Do not use PPC_OPCODE_VSX3;
1370
1371 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1372
1373         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1374
1375 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1376
1377         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1378         (MOD_0F1E_PREFIX_1): Likewise.
1379         (MOD_0F38F5_PREFIX_2): Likewise.
1380         (MOD_0F38F6_PREFIX_0): Likewise.
1381         (RM_0F1E_MOD_3_REG_7): Likewise.
1382         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1383         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1384         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1385         (PREFIX_0F1E): Likewise.
1386         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1387         (PREFIX_0F38F5): Likewise.
1388         (dis386_twobyte): Use PREFIX_0F1E.
1389         (reg_table): Add REG_0F1E_MOD_3.
1390         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1391         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1392         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1393         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1394         (three_byte_table): Use PREFIX_0F38F5.
1395         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1396         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1397         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1398         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1399         PREFIX_MOD_3_0F01_REG_5_RM_2.
1400         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1401         (cpu_flags): Add CpuCET.
1402         * i386-opc.h (CpuCET): New enum.
1403         (CpuUnused): Commented out.
1404         (i386_cpu_flags): Add cpucet.
1405         * i386-opc.tbl: Add Intel CET instructions.
1406         * i386-init.h: Regenerated.
1407         * i386-tbl.h: Likewise.
1408
1409 2017-03-06  Alan Modra  <amodra@gmail.com>
1410
1411         PR 21124
1412         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1413         (extract_raq, extract_ras, extract_rbx): New functions.
1414         (powerpc_operands): Use opposite corresponding insert function.
1415         (Q_MASK): Define.
1416         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1417         register restriction.
1418
1419 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1420
1421         * disassemble.c Include "safe-ctype.h".
1422         (disassemble_init_for_target): Handle s390 init.
1423         (remove_whitespace_and_extra_commas): New function.
1424         (disassembler_options_cmp): Likewise.
1425         * arm-dis.c: Include "libiberty.h".
1426         (NUM_ELEM): Delete.
1427         (regnames): Use long disassembler style names.
1428         Add force-thumb and no-force-thumb options.
1429         (NUM_ARM_REGNAMES): Rename from this...
1430         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1431         (get_arm_regname_num_options): Delete.
1432         (set_arm_regname_option): Likewise.
1433         (get_arm_regnames): Likewise.
1434         (parse_disassembler_options): Likewise.
1435         (parse_arm_disassembler_option): Rename from this...
1436         (parse_arm_disassembler_options): ...to this.  Make static.
1437         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1438         (print_insn): Use parse_arm_disassembler_options.
1439         (disassembler_options_arm): New function.
1440         (print_arm_disassembler_options): Handle updated regnames.
1441         * ppc-dis.c: Include "libiberty.h".
1442         (ppc_opts): Add "32" and "64" entries.
1443         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1444         (powerpc_init_dialect): Add break to switch statement.
1445         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1446         (disassembler_options_powerpc): New function.
1447         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1448         Remove printing of "32" and "64".
1449         * s390-dis.c: Include "libiberty.h".
1450         (init_flag): Remove unneeded variable.
1451         (struct s390_options_t): New structure type.
1452         (options): New structure.
1453         (init_disasm): Rename from this...
1454         (disassemble_init_s390): ...to this.  Add initializations for
1455         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1456         (print_insn_s390): Delete call to init_disasm.
1457         (disassembler_options_s390): New function.
1458         (print_s390_disassembler_options): Print using information from
1459         struct 'options'.
1460         * po/opcodes.pot: Regenerate.
1461
1462 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1463
1464         * i386-dis.c (PCMPESTR_Fixup): New.
1465         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1466         (prefix_table): Use PCMPESTR_Fixup.
1467         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1468         PCMPESTR_Fixup.
1469         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1470         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1471         Split 64-bit and non-64-bit variants.
1472         * opcodes/i386-tbl.h: Re-generate.
1473
1474 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1475
1476         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1477         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1478         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1479         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1480         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1481         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1482         (OP_SVE_V_HSD): New macros.
1483         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1484         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1485         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1486         (aarch64_opcode_table): Add new SVE instructions.
1487         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1488         for rotation operands.  Add new SVE operands.
1489         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1490         (ins_sve_quad_index): Likewise.
1491         (ins_imm_rotate): Split into...
1492         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1493         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1494         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1495         functions.
1496         (aarch64_ins_sve_addr_ri_s4): New function.
1497         (aarch64_ins_sve_quad_index): Likewise.
1498         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1499         * aarch64-asm-2.c: Regenerate.
1500         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1501         (ext_sve_quad_index): Likewise.
1502         (ext_imm_rotate): Split into...
1503         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1504         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1505         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1506         functions.
1507         (aarch64_ext_sve_addr_ri_s4): New function.
1508         (aarch64_ext_sve_quad_index): Likewise.
1509         (aarch64_ext_sve_index): Allow quad indices.
1510         (do_misc_decoding): Likewise.
1511         * aarch64-dis-2.c: Regenerate.
1512         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1513         aarch64_field_kinds.
1514         (OPD_F_OD_MASK): Widen by one bit.
1515         (OPD_F_NO_ZR): Bump accordingly.
1516         (get_operand_field_width): New function.
1517         * aarch64-opc.c (fields): Add new SVE fields.
1518         (operand_general_constraint_met_p): Handle new SVE operands.
1519         (aarch64_print_operand): Likewise.
1520         * aarch64-opc-2.c: Regenerate.
1521
1522 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1523
1524         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1525         (aarch64_feature_compnum): ...this.
1526         (SIMD_V8_3): Replace with...
1527         (COMPNUM): ...this.
1528         (CNUM_INSN): New macro.
1529         (aarch64_opcode_table): Use it for the complex number instructions.
1530
1531 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1532
1533         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1534
1535 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1536
1537         Add support for associating SPARC ASIs with an architecture level.
1538         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1539         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1540         decoding of SPARC ASIs.
1541
1542 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1543
1544         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1545         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1546
1547 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1548
1549         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1550         1 (instead of to itself). Correct typo.
1551
1552 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1553
1554         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1555         pseudoinstructions.
1556
1557 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1558
1559         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1560         (aarch64_sys_reg_supported_p): Handle them.
1561
1562 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1563
1564         * arc-opc.c (UIMM6_20R): Define.
1565         (SIMM12_20): Use above.
1566         (SIMM12_20R): Define.
1567         (SIMM3_5_S): Use above.
1568         (UIMM7_A32_11R_S): Define.
1569         (UIMM7_9_S): Use above.
1570         (UIMM3_13R_S): Define.
1571         (SIMM11_A32_7_S): Use above.
1572         (SIMM9_8R): Define.
1573         (UIMM10_A32_8_S): Use above.
1574         (UIMM8_8R_S): Define.
1575         (W6): Use above.
1576         (arc_relax_opcodes): Use all above defines.
1577
1578 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1579
1580         * arc-regs.h: Distinguish some of the registers different on
1581         ARC700 and HS38 cpus.
1582
1583 2017-02-14  Alan Modra  <amodra@gmail.com>
1584
1585         PR 21118
1586         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1587         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1588
1589 2017-02-11  Stafford Horne  <shorne@gmail.com>
1590             Alan Modra  <amodra@gmail.com>
1591
1592         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1593         Use insn_bytes_value and insn_int_value directly instead.  Don't
1594         free allocated memory until function exit.
1595
1596 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1597
1598         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1599
1600 2017-02-03  Nick Clifton  <nickc@redhat.com>
1601
1602         PR 21096
1603         * aarch64-opc.c (print_register_list): Ensure that the register
1604         list index will fir into the tb buffer.
1605         (print_register_offset_address): Likewise.
1606         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1607
1608 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1609
1610         PR 21056
1611         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1612         instructions when the previous fetch packet ends with a 32-bit
1613         instruction.
1614
1615 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1616
1617         * pru-opc.c: Remove vague reference to a future GDB port.
1618
1619 2017-01-20  Nick Clifton  <nickc@redhat.com>
1620
1621         * po/ga.po: Updated Irish translation.
1622
1623 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1624
1625         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1626
1627 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1628
1629         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1630         if FETCH_DATA returns 0.
1631         (m68k_scan_mask): Likewise.
1632         (print_insn_m68k): Update code to handle -1 return value.
1633
1634 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1635
1636         * m68k-dis.c (enum print_insn_arg_error): New.
1637         (NEXTBYTE): Replace -3 with
1638         PRINT_INSN_ARG_MEMORY_ERROR.
1639         (NEXTULONG): Likewise.
1640         (NEXTSINGLE): Likewise.
1641         (NEXTDOUBLE): Likewise.
1642         (NEXTDOUBLE): Likewise.
1643         (NEXTPACKED): Likewise.
1644         (FETCH_ARG): Likewise.
1645         (FETCH_DATA): Update comments.
1646         (print_insn_arg): Update comments. Replace magic numbers with
1647         enum.
1648         (match_insn_m68k): Likewise.
1649
1650 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1651
1652         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1653         * i386-dis-evex.h (evex_table): Updated.
1654         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1655         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1656         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1657         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1658         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1659         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1660         * i386-init.h: Regenerate.
1661         * i386-tbl.h: Ditto.
1662
1663 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1664
1665         * msp430-dis.c (msp430_singleoperand): Return -1 if
1666         msp430dis_opcode_signed returns false.
1667         (msp430_doubleoperand): Likewise.
1668         (msp430_branchinstr): Return -1 if
1669         msp430dis_opcode_unsigned returns false.
1670         (msp430x_calla_instr): Likewise.
1671         (print_insn_msp430): Likewise.
1672
1673 2017-01-05  Nick Clifton  <nickc@redhat.com>
1674
1675         PR 20946
1676         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1677         could not be matched.
1678         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1679         NULL.
1680
1681 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1682
1683         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1684         (aarch64_opcode_table): Use RCPC_INSN.
1685
1686 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1687
1688         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1689         extension.
1690         * riscv-opcodes/all-opcodes: Likewise.
1691
1692 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1693
1694         * riscv-dis.c (print_insn_args): Add fall through comment.
1695
1696 2017-01-03  Nick Clifton  <nickc@redhat.com>
1697
1698         * po/sr.po: New Serbian translation.
1699         * configure.ac (ALL_LINGUAS): Add sr.
1700         * configure: Regenerate.
1701
1702 2017-01-02  Alan Modra  <amodra@gmail.com>
1703
1704         * epiphany-desc.h: Regenerate.
1705         * epiphany-opc.h: Regenerate.
1706         * fr30-desc.h: Regenerate.
1707         * fr30-opc.h: Regenerate.
1708         * frv-desc.h: Regenerate.
1709         * frv-opc.h: Regenerate.
1710         * ip2k-desc.h: Regenerate.
1711         * ip2k-opc.h: Regenerate.
1712         * iq2000-desc.h: Regenerate.
1713         * iq2000-opc.h: Regenerate.
1714         * lm32-desc.h: Regenerate.
1715         * lm32-opc.h: Regenerate.
1716         * m32c-desc.h: Regenerate.
1717         * m32c-opc.h: Regenerate.
1718         * m32r-desc.h: Regenerate.
1719         * m32r-opc.h: Regenerate.
1720         * mep-desc.h: Regenerate.
1721         * mep-opc.h: Regenerate.
1722         * mt-desc.h: Regenerate.
1723         * mt-opc.h: Regenerate.
1724         * or1k-desc.h: Regenerate.
1725         * or1k-opc.h: Regenerate.
1726         * xc16x-desc.h: Regenerate.
1727         * xc16x-opc.h: Regenerate.
1728         * xstormy16-desc.h: Regenerate.
1729         * xstormy16-opc.h: Regenerate.
1730
1731 2017-01-02  Alan Modra  <amodra@gmail.com>
1732
1733         Update year range in copyright notice of all files.
1734
1735 For older changes see ChangeLog-2016
1736 \f
1737 Copyright (C) 2017 Free Software Foundation, Inc.
1738
1739 Copying and distribution of this file, with or without modification,
1740 are permitted in any medium without royalty provided the copyright
1741 notice and this notice are preserved.
1742
1743 Local Variables:
1744 mode: change-log
1745 left-margin: 8
1746 fill-column: 74
1747 version-control: never
1748 End: