opcodes/ChangeLog

   1 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR binutils/24691
   4         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
   5         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
   6         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
   7         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
   8         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
   9         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
  10         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
  11         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
  12         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
  13         EVEX_LEN_0F3A43_P_2_W_1.
  14         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
  15         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
  16         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
  17         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
  18         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
  19         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
  20         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
  21         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
  22         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
  23         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
  24         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
  25         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
  26
  27 2019-06-14  Nick Clifton  <nickc@redhat.com>
  28
  29         * po/fr.po; Updated French translation.
  30
  31 2019-06-13  Stafford Horne  <shorne@gmail.com>
  32
  33         * or1k-asm.c: Regenerated.
  34         * or1k-desc.c: Regenerated.
  35         * or1k-desc.h: Regenerated.
  36         * or1k-dis.c: Regenerated.
  37         * or1k-ibld.c: Regenerated.
  38         * or1k-opc.c: Regenerated.
  39         * or1k-opc.h: Regenerated.
  40         * or1k-opinst.c: Regenerated.
  41
  42 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
  43
  44         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
  45
  46 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
  47
  48         PR binutils/24633
  49         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
  50         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
  51         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
  52         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
  53         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
  54         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
  55         EVEX_LEN_0F3A1B_P_2_W_1.
  56         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
  57         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
  58         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
  59         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
  60         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
  61         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
  62         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
  63         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
  64
  65 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
  66
  67         PR binutils/24626
  68         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
  69         EVEX.vvvv when disassembling VEX and EVEX instructions.
  70         (OP_VEX): Set vex.register_specifier to 0 after readding
  71         vex.register_specifier.
  72         (OP_Vex_2src_1): Likewise.
  73         (OP_Vex_2src_2): Likewise.
  74         (OP_LWP_E): Likewise.
  75         (OP_EX_Vex): Don't check vex.register_specifier.
  76         (OP_XMM_Vex): Likewise.
  77
  78 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  79             Lili Cui  <lili.cui@intel.com>
  80
  81         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
  82         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
  83         instructions.
  84         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
  85         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
  86         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
  87         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
  88         (i386_cpu_flags): Add cpuavx512_vp2intersect.
  89         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
  90         * i386-init.h: Regenerated.
  91         * i386-tbl.h: Likewise.
  92
  93 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
  94             Lili Cui  <lili.cui@intel.com>
  95
  96         * doc/c-i386.texi: Document enqcmd.
  97         * testsuite/gas/i386/enqcmd-intel.d: New file.
  98         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
  99         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 100         * testsuite/gas/i386/enqcmd.d: Likewise.
 101         * testsuite/gas/i386/enqcmd.s: Likewise.
 102         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 103         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 104         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 105         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 106         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 107         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 108         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 109         and x86-64-enqcmd.
 110
 111 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 112
 113         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 114
 115 2019-06-03  Alan Modra  <amodra@gmail.com>
 116
 117         * ppc-dis.c (prefix_opcd_indices): Correct size.
 118
 119 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 120
 121         PR gas/24625
 122         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 123         Disp8ShiftVL.
 124         * i386-tbl.h: Regenerated.
 125
 126 2019-05-24  Alan Modra  <amodra@gmail.com>
 127
 128         * po/POTFILES.in: Regenerate.
 129
 130 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 131             Alan Modra  <amodra@gmail.com>
 132
 133         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 134         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 135         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 136         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 137         XTOP>): Define and add entries.
 138         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 139         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 140         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 141         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 142
 143 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 144             Alan Modra  <amodra@gmail.com>
 145
 146         * ppc-dis.c (ppc_opts): Add "future" entry.
 147         (PREFIX_OPCD_SEGS): Define.
 148         (prefix_opcd_indices): New array.
 149         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 150         (lookup_prefix): New function.
 151         (print_insn_powerpc): Handle 64-bit prefix instructions.
 152         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 153         (PMRR, POWERXX): Define.
 154         (prefix_opcodes): New instruction table.
 155         (prefix_num_opcodes): New constant.
 156
 157 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 158
 159         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 160         * configure: Regenerated.
 161         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 162         and cpu/bpf.opc.
 163         (HFILES): Add bpf-desc.h and bpf-opc.h.
 164         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 165         bpf-ibld.c and bpf-opc.c.
 166         (BPF_DEPS): Define.
 167         * Makefile.in: Regenerated.
 168         * disassemble.c (ARCH_bpf): Define.
 169         (disassembler): Add case for bfd_arch_bpf.
 170         (disassemble_init_for_target): Likewise.
 171         (enum epbf_isa_attr): Define.
 172         * disassemble.h: extern print_insn_bpf.
 173         * bpf-asm.c: Generated.
 174         * bpf-opc.h: Likewise.
 175         * bpf-opc.c: Likewise.
 176         * bpf-ibld.c: Likewise.
 177         * bpf-dis.c: Likewise.
 178         * bpf-desc.h: Likewise.
 179         * bpf-desc.c: Likewise.
 180
 181 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 182
 183         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 184         and VMSR with the new operands.
 185
 186 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 187
 188         * arm-dis.c (enum mve_instructions): New enum
 189         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 190         and cneg.
 191         (mve_opcodes): New instructions as above.
 192         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 193         csneg and csel.
 194         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 195
 196 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 197
 198         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 199         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 200         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 201         uqshl, urshrl and urshr.
 202         (is_mve_okay_in_it): Add new instructions to TRUE list.
 203         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 204         (print_insn_mve): Updated to accept new %j,
 205         %<bitfield>m and %<bitfield>n patterns.
 206
 207 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 208
 209         * mips-opc.c (mips_builtin_opcodes): Change source register
 210         constraint for DAUI.
 211
 212 2019-05-20  Nick Clifton  <nickc@redhat.com>
 213
 214         * po/fr.po: Updated French translation.
 215
 216 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 217             Michael Collison <michael.collison@arm.com>
 218
 219         * arm-dis.c (thumb32_opcodes): Add new instructions.
 220         (enum mve_instructions): Likewise.
 221         (enum mve_undefined): Add new reasons.
 222         (is_mve_encoding_conflict): Handle new instructions.
 223         (is_mve_undefined): Likewise.
 224         (is_mve_unpredictable): Likewise.
 225         (print_mve_undefined): Likewise.
 226         (print_mve_size): Likewise.
 227
 228 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 229             Michael Collison <michael.collison@arm.com>
 230
 231         * arm-dis.c (thumb32_opcodes): Add new instructions.
 232         (enum mve_instructions): Likewise.
 233         (is_mve_encoding_conflict): Handle new instructions.
 234         (is_mve_undefined): Likewise.
 235         (is_mve_unpredictable): Likewise.
 236         (print_mve_size): Likewise.
 237
 238 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 239             Michael Collison <michael.collison@arm.com>
 240
 241         * arm-dis.c (thumb32_opcodes): Add new instructions.
 242         (enum mve_instructions): Likewise.
 243         (is_mve_encoding_conflict): Likewise.
 244         (is_mve_unpredictable): Likewise.
 245         (print_mve_size): Likewise.
 246
 247 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 248             Michael Collison <michael.collison@arm.com>
 249
 250         * arm-dis.c (thumb32_opcodes): Add new instructions.
 251         (enum mve_instructions): Likewise.
 252         (is_mve_encoding_conflict): Handle new instructions.
 253         (is_mve_undefined): Likewise.
 254         (is_mve_unpredictable): Likewise.
 255         (print_mve_size): Likewise.
 256
 257 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 258             Michael Collison <michael.collison@arm.com>
 259
 260         * arm-dis.c (thumb32_opcodes): Add new instructions.
 261         (enum mve_instructions): Likewise.
 262         (is_mve_encoding_conflict): Handle new instructions.
 263         (is_mve_undefined): Likewise.
 264         (is_mve_unpredictable): Likewise.
 265         (print_mve_size): Likewise.
 266         (print_insn_mve): Likewise.
 267
 268 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 269             Michael Collison <michael.collison@arm.com>
 270
 271         * arm-dis.c (thumb32_opcodes): Add new instructions.
 272         (print_insn_thumb32): Handle new instructions.
 273
 274 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 275             Michael Collison <michael.collison@arm.com>
 276
 277         * arm-dis.c (enum mve_instructions): Add new instructions.
 278         (enum mve_undefined): Add new reasons.
 279         (is_mve_encoding_conflict): Handle new instructions.
 280         (is_mve_undefined): Likewise.
 281         (is_mve_unpredictable): Likewise.
 282         (print_mve_undefined): Likewise.
 283         (print_mve_size): Likewise.
 284         (print_mve_shift_n): Likewise.
 285         (print_insn_mve): Likewise.
 286
 287 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 288             Michael Collison <michael.collison@arm.com>
 289
 290         * arm-dis.c (enum mve_instructions): Add new instructions.
 291         (is_mve_encoding_conflict): Handle new instructions.
 292         (is_mve_unpredictable): Likewise.
 293         (print_mve_rotate): Likewise.
 294         (print_mve_size): Likewise.
 295         (print_insn_mve): Likewise.
 296
 297 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 298             Michael Collison <michael.collison@arm.com>
 299
 300         * arm-dis.c (enum mve_instructions): Add new instructions.
 301         (is_mve_encoding_conflict): Handle new instructions.
 302         (is_mve_unpredictable): Likewise.
 303         (print_mve_size): Likewise.
 304         (print_insn_mve): Likewise.
 305
 306 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 307             Michael Collison <michael.collison@arm.com>
 308
 309         * arm-dis.c (enum mve_instructions): Add new instructions.
 310         (enum mve_undefined): Add new reasons.
 311         (is_mve_encoding_conflict): Handle new instructions.
 312         (is_mve_undefined): Likewise.
 313         (is_mve_unpredictable): Likewise.
 314         (print_mve_undefined): Likewise.
 315         (print_mve_size): Likewise.
 316         (print_insn_mve): Likewise.
 317
 318 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 319             Michael Collison <michael.collison@arm.com>
 320
 321         * arm-dis.c (enum mve_instructions): Add new instructions.
 322         (is_mve_encoding_conflict): Handle new instructions.
 323         (is_mve_undefined): Likewise.
 324         (is_mve_unpredictable): Likewise.
 325         (print_mve_size): Likewise.
 326         (print_insn_mve): Likewise.
 327
 328 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 329             Michael Collison <michael.collison@arm.com>
 330
 331         * arm-dis.c (enum mve_instructions): Add new instructions.
 332         (enum mve_unpredictable): Add new reasons.
 333         (enum mve_undefined): Likewise.
 334         (is_mve_okay_in_it): Handle new isntructions.
 335         (is_mve_encoding_conflict): Likewise.
 336         (is_mve_undefined): Likewise.
 337         (is_mve_unpredictable): Likewise.
 338         (print_mve_vmov_index): Likewise.
 339         (print_simd_imm8): Likewise.
 340         (print_mve_undefined): Likewise.
 341         (print_mve_unpredictable): Likewise.
 342         (print_mve_size): Likewise.
 343         (print_insn_mve): Likewise.
 344
 345 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 346             Michael Collison <michael.collison@arm.com>
 347
 348         * arm-dis.c (enum mve_instructions): Add new instructions.
 349         (enum mve_unpredictable): Add new reasons.
 350         (enum mve_undefined): Likewise.
 351         (is_mve_encoding_conflict): Handle new instructions.
 352         (is_mve_undefined): Likewise.
 353         (is_mve_unpredictable): Likewise.
 354         (print_mve_undefined): Likewise.
 355         (print_mve_unpredictable): Likewise.
 356         (print_mve_rounding_mode): Likewise.
 357         (print_mve_vcvt_size): Likewise.
 358         (print_mve_size): Likewise.
 359         (print_insn_mve): Likewise.
 360
 361 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 362             Michael Collison <michael.collison@arm.com>
 363
 364         * arm-dis.c (enum mve_instructions): Add new instructions.
 365         (enum mve_unpredictable): Add new reasons.
 366         (enum mve_undefined): Likewise.
 367         (is_mve_undefined): Handle new instructions.
 368         (is_mve_unpredictable): Likewise.
 369         (print_mve_undefined): Likewise.
 370         (print_mve_unpredictable): Likewise.
 371         (print_mve_size): Likewise.
 372         (print_insn_mve): Likewise.
 373
 374 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 375             Michael Collison <michael.collison@arm.com>
 376
 377         * arm-dis.c (enum mve_instructions): Add new instructions.
 378         (enum mve_undefined): Add new reasons.
 379         (insns): Add new instructions.
 380         (is_mve_encoding_conflict):
 381         (print_mve_vld_str_addr): New print function.
 382         (is_mve_undefined): Handle new instructions.
 383         (is_mve_unpredictable): Likewise.
 384         (print_mve_undefined): Likewise.
 385         (print_mve_size): Likewise.
 386         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 387         (print_insn_mve):  Handle new operands.
 388
 389 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 390             Michael Collison <michael.collison@arm.com>
 391
 392         * arm-dis.c (enum mve_instructions): Add new instructions.
 393         (enum mve_unpredictable): Add new reasons.
 394         (is_mve_encoding_conflict): Handle new instructions.
 395         (is_mve_unpredictable): Likewise.
 396         (mve_opcodes): Add new instructions.
 397         (print_mve_unpredictable): Handle new reasons.
 398         (print_mve_register_blocks): New print function.
 399         (print_mve_size): Handle new instructions.
 400         (print_insn_mve): Likewise.
 401
 402 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 403             Michael Collison <michael.collison@arm.com>
 404
 405         * arm-dis.c (enum mve_instructions): Add new instructions.
 406         (enum mve_unpredictable): Add new reasons.
 407         (enum mve_undefined): Likewise.
 408         (is_mve_encoding_conflict): Handle new instructions.
 409         (is_mve_undefined): Likewise.
 410         (is_mve_unpredictable): Likewise.
 411         (coprocessor_opcodes): Move NEON VDUP from here...
 412         (neon_opcodes): ... to here.
 413         (mve_opcodes): Add new instructions.
 414         (print_mve_undefined):  Handle new reasons.
 415         (print_mve_unpredictable): Likewise.
 416         (print_mve_size): Handle new instructions.
 417         (print_insn_neon): Handle vdup.
 418         (print_insn_mve): Handle new operands.
 419
 420 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 421             Michael Collison <michael.collison@arm.com>
 422
 423         * arm-dis.c (enum mve_instructions): Add new instructions.
 424         (enum mve_unpredictable): Add new values.
 425         (mve_opcodes): Add new instructions.
 426         (vec_condnames): New array with vector conditions.
 427         (mve_predicatenames): New array with predicate suffixes.
 428         (mve_vec_sizename): New array with vector sizes.
 429         (enum vpt_pred_state): New enum with vector predication states.
 430         (struct vpt_block): New struct type for vpt blocks.
 431         (vpt_block_state): Global struct to keep track of state.
 432         (mve_extract_pred_mask): New helper function.
 433         (num_instructions_vpt_block): Likewise.
 434         (mark_outside_vpt_block): Likewise.
 435         (mark_inside_vpt_block): Likewise.
 436         (invert_next_predicate_state): Likewise.
 437         (update_next_predicate_state): Likewise.
 438         (update_vpt_block_state): Likewise.
 439         (is_vpt_instruction): Likewise.
 440         (is_mve_encoding_conflict): Add entries for new instructions.
 441         (is_mve_unpredictable): Likewise.
 442         (print_mve_unpredictable): Handle new cases.
 443         (print_instruction_predicate): Likewise.
 444         (print_mve_size): New function.
 445         (print_vec_condition): New function.
 446         (print_insn_mve): Handle vpt blocks and new print operands.
 447
 448 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 449
 450         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 451         8, 14 and 15 for Armv8.1-M Mainline.
 452
 453 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 454             Michael Collison <michael.collison@arm.com>
 455
 456         * arm-dis.c (enum mve_instructions): New enum.
 457         (enum mve_unpredictable): Likewise.
 458         (enum mve_undefined): Likewise.
 459         (struct mopcode32): New struct.
 460         (is_mve_okay_in_it): New function.
 461         (is_mve_architecture): Likewise.
 462         (arm_decode_field): Likewise.
 463         (arm_decode_field_multiple): Likewise.
 464         (is_mve_encoding_conflict): Likewise.
 465         (is_mve_undefined): Likewise.
 466         (is_mve_unpredictable): Likewise.
 467         (print_mve_undefined): Likewise.
 468         (print_mve_unpredictable): Likewise.
 469         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 470         (print_insn_mve): New function.
 471         (print_insn_thumb32): Handle MVE architecture.
 472         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 473
 474 2019-05-10  Nick Clifton  <nickc@redhat.com>
 475
 476         PR 24538
 477         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 478         end of the table prematurely.
 479
 480 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 481
 482         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 483         macros for R6.
 484
 485 2019-05-11  Alan Modra  <amodra@gmail.com>
 486
 487         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 488         when -Mraw is in effect.
 489
 490 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 491
 492         * aarch64-dis-2.c: Regenerate.
 493         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 494         (OP_SVE_BBB): New variant set.
 495         (OP_SVE_DDDD): New variant set.
 496         (OP_SVE_HHH): New variant set.
 497         (OP_SVE_HHHU): New variant set.
 498         (OP_SVE_SSS): New variant set.
 499         (OP_SVE_SSSU): New variant set.
 500         (OP_SVE_SHH): New variant set.
 501         (OP_SVE_SBBU): New variant set.
 502         (OP_SVE_DSS): New variant set.
 503         (OP_SVE_DHHU): New variant set.
 504         (OP_SVE_VMV_HSD_BHS): New variant set.
 505         (OP_SVE_VVU_HSD_BHS): New variant set.
 506         (OP_SVE_VVVU_SD_BH): New variant set.
 507         (OP_SVE_VVVU_BHSD): New variant set.
 508         (OP_SVE_VVV_QHD_DBS): New variant set.
 509         (OP_SVE_VVV_HSD_BHS): New variant set.
 510         (OP_SVE_VVV_HSD_BHS2): New variant set.
 511         (OP_SVE_VVV_BHS_HSD): New variant set.
 512         (OP_SVE_VV_BHS_HSD): New variant set.
 513         (OP_SVE_VVV_SD): New variant set.
 514         (OP_SVE_VVU_BHS_HSD): New variant set.
 515         (OP_SVE_VZVV_SD): New variant set.
 516         (OP_SVE_VZVV_BH): New variant set.
 517         (OP_SVE_VZV_SD): New variant set.
 518         (aarch64_opcode_table): Add sve2 instructions.
 519
 520 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 521
 522         * aarch64-asm-2.c: Regenerated.
 523         * aarch64-dis-2.c: Regenerated.
 524         * aarch64-opc-2.c: Regenerated.
 525         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 526         for SVE_SHLIMM_UNPRED_22.
 527         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 528         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 529         operand.
 530
 531 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 532
 533         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 534         sve_size_tsz_bhs iclass encode.
 535         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 536         sve_size_tsz_bhs iclass decode.
 537
 538 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 539
 540         * aarch64-asm-2.c: Regenerated.
 541         * aarch64-dis-2.c: Regenerated.
 542         * aarch64-opc-2.c: Regenerated.
 543         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 544         for SVE_Zm4_11_INDEX.
 545         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 546         (fields): Handle SVE_i2h field.
 547         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 548         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 549
 550 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 551
 552         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 553         sve_shift_tsz_bhsd iclass encode.
 554         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 555         sve_shift_tsz_bhsd iclass decode.
 556
 557 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 558
 559         * aarch64-asm-2.c: Regenerated.
 560         * aarch64-dis-2.c: Regenerated.
 561         * aarch64-opc-2.c: Regenerated.
 562         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 563         (aarch64_encode_variant_using_iclass): Handle
 564         sve_shift_tsz_hsd iclass encode.
 565         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 566         sve_shift_tsz_hsd iclass decode.
 567         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 568         for SVE_SHRIMM_UNPRED_22.
 569         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 570         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 571         operand.
 572
 573 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 574
 575         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 576         sve_size_013 iclass encode.
 577         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 578         sve_size_013 iclass decode.
 579
 580 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 581
 582         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 583         sve_size_bh iclass encode.
 584         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 585         sve_size_bh iclass decode.
 586
 587 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 588
 589         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 590         sve_size_sd2 iclass encode.
 591         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 592         sve_size_sd2 iclass decode.
 593         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 594         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 595
 596 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 597
 598         * aarch64-asm-2.c: Regenerated.
 599         * aarch64-dis-2.c: Regenerated.
 600         * aarch64-opc-2.c: Regenerated.
 601         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 602         for SVE_ADDR_ZX.
 603         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 604         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 605
 606 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 607
 608         * aarch64-asm-2.c: Regenerated.
 609         * aarch64-dis-2.c: Regenerated.
 610         * aarch64-opc-2.c: Regenerated.
 611         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 612         for SVE_Zm3_11_INDEX.
 613         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 614         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 615         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 616         fields.
 617         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 618
 619 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 620
 621         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 622         sve_size_hsd2 iclass encode.
 623         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 624         sve_size_hsd2 iclass decode.
 625         * aarch64-opc.c (fields): Handle SVE_size field.
 626         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 627
 628 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 629
 630         * aarch64-asm-2.c: Regenerated.
 631         * aarch64-dis-2.c: Regenerated.
 632         * aarch64-opc-2.c: Regenerated.
 633         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 634         for SVE_IMM_ROT3.
 635         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 636         (fields): Handle SVE_rot3 field.
 637         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 638         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 639
 640 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 641
 642         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 643         instructions.
 644
 645 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 646
 647         * aarch64-tbl.h
 648         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 649         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 650         aarch64_feature_sve2bitperm): New feature sets.
 651         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 652         for feature set addresses.
 653         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 654         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 655
 656 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 657             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 658
 659         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 660         argument and set ASE_EVA_R6 appropriately.
 661         (set_default_mips_dis_options): Pass ISA to above.
 662         (parse_mips_dis_option): Likewise.
 663         * mips-opc.c (EVAR6): New macro.
 664         (mips_builtin_opcodes): Add llwpe, scwpe.
 665
 666 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 667
 668         * aarch64-asm-2.c: Regenerated.
 669         * aarch64-dis-2.c: Regenerated.
 670         * aarch64-opc-2.c: Regenerated.
 671         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 672         AARCH64_OPND_TME_UIMM16.
 673         (aarch64_print_operand): Likewise.
 674         * aarch64-tbl.h (QL_IMM_NIL): New.
 675         (TME): New.
 676         (_TME_INSN): New.
 677         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 678
 679 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 680
 681         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 682
 683 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 684             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 685
 686         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 687
 688 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 689
 690         * s12z-opc.h: Add extern "C" bracketing to help
 691         users who wish to use this interface in c++ code.
 692
 693 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 694
 695         * s12z-opc.c (bm_decode): Handle bit map operations with the
 696         "reserved0" mode.
 697
 698 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 699
 700         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 701         specifier.  Add entries for VLDR and VSTR of system registers.
 702         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 703         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 704         of %J and %K format specifier.
 705
 706 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 707
 708         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 709         Add new entries for VSCCLRM instruction.
 710         (print_insn_coprocessor): Handle new %C format control code.
 711
 712 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 713
 714         * arm-dis.c (enum isa): New enum.
 715         (struct sopcode32): New structure.
 716         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 717         set isa field of all current entries to ANY.
 718         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 719         Only match an entry if its isa field allows the current mode.
 720
 721 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 722
 723         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 724         CLRM.
 725         (print_insn_thumb32): Add logic to print %n CLRM register list.
 726
 727 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 728
 729         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 730         and %Q patterns.
 731
 732 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 733
 734         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 735         (print_insn_thumb32): Edit the switch case for %Z.
 736
 737 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 738
 739         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 740
 741 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 742
 743         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 744
 745 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 746
 747         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 748
 749 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 750
 751         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 752         Arm register with r13 and r15 unpredictable.
 753         (thumb32_opcodes): New instructions for bfx and bflx.
 754
 755 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 756
 757         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 758
 759 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 760
 761         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 762
 763 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 764
 765         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 766
 767 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 768
 769         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 770
 771 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 772
 773         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 774         "optr". ("operator" is a reserved word in c++).
 775
 776 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 777
 778         * aarch64-opc.c (aarch64_print_operand): Add case for
 779         AARCH64_OPND_Rt_SP.
 780         (verify_constraints): Likewise.
 781         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 782         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 783         to accept Rt|SP as first operand.
 784         (AARCH64_OPERANDS): Add new Rt_SP.
 785         * aarch64-asm-2.c: Regenerated.
 786         * aarch64-dis-2.c: Regenerated.
 787         * aarch64-opc-2.c: Regenerated.
 788
 789 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 790
 791         * aarch64-asm-2.c: Regenerated.
 792         * aarch64-dis-2.c: Likewise.
 793         * aarch64-opc-2.c: Likewise.
 794         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 795
 796 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 797
 798         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 799
 800 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 801
 802         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 803         * i386-init.h: Regenerated.
 804
 805 2019-04-07  Alan Modra  <amodra@gmail.com>
 806
 807         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 808         op_separator to control printing of spaces, comma and parens
 809         rather than need_comma, need_paren and spaces vars.
 810
 811 2019-04-07  Alan Modra  <amodra@gmail.com>
 812
 813         PR 24421
 814         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 815         (print_insn_neon, print_insn_arm): Likewise.
 816
 817 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 818
 819         * i386-dis-evex.h (evex_table): Updated to support BF16
 820         instructions.
 821         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 822         and EVEX_W_0F3872_P_3.
 823         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 824         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 825         * i386-opc.h (enum): Add CpuAVX512_BF16.
 826         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 827         * i386-opc.tbl: Add AVX512 BF16 instructions.
 828         * i386-init.h: Regenerated.
 829         * i386-tbl.h: Likewise.
 830
 831 2019-04-05  Alan Modra  <amodra@gmail.com>
 832
 833         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 834         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 835         to favour printing of "-" branch hint when using the "y" bit.
 836         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 837
 838 2019-04-05  Alan Modra  <amodra@gmail.com>
 839
 840         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 841         opcode until first operand is output.
 842
 843 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 844
 845         PR gas/24349
 846         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 847         (valid_bo_post_v2): Add support for 'at' branch hints.
 848         (insert_bo): Only error on branch on ctr.
 849         (get_bo_hint_mask): New function.
 850         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 851         for inserting 'at' branch hints.
 852         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 853         for extracting 'at' branch hints.
 854         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 855         (BOE): Delete operand.
 856         (BOM, BOP): New operands.
 857         (RM): Update value.
 858         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 859         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 860         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 861         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 862         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 863         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 864         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 865         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 866         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 867         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 868         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 869         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 870         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 871         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 872         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 873         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 874         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 875         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 876         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 877         bttarl+>: New extended mnemonics.
 878
 879 2019-03-28  Alan Modra  <amodra@gmail.com>
 880
 881         PR 24390
 882         * ppc-opc.c (BTF): Define.
 883         (powerpc_opcodes): Use for mtfsb*.
 884         * ppc-dis.c (print_insn_powerpc): Print fields with both
 885         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 886
 887 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 888
 889         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 890         (mapping_symbol_for_insn): Implement new algorithm.
 891         (print_insn): Remove duplicate code.
 892
 893 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 894
 895         * aarch64-dis.c (print_insn_aarch64):
 896         Implement override.
 897
 898 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 899
 900         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 901         order.
 902
 903 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 904
 905         * aarch64-dis.c (last_stop_offset): New.
 906         (print_insn_aarch64): Use stop_offset.
 907
 908 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 909
 910         PR gas/24359
 911         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 912         CPU_ANY_AVX2_FLAGS.
 913         * i386-init.h: Regenerated.
 914
 915 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 916
 917         PR gas/24348
 918         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 919         vmovdqu16, vmovdqu32 and vmovdqu64.
 920         * i386-tbl.h: Regenerated.
 921
 922 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 923
 924         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 925         from vstrszb, vstrszh, and vstrszf.
 926
 927 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 928
 929         * s390-opc.txt: Add instruction descriptions.
 930
 931 2019-02-08  Jim Wilson  <jimw@sifive.com>
 932
 933         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 934         <bne>: Likewise.
 935
 936 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 937
 938         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 939
 940 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 941
 942         PR binutils/23212
 943         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 944         * aarch64-opc.c (verify_elem_sd): New.
 945         (fields): Add FLD_sz entr.
 946         * aarch64-tbl.h (_SIMD_INSN): New.
 947         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 948         fmulx scalar and vector by element isns.
 949
 950 2019-02-07  Nick Clifton  <nickc@redhat.com>
 951
 952         * po/sv.po: Updated Swedish translation.
 953
 954 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 955
 956         * s390-mkopc.c (main): Accept arch13 as cpu string.
 957         * s390-opc.c: Add new instruction formats and instruction opcode
 958         masks.
 959         * s390-opc.txt: Add new arch13 instructions.
 960
 961 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 962
 963         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 964         (aarch64_opcode): Change encoding for stg, stzg
 965         st2g and st2zg.
 966         * aarch64-asm-2.c: Regenerated.
 967         * aarch64-dis-2.c: Regenerated.
 968         * aarch64-opc-2.c: Regenerated.
 969
 970 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 971
 972         * aarch64-asm-2.c: Regenerated.
 973         * aarch64-dis-2.c: Likewise.
 974         * aarch64-opc-2.c: Likewise.
 975         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 976
 977 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 978             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 979
 980         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 981         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 982         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 983         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 984         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 985         case for ldstgv_indexed.
 986         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 987         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 988         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 989         * aarch64-asm-2.c: Regenerated.
 990         * aarch64-dis-2.c: Regenerated.
 991         * aarch64-opc-2.c: Regenerated.
 992
 993 2019-01-23  Nick Clifton  <nickc@redhat.com>
 994
 995         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 996
 997 2019-01-21  Nick Clifton  <nickc@redhat.com>
 998
 999         * po/de.po: Updated German translation.
1000         * po/uk.po: Updated Ukranian translation.
1001
1002 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1003         * mips-dis.c (mips_arch_choices): Fix typo in
1004         gs464, gs464e and gs264e descriptors.
1005
1006 2019-01-19  Nick Clifton  <nickc@redhat.com>
1007
1008         * configure: Regenerate.
1009         * po/opcodes.pot: Regenerate.
1010
1011 2018-06-24  Nick Clifton  <nickc@redhat.com>
1012
1013         2.32 branch created.
1014
1015 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1016
1017         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1018         if it is null.
1019         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1020         zero.
1021
1022 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1023
1024         * configure: Regenerate.
1025
1026 2019-01-07  Alan Modra  <amodra@gmail.com>
1027
1028         * configure: Regenerate.
1029         * po/POTFILES.in: Regenerate.
1030
1031 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1032
1033         * s12z-opc.c: New file.
1034         * s12z-opc.h: New file.
1035         * s12z-dis.c: Removed all code not directly related to display
1036         of instructions.  Used the interface provided by the new files
1037         instead.
1038         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1039         * Makefile.in: Regenerate.
1040         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1041         * configure: Regenerate.
1042
1043 2019-01-01  Alan Modra  <amodra@gmail.com>
1044
1045         Update year range in copyright notice of all files.
1046
1047 For older changes see ChangeLog-2018
1048 \f
1049 Copyright (C) 2019 Free Software Foundation, Inc.
1050
1051 Copying and distribution of this file, with or without modification,
1052 are permitted in any medium without royalty provided the copyright
1053 notice and this notice are preserved.
1054
1055 Local Variables:
1056 mode: change-log
1057 left-margin: 8
1058 fill-column: 74
1059 version-control: never
1060 End: