opcodes/ChangeLog

   1 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
   2
   3         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
   4         * arc-opc.c (insert_r13el): New function.
   5         (R13_EL): Define.
   6         * arc-tbl.h: Add new enter/leave variants.
   7
   8 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
   9
  10         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
  11
  12 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
  13
  14         * mips-dis.c (print_mips_disassembler_options): Add
  15         `no-aliases'.
  16
  17 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
  18
  19         * mips16-opc.c (AL): New macro.
  20         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
  21         of "ld" and "lw" as aliases.
  22
  23 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
  24
  25         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
  26         arguments.
  27
  28 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
  29             Alan Modra  <amodra@gmail.com>
  30
  31         * ppc-opc.c (ELEV): Define.
  32         (vle_opcodes): Add se_rfgi and e_sc.
  33         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
  34         for E200Z4.
  35
  36 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
  37
  38         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
  39
  40 2017-04-21  Nick Clifton  <nickc@redhat.com>
  41
  42         PR binutils/21380
  43         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
  44         LD3R and LD4R.
  45
  46 2017-04-13  Alan Modra  <amodra@gmail.com>
  47
  48         * epiphany-desc.c: Regenerate.
  49         * fr30-desc.c: Regenerate.
  50         * frv-desc.c: Regenerate.
  51         * ip2k-desc.c: Regenerate.
  52         * iq2000-desc.c: Regenerate.
  53         * lm32-desc.c: Regenerate.
  54         * m32c-desc.c: Regenerate.
  55         * m32r-desc.c: Regenerate.
  56         * mep-desc.c: Regenerate.
  57         * mt-desc.c: Regenerate.
  58         * or1k-desc.c: Regenerate.
  59         * xc16x-desc.c: Regenerate.
  60         * xstormy16-desc.c: Regenerate.
  61
  62 2017-04-11  Alan Modra  <amodra@gmail.com>
  63
  64         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
  65         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
  66         PPC_OPCODE_TMR for e6500.
  67         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
  68         (PPCVEC3): Define as PPC_OPCODE_POWER9.
  69         (PPCVSX2): Define as PPC_OPCODE_POWER8.
  70         (PPCVSX3): Define as PPC_OPCODE_POWER9.
  71         (PPCHTM): Define as PPC_OPCODE_POWER8.
  72         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
  73
  74 2017-04-10  Alan Modra  <amodra@gmail.com>
  75
  76         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
  77         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
  78         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
  79         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
  80
  81 2017-04-09  Pip Cet  <pipcet@gmail.com>
  82
  83         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
  84         appropriate floating-point precision directly.
  85
  86 2017-04-07  Alan Modra  <amodra@gmail.com>
  87
  88         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
  89         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
  90         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
  91         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
  92         vector instructions with E6500 not PPCVEC2.
  93
  94 2017-04-06  Pip Cet  <pipcet@gmail.com>
  95
  96         * Makefile.am: Add wasm32-dis.c.
  97         * configure.ac: Add wasm32-dis.c to wasm32 target.
  98         * disassemble.c: Add wasm32 disassembler code.
  99         * wasm32-dis.c: New file.
 100         * Makefile.in: Regenerate.
 101         * configure: Regenerate.
 102         * po/POTFILES.in: Regenerate.
 103         * po/opcodes.pot: Regenerate.
 104
 105 2017-04-05  Pedro Alves  <palves@redhat.com>
 106
 107         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 108         * arm-dis.c (parse_arm_disassembler_options): Constify.
 109         * ppc-dis.c (powerpc_init_dialect): Constify local.
 110         * vax-dis.c (parse_disassembler_options): Constify.
 111
 112 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 113
 114         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 115         RISCV_GP_SYMBOL.
 116
 117 2017-03-30  Pip Cet  <pipcet@gmail.com>
 118
 119         * configure.ac: Add (empty) bfd_wasm32_arch target.
 120         * configure: Regenerate
 121         * po/opcodes.pot: Regenerate.
 122
 123 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 124
 125         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 126         OSA2015.
 127         * opcodes/sparc-opc.c (asi_table): New ASIs.
 128
 129 2017-03-29  Alan Modra  <amodra@gmail.com>
 130
 131         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 132         "raw" option.
 133         (lookup_powerpc): Don't special case -1 dialect.  Handle
 134         PPC_OPCODE_RAW.
 135         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 136         lookup_powerpc call, pass it on second.
 137
 138 2017-03-27  Alan Modra  <amodra@gmail.com>
 139
 140         PR 21303
 141         * ppc-dis.c (struct ppc_mopt): Comment.
 142         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 143
 144 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 145
 146         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 147         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 148         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 149         (insert_nps_misc_imm_offset): New function.
 150         (extract_nps_misc imm_offset): New function.
 151         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 152         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 153
 154 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 155
 156         * s390-mkopc.c (main): Remove vx2 check.
 157         * s390-opc.txt: Remove vx2 instruction flags.
 158
 159 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 160
 161         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 162         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 163         (insert_nps_imm_offset): New function.
 164         (extract_nps_imm_offset): New function.
 165         (insert_nps_imm_entry): New function.
 166         (extract_nps_imm_entry): New function.
 167
 168 2017-03-17  Alan Modra  <amodra@gmail.com>
 169
 170         PR 21248
 171         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 172         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 173         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 174
 175 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 176
 177         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 178         <c.andi>: Likewise.
 179         <c.addiw> Likewise.
 180
 181 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 182
 183         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 184
 185 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 186
 187         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 188         <srl> Likewise.
 189         <srai> Likewise.
 190         <sra> Likewise.
 191
 192 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 193
 194         * i386-gen.c (opcode_modifiers): Replace S with Load.
 195         * i386-opc.h (S): Removed.
 196         (Load): New.
 197         (i386_opcode_modifier): Replace s with load.
 198         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 199         and {evex}.  Replace S with Load.
 200         * i386-tbl.h: Regenerated.
 201
 202 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 203
 204         * i386-opc.tbl: Use CpuCET on rdsspq.
 205         * i386-tbl.h: Regenerated.
 206
 207 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 208
 209         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 210         <vsx>: Do not use PPC_OPCODE_VSX3;
 211
 212 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 213
 214         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 215
 216 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 217
 218         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 219         (MOD_0F1E_PREFIX_1): Likewise.
 220         (MOD_0F38F5_PREFIX_2): Likewise.
 221         (MOD_0F38F6_PREFIX_0): Likewise.
 222         (RM_0F1E_MOD_3_REG_7): Likewise.
 223         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 224         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 225         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 226         (PREFIX_0F1E): Likewise.
 227         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 228         (PREFIX_0F38F5): Likewise.
 229         (dis386_twobyte): Use PREFIX_0F1E.
 230         (reg_table): Add REG_0F1E_MOD_3.
 231         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 232         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 233         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 234         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 235         (three_byte_table): Use PREFIX_0F38F5.
 236         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 237         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 238         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 239         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 240         PREFIX_MOD_3_0F01_REG_5_RM_2.
 241         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 242         (cpu_flags): Add CpuCET.
 243         * i386-opc.h (CpuCET): New enum.
 244         (CpuUnused): Commented out.
 245         (i386_cpu_flags): Add cpucet.
 246         * i386-opc.tbl: Add Intel CET instructions.
 247         * i386-init.h: Regenerated.
 248         * i386-tbl.h: Likewise.
 249
 250 2017-03-06  Alan Modra  <amodra@gmail.com>
 251
 252         PR 21124
 253         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 254         (extract_raq, extract_ras, extract_rbx): New functions.
 255         (powerpc_operands): Use opposite corresponding insert function.
 256         (Q_MASK): Define.
 257         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 258         register restriction.
 259
 260 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 261
 262         * disassemble.c Include "safe-ctype.h".
 263         (disassemble_init_for_target): Handle s390 init.
 264         (remove_whitespace_and_extra_commas): New function.
 265         (disassembler_options_cmp): Likewise.
 266         * arm-dis.c: Include "libiberty.h".
 267         (NUM_ELEM): Delete.
 268         (regnames): Use long disassembler style names.
 269         Add force-thumb and no-force-thumb options.
 270         (NUM_ARM_REGNAMES): Rename from this...
 271         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 272         (get_arm_regname_num_options): Delete.
 273         (set_arm_regname_option): Likewise.
 274         (get_arm_regnames): Likewise.
 275         (parse_disassembler_options): Likewise.
 276         (parse_arm_disassembler_option): Rename from this...
 277         (parse_arm_disassembler_options): ...to this.  Make static.
 278         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 279         (print_insn): Use parse_arm_disassembler_options.
 280         (disassembler_options_arm): New function.
 281         (print_arm_disassembler_options): Handle updated regnames.
 282         * ppc-dis.c: Include "libiberty.h".
 283         (ppc_opts): Add "32" and "64" entries.
 284         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 285         (powerpc_init_dialect): Add break to switch statement.
 286         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 287         (disassembler_options_powerpc): New function.
 288         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 289         Remove printing of "32" and "64".
 290         * s390-dis.c: Include "libiberty.h".
 291         (init_flag): Remove unneeded variable.
 292         (struct s390_options_t): New structure type.
 293         (options): New structure.
 294         (init_disasm): Rename from this...
 295         (disassemble_init_s390): ...to this.  Add initializations for
 296         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 297         (print_insn_s390): Delete call to init_disasm.
 298         (disassembler_options_s390): New function.
 299         (print_s390_disassembler_options): Print using information from
 300         struct 'options'.
 301         * po/opcodes.pot: Regenerate.
 302
 303 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 304
 305         * i386-dis.c (PCMPESTR_Fixup): New.
 306         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 307         (prefix_table): Use PCMPESTR_Fixup.
 308         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 309         PCMPESTR_Fixup.
 310         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 311         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 312         Split 64-bit and non-64-bit variants.
 313         * opcodes/i386-tbl.h: Re-generate.
 314
 315 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 316
 317         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 318         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 319         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 320         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 321         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 322         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 323         (OP_SVE_V_HSD): New macros.
 324         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 325         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 326         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 327         (aarch64_opcode_table): Add new SVE instructions.
 328         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 329         for rotation operands.  Add new SVE operands.
 330         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 331         (ins_sve_quad_index): Likewise.
 332         (ins_imm_rotate): Split into...
 333         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 334         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 335         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 336         functions.
 337         (aarch64_ins_sve_addr_ri_s4): New function.
 338         (aarch64_ins_sve_quad_index): Likewise.
 339         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 340         * aarch64-asm-2.c: Regenerate.
 341         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 342         (ext_sve_quad_index): Likewise.
 343         (ext_imm_rotate): Split into...
 344         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 345         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 346         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 347         functions.
 348         (aarch64_ext_sve_addr_ri_s4): New function.
 349         (aarch64_ext_sve_quad_index): Likewise.
 350         (aarch64_ext_sve_index): Allow quad indices.
 351         (do_misc_decoding): Likewise.
 352         * aarch64-dis-2.c: Regenerate.
 353         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 354         aarch64_field_kinds.
 355         (OPD_F_OD_MASK): Widen by one bit.
 356         (OPD_F_NO_ZR): Bump accordingly.
 357         (get_operand_field_width): New function.
 358         * aarch64-opc.c (fields): Add new SVE fields.
 359         (operand_general_constraint_met_p): Handle new SVE operands.
 360         (aarch64_print_operand): Likewise.
 361         * aarch64-opc-2.c: Regenerate.
 362
 363 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 364
 365         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 366         (aarch64_feature_compnum): ...this.
 367         (SIMD_V8_3): Replace with...
 368         (COMPNUM): ...this.
 369         (CNUM_INSN): New macro.
 370         (aarch64_opcode_table): Use it for the complex number instructions.
 371
 372 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 373
 374         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 375
 376 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 377
 378         Add support for associating SPARC ASIs with an architecture level.
 379         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 380         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 381         decoding of SPARC ASIs.
 382
 383 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 384
 385         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 386         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 387
 388 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 389
 390         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 391         1 (instead of to itself). Correct typo.
 392
 393 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 394
 395         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 396         pseudoinstructions.
 397
 398 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 399
 400         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 401         (aarch64_sys_reg_supported_p): Handle them.
 402
 403 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 404
 405         * arc-opc.c (UIMM6_20R): Define.
 406         (SIMM12_20): Use above.
 407         (SIMM12_20R): Define.
 408         (SIMM3_5_S): Use above.
 409         (UIMM7_A32_11R_S): Define.
 410         (UIMM7_9_S): Use above.
 411         (UIMM3_13R_S): Define.
 412         (SIMM11_A32_7_S): Use above.
 413         (SIMM9_8R): Define.
 414         (UIMM10_A32_8_S): Use above.
 415         (UIMM8_8R_S): Define.
 416         (W6): Use above.
 417         (arc_relax_opcodes): Use all above defines.
 418
 419 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 420
 421         * arc-regs.h: Distinguish some of the registers different on
 422         ARC700 and HS38 cpus.
 423
 424 2017-02-14  Alan Modra  <amodra@gmail.com>
 425
 426         PR 21118
 427         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 428         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 429
 430 2017-02-11  Stafford Horne  <shorne@gmail.com>
 431             Alan Modra  <amodra@gmail.com>
 432
 433         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 434         Use insn_bytes_value and insn_int_value directly instead.  Don't
 435         free allocated memory until function exit.
 436
 437 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 438
 439         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 440
 441 2017-02-03  Nick Clifton  <nickc@redhat.com>
 442
 443         PR 21096
 444         * aarch64-opc.c (print_register_list): Ensure that the register
 445         list index will fir into the tb buffer.
 446         (print_register_offset_address): Likewise.
 447         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 448
 449 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 450
 451         PR 21056
 452         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 453         instructions when the previous fetch packet ends with a 32-bit
 454         instruction.
 455
 456 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 457
 458         * pru-opc.c: Remove vague reference to a future GDB port.
 459
 460 2017-01-20  Nick Clifton  <nickc@redhat.com>
 461
 462         * po/ga.po: Updated Irish translation.
 463
 464 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 465
 466         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 467
 468 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 469
 470         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 471         if FETCH_DATA returns 0.
 472         (m68k_scan_mask): Likewise.
 473         (print_insn_m68k): Update code to handle -1 return value.
 474
 475 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 476
 477         * m68k-dis.c (enum print_insn_arg_error): New.
 478         (NEXTBYTE): Replace -3 with
 479         PRINT_INSN_ARG_MEMORY_ERROR.
 480         (NEXTULONG): Likewise.
 481         (NEXTSINGLE): Likewise.
 482         (NEXTDOUBLE): Likewise.
 483         (NEXTDOUBLE): Likewise.
 484         (NEXTPACKED): Likewise.
 485         (FETCH_ARG): Likewise.
 486         (FETCH_DATA): Update comments.
 487         (print_insn_arg): Update comments. Replace magic numbers with
 488         enum.
 489         (match_insn_m68k): Likewise.
 490
 491 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 492
 493         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 494         * i386-dis-evex.h (evex_table): Updated.
 495         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 496         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 497         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 498         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 499         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 500         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 501         * i386-init.h: Regenerate.
 502         * i386-tbl.h: Ditto.
 503
 504 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 505
 506         * msp430-dis.c (msp430_singleoperand): Return -1 if
 507         msp430dis_opcode_signed returns false.
 508         (msp430_doubleoperand): Likewise.
 509         (msp430_branchinstr): Return -1 if
 510         msp430dis_opcode_unsigned returns false.
 511         (msp430x_calla_instr): Likewise.
 512         (print_insn_msp430): Likewise.
 513
 514 2017-01-05  Nick Clifton  <nickc@redhat.com>
 515
 516         PR 20946
 517         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 518         could not be matched.
 519         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 520         NULL.
 521
 522 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 523
 524         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 525         (aarch64_opcode_table): Use RCPC_INSN.
 526
 527 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 528
 529         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 530         extension.
 531         * riscv-opcodes/all-opcodes: Likewise.
 532
 533 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 534
 535         * riscv-dis.c (print_insn_args): Add fall through comment.
 536
 537 2017-01-03  Nick Clifton  <nickc@redhat.com>
 538
 539         * po/sr.po: New Serbian translation.
 540         * configure.ac (ALL_LINGUAS): Add sr.
 541         * configure: Regenerate.
 542
 543 2017-01-02  Alan Modra  <amodra@gmail.com>
 544
 545         * epiphany-desc.h: Regenerate.
 546         * epiphany-opc.h: Regenerate.
 547         * fr30-desc.h: Regenerate.
 548         * fr30-opc.h: Regenerate.
 549         * frv-desc.h: Regenerate.
 550         * frv-opc.h: Regenerate.
 551         * ip2k-desc.h: Regenerate.
 552         * ip2k-opc.h: Regenerate.
 553         * iq2000-desc.h: Regenerate.
 554         * iq2000-opc.h: Regenerate.
 555         * lm32-desc.h: Regenerate.
 556         * lm32-opc.h: Regenerate.
 557         * m32c-desc.h: Regenerate.
 558         * m32c-opc.h: Regenerate.
 559         * m32r-desc.h: Regenerate.
 560         * m32r-opc.h: Regenerate.
 561         * mep-desc.h: Regenerate.
 562         * mep-opc.h: Regenerate.
 563         * mt-desc.h: Regenerate.
 564         * mt-opc.h: Regenerate.
 565         * or1k-desc.h: Regenerate.
 566         * or1k-opc.h: Regenerate.
 567         * xc16x-desc.h: Regenerate.
 568         * xc16x-opc.h: Regenerate.
 569         * xstormy16-desc.h: Regenerate.
 570         * xstormy16-opc.h: Regenerate.
 571
 572 2017-01-02  Alan Modra  <amodra@gmail.com>
 573
 574         Update year range in copyright notice of all files.
 575
 576 For older changes see ChangeLog-2016
 577 \f
 578 Copyright (C) 2017 Free Software Foundation, Inc.
 579
 580 Copying and distribution of this file, with or without modification,
 581 are permitted in any medium without royalty provided the copyright
 582 notice and this notice are preserved.
 583
 584 Local Variables:
 585 mode: change-log
 586 left-margin: 8
 587 fill-column: 74
 588 version-control: never
 589 End: