1 2020-03-06 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
4 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
5 register and memory source templates. Replace VexW= by VexW*
7 * i386-tbl.h: Re-generate.
9 2020-03-06 Jan Beulich <jbeulich@suse.com>
11 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
12 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
13 * i386-tbl.h: Re-generate.
15 2020-03-06 Jan Beulich <jbeulich@suse.com>
17 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
18 * i386-tbl.h: Re-generate.
20 2020-03-06 Jan Beulich <jbeulich@suse.com>
22 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
23 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
24 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
25 VexW0 on SSE2AVX variants.
26 (vmovq): Drop NoRex64 from XMM/XMM variants.
27 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
28 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
30 * i386-tbl.h: Re-generate.
32 2020-03-06 Jan Beulich <jbeulich@suse.com>
34 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
35 * i386-opc.h (Rex64): Delete.
36 (struct i386_opcode_modifier): Remove rex64 field.
37 * i386-opc.tbl (crc32): Drop Rex64.
38 Replace Rex64 with Size64 everywhere else.
39 * i386-tbl.h: Re-generate.
41 2020-03-06 Jan Beulich <jbeulich@suse.com>
43 * i386-dis.c (OP_E_memory): Exclude recording of used address
44 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
45 addressed memory operands for MPX insns.
47 2020-03-06 Jan Beulich <jbeulich@suse.com>
49 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
50 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
51 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
52 (ptwrite): Split into non-64-bit and 64-bit forms.
53 * i386-tbl.h: Re-generate.
55 2020-03-06 Jan Beulich <jbeulich@suse.com>
57 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
59 * i386-tbl.h: Re-generate.
61 2020-03-04 Jan Beulich <jbeulich@suse.com>
63 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
64 (prefix_table): Move vmmcall here. Add vmgexit.
65 (rm_table): Replace vmmcall entry by prefix_table[] escape.
66 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
67 (cpu_flags): Add CpuSEV_ES entry.
68 * i386-opc.h (CpuSEV_ES): New.
69 (union i386_cpu_flags): Add cpusev_es field.
70 * i386-opc.tbl (vmgexit): New.
71 * i386-init.h, i386-tbl.h: Re-generate.
73 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
75 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
77 * i386-opc.h (IGNORESIZE): New.
78 (DEFAULTSIZE): Likewise.
79 (IgnoreSize): Removed.
80 (DefaultSize): Likewise.
82 (i386_opcode_modifier): Replace ignoresize/defaultsize with
84 * i386-opc.tbl (IgnoreSize): New.
85 (DefaultSize): Likewise.
86 * i386-tbl.h: Regenerated.
88 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
91 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
94 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
97 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
98 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
99 * i386-tbl.h: Regenerated.
101 2020-02-26 Alan Modra <amodra@gmail.com>
103 * aarch64-asm.c: Indent labels correctly.
104 * aarch64-dis.c: Likewise.
105 * aarch64-gen.c: Likewise.
106 * aarch64-opc.c: Likewise.
107 * alpha-dis.c: Likewise.
108 * i386-dis.c: Likewise.
109 * nds32-asm.c: Likewise.
110 * nfp-dis.c: Likewise.
111 * visium-dis.c: Likewise.
113 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
115 * arc-regs.h (int_vector_base): Make it available for all ARC
118 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
120 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
123 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
125 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
126 c.mv/c.li if rs1 is zero.
128 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
130 * i386-gen.c (cpu_flag_init): Replace CpuABM with
131 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
133 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
134 * i386-opc.h (CpuABM): Removed.
136 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
137 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
138 popcnt. Remove CpuABM from lzcnt.
139 * i386-init.h: Regenerated.
140 * i386-tbl.h: Likewise.
142 2020-02-17 Jan Beulich <jbeulich@suse.com>
144 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
145 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
146 VexW1 instead of open-coding them.
147 * i386-tbl.h: Re-generate.
149 2020-02-17 Jan Beulich <jbeulich@suse.com>
151 * i386-opc.tbl (AddrPrefixOpReg): Define.
152 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
153 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
154 templates. Drop NoRex64.
155 * i386-tbl.h: Re-generate.
157 2020-02-17 Jan Beulich <jbeulich@suse.com>
160 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
161 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
162 into Intel syntax instance (with Unpsecified) and AT&T one
164 (vcvtneps2bf16): Likewise, along with folding the two so far
166 * i386-tbl.h: Re-generate.
168 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
170 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
173 2020-02-17 Alan Modra <amodra@gmail.com>
175 * i386-gen.c (cpu_flag_init): Correct last change.
177 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
179 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
182 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
184 * i386-opc.tbl (movsx): Remove Intel syntax comments.
187 2020-02-14 Jan Beulich <jbeulich@suse.com>
190 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
191 destination for Cpu64-only variant.
192 (movzx): Fold patterns.
193 * i386-tbl.h: Re-generate.
195 2020-02-13 Jan Beulich <jbeulich@suse.com>
197 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
198 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
199 CPU_ANY_SSE4_FLAGS entry.
200 * i386-init.h: Re-generate.
202 2020-02-12 Jan Beulich <jbeulich@suse.com>
204 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
205 with Unspecified, making the present one AT&T syntax only.
206 * i386-tbl.h: Re-generate.
208 2020-02-12 Jan Beulich <jbeulich@suse.com>
210 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
211 * i386-tbl.h: Re-generate.
213 2020-02-12 Jan Beulich <jbeulich@suse.com>
216 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
217 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
218 Amd64 and Intel64 templates.
219 (call, jmp): Likewise for far indirect variants. Dro
221 * i386-tbl.h: Re-generate.
223 2020-02-11 Jan Beulich <jbeulich@suse.com>
225 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
226 * i386-opc.h (ShortForm): Delete.
227 (struct i386_opcode_modifier): Remove shortform field.
228 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
229 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
230 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
231 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
233 * i386-tbl.h: Re-generate.
235 2020-02-11 Jan Beulich <jbeulich@suse.com>
237 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
238 fucompi): Drop ShortForm from operand-less templates.
239 * i386-tbl.h: Re-generate.
241 2020-02-11 Alan Modra <amodra@gmail.com>
243 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
244 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
245 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
246 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
247 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
249 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
251 * arm-dis.c (print_insn_cde): Define 'V' parse character.
252 (cde_opcodes): Add VCX* instructions.
254 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
255 Matthew Malcomson <matthew.malcomson@arm.com>
257 * arm-dis.c (struct cdeopcode32): New.
258 (CDE_OPCODE): New macro.
259 (cde_opcodes): New disassembly table.
260 (regnames): New option to table.
261 (cde_coprocs): New global variable.
262 (print_insn_cde): New
263 (print_insn_thumb32): Use print_insn_cde.
264 (parse_arm_disassembler_options): Parse coprocN args.
266 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
269 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
271 * i386-opc.h (AMD64): Removed.
275 (INTEL64ONLY): Likewise.
276 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
277 * i386-opc.tbl (Amd64): New.
279 (Intel64Only): Likewise.
280 Replace AMD64 with Amd64. Update sysenter/sysenter with
281 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
282 * i386-tbl.h: Regenerated.
284 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
287 * z80-dis.c: Add support for GBZ80 opcodes.
289 2020-02-04 Alan Modra <amodra@gmail.com>
291 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
293 2020-02-03 Alan Modra <amodra@gmail.com>
295 * m32c-ibld.c: Regenerate.
297 2020-02-01 Alan Modra <amodra@gmail.com>
299 * frv-ibld.c: Regenerate.
301 2020-01-31 Jan Beulich <jbeulich@suse.com>
303 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
304 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
305 (OP_E_memory): Replace xmm_mdq_mode case label by
306 vex_scalar_w_dq_mode one.
307 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
309 2020-01-31 Jan Beulich <jbeulich@suse.com>
311 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
312 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
313 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
314 (intel_operand_size): Drop vex_w_dq_mode case label.
316 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
318 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
319 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
321 2020-01-30 Alan Modra <amodra@gmail.com>
323 * m32c-ibld.c: Regenerate.
325 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
327 * bpf-opc.c: Regenerate.
329 2020-01-30 Jan Beulich <jbeulich@suse.com>
331 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
332 (dis386): Use them to replace C2/C3 table entries.
333 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
334 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
335 ones. Use Size64 instead of DefaultSize on Intel64 ones.
336 * i386-tbl.h: Re-generate.
338 2020-01-30 Jan Beulich <jbeulich@suse.com>
340 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
342 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
344 * i386-tbl.h: Re-generate.
346 2020-01-30 Alan Modra <amodra@gmail.com>
348 * tic4x-dis.c (tic4x_dp): Make unsigned.
350 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
351 Jan Beulich <jbeulich@suse.com>
354 * i386-dis.c (MOVSXD_Fixup): New function.
355 (movsxd_mode): New enum.
356 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
357 (intel_operand_size): Handle movsxd_mode.
358 (OP_E_register): Likewise.
360 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
361 register on movsxd. Add movsxd with 16-bit destination register
362 for AMD64 and Intel64 ISAs.
363 * i386-tbl.h: Regenerated.
365 2020-01-27 Tamar Christina <tamar.christina@arm.com>
368 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
369 * aarch64-asm-2.c: Regenerate
370 * aarch64-dis-2.c: Likewise.
371 * aarch64-opc-2.c: Likewise.
373 2020-01-21 Jan Beulich <jbeulich@suse.com>
375 * i386-opc.tbl (sysret): Drop DefaultSize.
376 * i386-tbl.h: Re-generate.
378 2020-01-21 Jan Beulich <jbeulich@suse.com>
380 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
382 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
383 * i386-tbl.h: Re-generate.
385 2020-01-20 Nick Clifton <nickc@redhat.com>
387 * po/de.po: Updated German translation.
388 * po/pt_BR.po: Updated Brazilian Portuguese translation.
389 * po/uk.po: Updated Ukranian translation.
391 2020-01-20 Alan Modra <amodra@gmail.com>
393 * hppa-dis.c (fput_const): Remove useless cast.
395 2020-01-20 Alan Modra <amodra@gmail.com>
397 * arm-dis.c (print_insn_arm): Wrap 'T' value.
399 2020-01-18 Nick Clifton <nickc@redhat.com>
401 * configure: Regenerate.
402 * po/opcodes.pot: Regenerate.
404 2020-01-18 Nick Clifton <nickc@redhat.com>
406 Binutils 2.34 branch created.
408 2020-01-17 Christian Biesinger <cbiesinger@google.com>
410 * opintl.h: Fix spelling error (seperate).
412 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
414 * i386-opc.tbl: Add {vex} pseudo prefix.
415 * i386-tbl.h: Regenerated.
417 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
420 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
421 (neon_opcodes): Likewise.
422 (select_arm_features): Make sure we enable MVE bits when selecting
423 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
426 2020-01-16 Jan Beulich <jbeulich@suse.com>
428 * i386-opc.tbl: Drop stale comment from XOP section.
430 2020-01-16 Jan Beulich <jbeulich@suse.com>
432 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
433 (extractps): Add VexWIG to SSE2AVX forms.
434 * i386-tbl.h: Re-generate.
436 2020-01-16 Jan Beulich <jbeulich@suse.com>
438 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
439 Size64 from and use VexW1 on SSE2AVX forms.
440 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
441 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
442 * i386-tbl.h: Re-generate.
444 2020-01-15 Alan Modra <amodra@gmail.com>
446 * tic4x-dis.c (tic4x_version): Make unsigned long.
447 (optab, optab_special, registernames): New file scope vars.
448 (tic4x_print_register): Set up registernames rather than
449 malloc'd registertable.
450 (tic4x_disassemble): Delete optable and optable_special. Use
451 optab and optab_special instead. Throw away old optab,
452 optab_special and registernames when info->mach changes.
454 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
457 * z80-dis.c (suffix): Use .db instruction to generate double
460 2020-01-14 Alan Modra <amodra@gmail.com>
462 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
463 values to unsigned before shifting.
465 2020-01-13 Thomas Troeger <tstroege@gmx.de>
467 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
469 (print_insn_thumb16, print_insn_thumb32): Likewise.
470 (print_insn): Initialize the insn info.
471 * i386-dis.c (print_insn): Initialize the insn info fields, and
474 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
476 * arc-opc.c (C_NE): Make it required.
478 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
480 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
481 reserved register name.
483 2020-01-13 Alan Modra <amodra@gmail.com>
485 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
486 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
488 2020-01-13 Alan Modra <amodra@gmail.com>
490 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
491 result of wasm_read_leb128 in a uint64_t and check that bits
492 are not lost when copying to other locals. Use uint32_t for
493 most locals. Use PRId64 when printing int64_t.
495 2020-01-13 Alan Modra <amodra@gmail.com>
497 * score-dis.c: Formatting.
498 * score7-dis.c: Formatting.
500 2020-01-13 Alan Modra <amodra@gmail.com>
502 * score-dis.c (print_insn_score48): Use unsigned variables for
503 unsigned values. Don't left shift negative values.
504 (print_insn_score32): Likewise.
505 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
507 2020-01-13 Alan Modra <amodra@gmail.com>
509 * tic4x-dis.c (tic4x_print_register): Remove dead code.
511 2020-01-13 Alan Modra <amodra@gmail.com>
513 * fr30-ibld.c: Regenerate.
515 2020-01-13 Alan Modra <amodra@gmail.com>
517 * xgate-dis.c (print_insn): Don't left shift signed value.
518 (ripBits): Formatting, use 1u.
520 2020-01-10 Alan Modra <amodra@gmail.com>
522 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
523 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
525 2020-01-10 Alan Modra <amodra@gmail.com>
527 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
528 and XRREG value earlier to avoid a shift with negative exponent.
529 * m10200-dis.c (disassemble): Similarly.
531 2020-01-09 Nick Clifton <nickc@redhat.com>
534 * z80-dis.c (ld_ii_ii): Use correct cast.
536 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
539 * z80-dis.c (ld_ii_ii): Use character constant when checking
542 2020-01-09 Jan Beulich <jbeulich@suse.com>
544 * i386-dis.c (SEP_Fixup): New.
546 (dis386_twobyte): Use it for sysenter/sysexit.
547 (enum x86_64_isa): Change amd64 enumerator to value 1.
548 (OP_J): Compare isa64 against intel64 instead of amd64.
549 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
551 * i386-tbl.h: Re-generate.
553 2020-01-08 Alan Modra <amodra@gmail.com>
555 * z8k-dis.c: Include libiberty.h
556 (instr_data_s): Make max_fetched unsigned.
557 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
558 Don't exceed byte_info bounds.
559 (output_instr): Make num_bytes unsigned.
560 (unpack_instr): Likewise for nibl_count and loop.
561 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
563 * z8k-opc.h: Regenerate.
565 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
567 * arc-tbl.h (llock): Use 'LLOCK' as class.
569 (scond): Use 'SCOND' as class.
571 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
574 2020-01-06 Alan Modra <amodra@gmail.com>
576 * m32c-ibld.c: Regenerate.
578 2020-01-06 Alan Modra <amodra@gmail.com>
581 * z80-dis.c (suffix): Don't use a local struct buffer copy.
582 Peek at next byte to prevent recursion on repeated prefix bytes.
583 Ensure uninitialised "mybuf" is not accessed.
584 (print_insn_z80): Don't zero n_fetch and n_used here,..
585 (print_insn_z80_buf): ..do it here instead.
587 2020-01-04 Alan Modra <amodra@gmail.com>
589 * m32r-ibld.c: Regenerate.
591 2020-01-04 Alan Modra <amodra@gmail.com>
593 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
595 2020-01-04 Alan Modra <amodra@gmail.com>
597 * crx-dis.c (match_opcode): Avoid shift left of signed value.
599 2020-01-04 Alan Modra <amodra@gmail.com>
601 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
603 2020-01-03 Jan Beulich <jbeulich@suse.com>
605 * aarch64-tbl.h (aarch64_opcode_table): Use
606 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
608 2020-01-03 Jan Beulich <jbeulich@suse.com>
610 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
611 forms of SUDOT and USDOT.
613 2020-01-03 Jan Beulich <jbeulich@suse.com>
615 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
617 * opcodes/aarch64-dis-2.c: Re-generate.
619 2020-01-03 Jan Beulich <jbeulich@suse.com>
621 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
623 * opcodes/aarch64-dis-2.c: Re-generate.
625 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
627 * z80-dis.c: Add support for eZ80 and Z80 instructions.
629 2020-01-01 Alan Modra <amodra@gmail.com>
631 Update year range in copyright notice of all files.
633 For older changes see ChangeLog-2019
635 Copyright (C) 2020 Free Software Foundation, Inc.
637 Copying and distribution of this file, with or without modification,
638 are permitted in any medium without royalty provided the copyright
639 notice and this notice are preserved.
645 version-control: never