opcodes/ChangeLog

   1 2019-12-24  Alan Modra  <amodra@gmail.com>
   2
   3         * arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var.
   4
   5 2019-12-23  Jan Beulich  <jbeulich@suse.com>
   6
   7         * ppc-dis.c (print_insn_powerpc): Rename local variable "spaces"
   8         to "blanks".
   9         * ppc-opc.c (D34, SI34, NSI34): Use UINT64_C().
  10
  11 2019-12-23  Alan Modra  <amodra@gmail.com>
  12
  13         * score-dis.c (print_insn_score32): Avoid signed overflow.
  14         (print_insn_score48): Likewise.  Don't cast to int when printing
  15         hex values.
  16
  17 2019-12-23  Alan Modra  <amodra@gmail.com>
  18
  19         * iq2000-ibld.c: Regenerate.
  20
  21 2019-12-23  Alan Modra  <amodra@gmail.com>
  22
  23         * d30v-dis.c (extract_value): Make num param a uint64_t, constify
  24         oper.  Use unsigned vars.
  25         (print_insn): Make num var uint64_t.  Constify oper and remove now
  26         unnecessary casts on extract_value calls.
  27         (print_insn_d30v): Use unsigned vars.  Adjust printf formats.
  28
  29 2019-12-23  Alan Modra  <amodra@gmail.com>
  30
  31         * wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts.
  32         Catch value overflow.  Sign extend only on terminating byte.
  33
  34 2019-12-20  Alan Modra  <amodra@gmail.com>
  35
  36         PR 25281
  37         * sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
  38         and MOVY_NOPX insns.  For invalid cases include 0xf000 in the word
  39         printed.  Print .word in more cases.
  40
  41 2019-12-20  Alan Modra  <amodra@gmail.com>
  42
  43         * or1k-ibld.c: Regenerate.
  44
  45 2019-12-20  Alan Modra  <amodra@gmail.com>
  46
  47         * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
  48         unsigned variables.
  49
  50 2019-12-20  Alan Modra  <amodra@gmail.com>
  51
  52         * m68hc11-dis.c (read_memory): Delete forward decls.
  53         (print_indexed_operand, print_insn): Likewise.
  54         (print_indexed_operand): Formatting.  Don't rely on short being
  55         exactly 16 bits, make sign extension explicit.
  56         (print_insn): Likewise.  Avoid signed overflow.
  57
  58 2019-12-19  Alan Modra  <amodra@gmail.com>
  59
  60         * vax-dis.c (print_insn_mode): Stop index mode recursion.
  61
  62 2019-12-19  Dr N.W. Filardo  <nwf20@cam.ac.uk>
  63
  64         PR 25277
  65         * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
  66         fdiv with "mbi_".
  67         * microblaze-opc.h (opcodes): Adjust to suit.
  68
  69 2019-12-18  Alan Modra  <amodra@gmail.com>
  70
  71         * alpha-opc.c (OP): Avoid signed overflow.
  72         * arm-dis.c (print_insn): Likewise.
  73         * mcore-dis.c (print_insn_mcore): Likewise.
  74         * pj-dis.c (get_int): Likewise.
  75         * ppc-opc.c (EBD15, EBD15BI): Likewise.
  76         * score7-dis.c (s7_print_insn): Likewise.
  77         * tic30-dis.c (print_insn_tic30): Likewise.
  78         * v850-opc.c (insert_SELID): Likewise.
  79         * vax-dis.c (print_insn_vax): Likewise.
  80         * arc-ext.c (create_map): Likewise.
  81         (struct ExtAuxRegister): Make "address" field unsigned int.
  82         (arcExtMap_auxRegName): Pass unsigned address.
  83         (dump_ARC_extmap): Adjust.
  84         * arc-ext.h (arcExtMap_auxRegName): Update prototype.
  85
  86 2019-12-17  Alan Modra  <amodra@gmail.com>
  87
  88         * visium-dis.c (print_insn_visium): Avoid signed overflow.
  89
  90 2019-12-17  Alan Modra  <amodra@gmail.com>
  91
  92         * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
  93         (value_fit_unsigned_field_p): Likewise.
  94         (aarch64_wide_constant_p): Likewise.
  95         (operand_general_constraint_met_p): Likewise.
  96         * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
  97
  98 2019-12-17  Alan Modra  <amodra@gmail.com>
  99
 100         * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
 101         (print_insn_nds32): Use uint64_t for "given" and "given1".
 102
 103 2019-12-17  Alan Modra  <amodra@gmail.com>
 104
 105         * tic80-dis.c: Delete file.
 106         * tic80-opc.c: Delete file.
 107         * disassemble.c: Remove tic80 support.
 108         * disassemble.h: Likewise.
 109         * Makefile.am: Likewise.
 110         * configure.ac: Likewise.
 111         * Makefile.in: Regenerate.
 112         * configure: Regenerate.
 113         * po/POTFILES.in: Regenerate.
 114
 115 2019-12-17  Alan Modra  <amodra@gmail.com>
 116
 117         * bpf-ibld.c: Regenerate.
 118
 119 2019-12-16  Alan Modra  <amodra@gmail.com>
 120
 121         * aarch64-dis.c (sign_extend): Return uint64_t.  Rewrite without
 122         conditional.
 123         (aarch64_ext_imm): Avoid signed overflow.
 124
 125 2019-12-16  Alan Modra  <amodra@gmail.com>
 126
 127         * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
 128
 129 2019-12-16  Alan Modra  <amodra@gmail.com>
 130
 131         * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
 132
 133 2019-12-16  Alan Modra  <amodra@gmail.com>
 134
 135         * xstormy16-ibld.c: Regenerate.
 136
 137 2019-12-16  Alan Modra  <amodra@gmail.com>
 138
 139         * score-dis.c (print_insn_score16): Move rpush/rpop imm field
 140         value adjustment so that it doesn't affect reg field too.
 141
 142 2019-12-16  Alan Modra  <amodra@gmail.com>
 143
 144         * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
 145         (get_number_of_operands, getargtype, getbits, getregname),
 146         (getcopregname, getprocregname, gettrapstring, getcinvstring),
 147         (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
 148         (powerof2, match_opcode, make_instruction, print_arguments),
 149         (print_arg): Delete forward declarations, moving static to..
 150         (getregname, getcopregname, getregliststring): ..these definitions.
 151         (build_mask): Return unsigned int mask.
 152         (match_opcode): Use unsigned int vars.
 153
 154 2019-12-16  Alan Modra  <amodra@gmail.com>
 155
 156         * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
 157
 158 2019-12-16  Alan Modra  <amodra@gmail.com>
 159
 160         * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
 161         (struct objdump_disasm_info): Delete.
 162         (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
 163         N32_IMMS to unsigned before shifting left.
 164
 165 2019-12-16  Alan Modra  <amodra@gmail.com>
 166
 167         * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
 168         (print_insn_moxie): Remove unnecessary cast.
 169
 170 2019-12-12  Alan Modra  <amodra@gmail.com>
 171
 172         * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
 173         mask.
 174
 175 2019-12-11  Alan Modra  <amodra@gmail.com>
 176
 177         * arc-dis.c (BITS): Don't truncate high bits with shifts.
 178         * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
 179         * tic54x-dis.c (print_instruction): Likewise.
 180         * tilegx-opc.c (parse_insn_tilegx): Likewise.
 181         * tilepro-opc.c (parse_insn_tilepro): Likewise.
 182         * visium-dis.c (disassem_class0): Likewise.
 183         * pdp11-dis.c (sign_extend): Likewise.
 184         (SIGN_BITS): Delete.
 185         * epiphany-ibld.c: Regenerate.
 186         * lm32-ibld.c: Regenerate.
 187         * m32c-ibld.c: Regenerate.
 188
 189 2019-12-11  Alan Modra  <amodra@gmail.com>
 190
 191         * ns32k-dis.c (sign_extend): Correct last patch.
 192
 193 2019-12-11  Alan Modra  <amodra@gmail.com>
 194
 195         * vax-dis.c (NEXTLONG): Avoid signed overflow.
 196
 197 2019-12-11  Alan Modra  <amodra@gmail.com>
 198
 199         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
 200         sign extend using shifts.
 201
 202 2019-12-11  Alan Modra  <amodra@gmail.com>
 203
 204         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
 205
 206 2019-12-11  Alan Modra  <amodra@gmail.com>
 207
 208         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
 209         on NULL registertable entry.
 210         (tic4x_hash_opcode): Use unsigned arithmetic.
 211
 212 2019-12-11  Alan Modra  <amodra@gmail.com>
 213
 214         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
 215
 216 2019-12-11  Alan Modra  <amodra@gmail.com>
 217
 218         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
 219         (bit_extract_simple, sign_extend): Likewise.
 220
 221 2019-12-11  Alan Modra  <amodra@gmail.com>
 222
 223         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
 224
 225 2019-12-11  Alan Modra  <amodra@gmail.com>
 226
 227         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
 228
 229 2019-12-11  Alan Modra  <amodra@gmail.com>
 230
 231         * m68k-dis.c (COERCE32): Cast value first.
 232         (NEXTLONG, NEXTULONG): Avoid signed overflow.
 233
 234 2019-12-11  Alan Modra  <amodra@gmail.com>
 235
 236         * h8300-dis.c (extract_immediate): Avoid signed overflow.
 237         (bfd_h8_disassemble): Likewise.
 238
 239 2019-12-11  Alan Modra  <amodra@gmail.com>
 240
 241         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
 242         past end of operands array.
 243
 244 2019-12-11  Alan Modra  <amodra@gmail.com>
 245
 246         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
 247         overflow when collecting bytes of a number.
 248
 249 2019-12-11  Alan Modra  <amodra@gmail.com>
 250
 251         * cris-dis.c (print_with_operands): Avoid signed integer
 252         overflow when collecting bytes of a 32-bit integer.
 253
 254 2019-12-11  Alan Modra  <amodra@gmail.com>
 255
 256         * cr16-dis.c (EXTRACT, SBM): Rewrite.
 257         (cr16_match_opcode): Delete duplicate bcond test.
 258
 259 2019-12-11  Alan Modra  <amodra@gmail.com>
 260
 261         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
 262         (SIGNBIT): New.
 263         (MASKBITS, SIGNEXTEND): Rewrite.
 264         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
 265         unsigned arithmetic, instead assign result of SIGNEXTEND back
 266         to x.
 267         (fmtconst_val): Use 1u in shift expression.
 268
 269 2019-12-11  Alan Modra  <amodra@gmail.com>
 270
 271         * arc-dis.c (find_format_from_table): Use ull constant when
 272         shifting by up to 32.
 273
 274 2019-12-11  Alan Modra  <amodra@gmail.com>
 275
 276         PR 25270
 277         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
 278         false when field is zero for sve_size_tsz_bhs.
 279
 280 2019-12-11  Alan Modra  <amodra@gmail.com>
 281
 282         * epiphany-ibld.c: Regenerate.
 283
 284 2019-12-10  Alan Modra  <amodra@gmail.com>
 285
 286         PR 24960
 287         * disassemble.c (disassemble_free_target): New function.
 288
 289 2019-12-10  Alan Modra  <amodra@gmail.com>
 290
 291         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 292         * disassemble.c (disassemble_init_for_target): Likewise.
 293         * bpf-dis.c: Regenerate.
 294         * epiphany-dis.c: Regenerate.
 295         * fr30-dis.c: Regenerate.
 296         * frv-dis.c: Regenerate.
 297         * ip2k-dis.c: Regenerate.
 298         * iq2000-dis.c: Regenerate.
 299         * lm32-dis.c: Regenerate.
 300         * m32c-dis.c: Regenerate.
 301         * m32r-dis.c: Regenerate.
 302         * mep-dis.c: Regenerate.
 303         * mt-dis.c: Regenerate.
 304         * or1k-dis.c: Regenerate.
 305         * xc16x-dis.c: Regenerate.
 306         * xstormy16-dis.c: Regenerate.
 307
 308 2019-12-10  Alan Modra  <amodra@gmail.com>
 309
 310         * ppc-dis.c (private): Delete variable.
 311         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 312         (powerpc_init_dialect): Don't use global private.
 313
 314 2019-12-10  Alan Modra  <amodra@gmail.com>
 315
 316         * s12z-opc.c: Formatting.
 317
 318 2019-12-08  Alan Modra  <amodra@gmail.com>
 319
 320         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 321         registers.
 322
 323 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 324
 325         * aarch64-tbl.h (aarch64_feature_crypto,
 326         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 327         CRYPTO_V8_2_INSN): Delete.
 328
 329 2019-12-05  Alan Modra  <amodra@gmail.com>
 330
 331         PR 25249
 332         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 333         (struct string_buf): New.
 334         (strbuf): New function.
 335         (get_field): Use strbuf rather than strdup of local temp.
 336         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 337         (get_field_rfsl, get_field_imm15): Likewise.
 338         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 339         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 340         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 341         get_field functions.
 342
 343 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 344
 345         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 346         * i386-tbl.h: Re-generate.
 347
 348 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 349
 350         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 351
 352 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 353
 354         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 355         forms.
 356         (xbegin): Drop DefaultSize.
 357         * i386-tbl.h: Re-generate.
 358
 359 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 360
 361         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 362         Change the coproc CRC conditions to use the extension
 363         feature set, second word, base on ARM_EXT2_CRC.
 364
 365 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 366
 367         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 368         * i386-tbl.h: Re-generate.
 369
 370 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 371
 372         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 373         JumpInterSegment, and JumpAbsolute entries.
 374         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 375         JUMP_ABSOLUTE): Define.
 376         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 377         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 378         fields.
 379         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 380         JumpInterSegment): Define.
 381         * i386-tbl.h: Re-generate.
 382
 383 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 384
 385         * i386-gen.c (operand_type_init): Remove
 386         OPERAND_TYPE_JUMPABSOLUTE entry.
 387         (opcode_modifiers): Add JumpAbsolute entry.
 388         (operand_types): Remove JumpAbsolute entry.
 389         * i386-opc.h (JumpAbsolute): Move between enums.
 390         (struct i386_opcode_modifier): Add jumpabsolute field.
 391         (union i386_operand_type): Remove jumpabsolute field.
 392         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 393         * i386-init.h, i386-tbl.h: Re-generate.
 394
 395 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 396
 397         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 398         (operand_types): Remove AnySize entry.
 399         * i386-opc.h (AnySize): Move between enums.
 400         (struct i386_opcode_modifier): Add anysize field.
 401         (OTUnused): Un-comment.
 402         (union i386_operand_type): Remove anysize field.
 403         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 404         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 405         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 406         AnySize.
 407         * i386-tbl.h: Re-generate.
 408
 409 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 410
 411         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 412         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 413         use the floating point register (FPR).
 414
 415 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 416
 417         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 418         cmode 1101.
 419         (is_mve_encoding_conflict): Update cmode conflict checks for
 420         MVE_VMVN_IMM.
 421
 422 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 423
 424         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 425         entry.
 426         (operand_types): Remove EsSeg entry.
 427         (main): Replace stale use of OTMax.
 428         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 429         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 430         (EsSeg): Delete.
 431         (OTUnused): Comment out.
 432         (union i386_operand_type): Remove esseg field.
 433         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 434         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 435         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 436         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 437         * i386-init.h, i386-tbl.h: Re-generate.
 438
 439 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 440
 441         * i386-gen.c (operand_instances): Add RegB entry.
 442         * i386-opc.h (enum operand_instance): Add RegB.
 443         * i386-opc.tbl (RegC, RegD, RegB): Define.
 444         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 445         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 446         monitorx, mwaitx): Drop ImmExt and convert encodings
 447         accordingly.
 448         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 449         (edx, rdx): Add Instance=RegD.
 450         (ebx, rbx): Add Instance=RegB.
 451         * i386-tbl.h: Re-generate.
 452
 453 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-gen.c (operand_type_init): Adjust
 456         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 457         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 458         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 459         (operand_instances): New.
 460         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 461         (output_operand_type): New parameter "instance". Process it.
 462         (process_i386_operand_type): New local variable "instance".
 463         (main): Adjust static assertions.
 464         * i386-opc.h (INSTANCE_WIDTH): Define.
 465         (enum operand_instance): New.
 466         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 467         (union i386_operand_type): Replace acc, inoutportreg, and
 468         shiftcount by instance.
 469         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 470         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 471         Add Instance=.
 472         * i386-init.h, i386-tbl.h: Re-generate.
 473
 474 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 475
 476         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 477         smaxp/sminp entries' "tied_operand" field to 2.
 478
 479 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 480
 481         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 482         "index" local variable by that of the already existing "num".
 483
 484 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 485
 486         PR gas/25167
 487         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 488         * i386-tbl.h: Regenerated.
 489
 490 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 491
 492         * i386-gen.c (operand_type_init): Add Class= to
 493         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 494         OPERAND_TYPE_REGBND entry.
 495         (operand_classes): Add RegMask and RegBND entries.
 496         (operand_types): Drop RegMask and RegBND entry.
 497         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 498         (RegMask, RegBND): Delete.
 499         (union i386_operand_type): Remove regmask and regbnd fields.
 500         * i386-opc.tbl (RegMask, RegBND): Define.
 501         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 502         Class=RegBND.
 503         * i386-init.h, i386-tbl.h: Re-generate.
 504
 505 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 506
 507         * i386-gen.c (operand_type_init): Add Class= to
 508         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 509         OPERAND_TYPE_REGZMM entries.
 510         (operand_classes): Add RegMMX and RegSIMD entries.
 511         (operand_types): Drop RegMMX and RegSIMD entries.
 512         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 513         (RegMMX, RegSIMD): Delete.
 514         (union i386_operand_type): Remove regmmx and regsimd fields.
 515         * i386-opc.tbl (RegMMX): Define.
 516         (RegXMM, RegYMM, RegZMM): Add Class=.
 517         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 518         Class=RegSIMD.
 519         * i386-init.h, i386-tbl.h: Re-generate.
 520
 521 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 522
 523         * i386-gen.c (operand_type_init): Add Class= to
 524         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 525         entries.
 526         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 527         (operand_types): Drop Control, Debug, and Test entries.
 528         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 529         (Control, Debug, Test): Delete.
 530         (union i386_operand_type): Remove control, debug, and test
 531         fields.
 532         * i386-opc.tbl (Control, Debug, Test): Define.
 533         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 534         Class=RegDR, and Test by Class=RegTR.
 535         * i386-init.h, i386-tbl.h: Re-generate.
 536
 537 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 538
 539         * i386-gen.c (operand_type_init): Add Class= to
 540         OPERAND_TYPE_SREG entry.
 541         (operand_classes): Add SReg entry.
 542         (operand_types): Drop SReg entry.
 543         * i386-opc.h (enum operand_class): Add SReg.
 544         (SReg): Delete.
 545         (union i386_operand_type): Remove sreg field.
 546         * i386-opc.tbl (SReg): Define.
 547         * i386-reg.tbl: Replace SReg by Class=SReg.
 548         * i386-init.h, i386-tbl.h: Re-generate.
 549
 550 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 551
 552         * i386-gen.c (operand_type_init): Add Class=. New
 553         OPERAND_TYPE_ANYIMM entry.
 554         (operand_classes): New.
 555         (operand_types): Drop Reg entry.
 556         (output_operand_type): New parameter "class". Process it.
 557         (process_i386_operand_type): New local variable "class".
 558         (main): Adjust static assertions.
 559         * i386-opc.h (CLASS_WIDTH): Define.
 560         (enum operand_class): New.
 561         (Reg): Replace by Class. Adjust comment.
 562         (union i386_operand_type): Replace reg by class.
 563         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 564         Class=.
 565         * i386-reg.tbl: Replace Reg by Class=Reg.
 566         * i386-init.h: Re-generate.
 567
 568 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 569
 570         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 571         (aarch64_opcode_table): Add data gathering hint mnemonic.
 572         * opcodes/aarch64-dis-2.c: Account for new instruction.
 573
 574 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 575
 576         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 577
 578
 579 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 580
 581         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 582         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 583         aarch64_feature_f64mm): New feature sets.
 584         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 585         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 586         instructions.
 587         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 588         macros.
 589         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 590         (OP_SVE_QQQ): New qualifier.
 591         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 592         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 593         the movprfx constraint.
 594         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 595         (aarch64_opcode_table): Define new instructions smmla,
 596         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 597         uzip{1/2}, trn{1/2}.
 598         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 599         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 600         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 601         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 602         Account for new instructions.
 603         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 604         S4x32 operand.
 605         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 606
 607 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 608 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 609
 610         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 611         Armv8.6-A.
 612         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 613         (neon_opcodes): Add bfloat SIMD instructions.
 614         (print_insn_coprocessor): Add new control character %b to print
 615         condition code without checking cp_num.
 616         (print_insn_neon): Account for BFloat16 instructions that have no
 617         special top-byte handling.
 618
 619 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 620 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 621
 622         * arm-dis.c (print_insn_coprocessor,
 623         print_insn_generic_coprocessor): Create wrapper functions around
 624         the implementation of the print_insn_coprocessor control codes.
 625         (print_insn_coprocessor_1): Original print_insn_coprocessor
 626         function that now takes which array to look at as an argument.
 627         (print_insn_arm): Use both print_insn_coprocessor and
 628         print_insn_generic_coprocessor.
 629         (print_insn_thumb32): As above.
 630
 631 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 632 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 633
 634         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 635         in reglane special case.
 636         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 637         aarch64_find_next_opcode): Account for new instructions.
 638         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 639         in reglane special case.
 640         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 641         new AARCH64_OPND_QLF_S_2H qualifier.
 642         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 643         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 644         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 645         sets.
 646         (BFLOAT_SVE, BFLOAT): New feature set macros.
 647         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 648         instructions.
 649         (aarch64_opcode_table): Define new instructions bfdot,
 650         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 651         bfcvtn2, bfcvt.
 652
 653 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 654 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 655
 656         * aarch64-tbl.h (ARMV8_6): New macro.
 657
 658 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 659
 660         * i386-dis.c (prefix_table): Add mcommit.
 661         (rm_table): Add rdpru.
 662         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 663         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 664         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 665         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 666         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 667         * i386-opc.tbl (mcommit, rdpru): New.
 668         * i386-init.h, i386-tbl.h: Re-generate.
 669
 670 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 671
 672         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 673         "names32" instead.
 674         (OP_Monitor): Drop local variable "op1_names", re-purpose
 675         "names" for it instead, and replace former "names" uses by
 676         "names32" ones.
 677
 678 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 679
 680         PR/gas 25167
 681         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 682         operand-less forms.
 683         * opcodes/i386-tbl.h: Re-generate.
 684
 685 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 686
 687         * i386-dis.c (OP_Mwaitx): Delete.
 688         (prefix_table): Use OP_Mwait for mwaitx entry.
 689         (OP_Mwait): Also handle mwaitx.
 690
 691 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 692
 693         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 694         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 695         (prefix_table): Add respective entries.
 696         (rm_table): Link to those entries.
 697
 698 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 699
 700         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 701         (REG_0F1C_P_0_MOD_0): ... this.
 702         (REG_0F1E_MOD_3): Rename to ...
 703         (REG_0F1E_P_1_MOD_3): ... this.
 704         (RM_0F01_REG_5): Rename to ...
 705         (RM_0F01_REG_5_MOD_3): ... this.
 706         (RM_0F01_REG_7): Rename to ...
 707         (RM_0F01_REG_7_MOD_3): ... this.
 708         (RM_0F1E_MOD_3_REG_7): Rename to ...
 709         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 710         (RM_0FAE_REG_6): Rename to ...
 711         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 712         (RM_0FAE_REG_7): Rename to ...
 713         (RM_0FAE_REG_7_MOD_3): ... this.
 714         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 715         (PREFIX_0F01_REG_5_MOD_0): ... this.
 716         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 717         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 718         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 719         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 720         (PREFIX_0FAE_REG_0): Rename to ...
 721         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 722         (PREFIX_0FAE_REG_1): Rename to ...
 723         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 724         (PREFIX_0FAE_REG_2): Rename to ...
 725         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 726         (PREFIX_0FAE_REG_3): Rename to ...
 727         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 728         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 729         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 730         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 731         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 732         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 733         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 734         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 735         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 736         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 737         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 738         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 739         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 740         (PREFIX_0FAE_REG_7): Rename to ...
 741         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 742         (PREFIX_MOD_0_0FC3): Rename to ...
 743         (PREFIX_0FC3_MOD_0): ... this.
 744         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 745         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 746         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 747         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 748         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 749         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 750         (reg_table, prefix_table, mod_table, rm_table): Adjust
 751         accordingly.
 752
 753 2019-11-04  Nick Clifton  <nickc@redhat.com>
 754
 755         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 756         of a v850 system register.  Move the v850_sreg_names array into
 757         this function.
 758         (get_v850_reg_name): Likewise for ordinary register names.
 759         (get_v850_vreg_name): Likewise for vector register names.
 760         (get_v850_cc_name): Likewise for condition codes.
 761         * get_v850_float_cc_name): Likewise for floating point condition
 762         codes.
 763         (get_v850_cacheop_name): Likewise for cache-ops.
 764         (get_v850_prefop_name): Likewise for pref-ops.
 765         (disassemble): Use the new accessor functions.
 766
 767 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 768
 769         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 770         immediate for the writeback form of ldraa/ldrab if it is 0.
 771         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 772         * aarch64-opc-2.c: Regenerated.
 773
 774 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 775
 776         * i386-gen.c (operand_type_shorthands): Delete.
 777         (operand_type_init): Expand previous shorthands.
 778         (set_bitfield_from_shorthand): Rename back to ...
 779         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 780         of operand_type_init[].
 781         (set_bitfield): Adjust call to the above function.
 782         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 783         RegXMM, RegYMM, RegZMM): Define.
 784         * i386-reg.tbl: Expand prior shorthands.
 785
 786 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 787
 788         * i386-gen.c (output_i386_opcode): Change order of fields
 789         emitted to output.
 790         * i386-opc.h (struct insn_template): Move operands field.
 791         Convert extension_opcode field to unsigned short.
 792         * i386-tbl.h: Re-generate.
 793
 794 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 795
 796         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 797         of W.
 798         * i386-opc.h (W): Extend comment.
 799         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 800         general purpose variants not allowing for byte operands.
 801         * i386-tbl.h: Re-generate.
 802
 803 2019-10-29  Nick Clifton  <nickc@redhat.com>
 804
 805         * tic30-dis.c (print_branch): Correct size of operand array.
 806
 807 2019-10-29  Nick Clifton  <nickc@redhat.com>
 808
 809         * d30v-dis.c (print_insn): Check that operand index is valid
 810         before attempting to access the operands array.
 811
 812 2019-10-29  Nick Clifton  <nickc@redhat.com>
 813
 814         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 815         locating the bit to be tested.
 816
 817 2019-10-29  Nick Clifton  <nickc@redhat.com>
 818
 819         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 820         values.
 821         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 822         (print_insn_s12z):  Check for illegal size values.
 823
 824 2019-10-28  Nick Clifton  <nickc@redhat.com>
 825
 826         * csky-dis.c (csky_chars_to_number): Check for a negative
 827         count. Use an unsigned integer to construct the return value.
 828
 829 2019-10-28  Nick Clifton  <nickc@redhat.com>
 830
 831         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 832         operand buffer.  Set value to 15 not 13.
 833         (get_register_operand): Use OPERAND_BUFFER_LEN.
 834         (get_indirect_operand): Likewise.
 835         (print_two_operand): Likewise.
 836         (print_three_operand): Likewise.
 837         (print_oar_insn): Likewise.
 838
 839 2019-10-28  Nick Clifton  <nickc@redhat.com>
 840
 841         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 842         (bit_extract_simple): Likewise.
 843         (bit_copy): Likewise.
 844         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 845         index_offset array are not accessed.
 846
 847 2019-10-28  Nick Clifton  <nickc@redhat.com>
 848
 849         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 850         operand.
 851
 852 2019-10-25  Nick Clifton  <nickc@redhat.com>
 853
 854         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 855         access to opcodes.op array element.
 856
 857 2019-10-23  Nick Clifton  <nickc@redhat.com>
 858
 859         * rx-dis.c (get_register_name): Fix spelling typo in error
 860         message.
 861         (get_condition_name, get_flag_name, get_double_register_name)
 862         (get_double_register_high_name, get_double_register_low_name)
 863         (get_double_control_register_name, get_double_condition_name)
 864         (get_opsize_name, get_size_name): Likewise.
 865
 866 2019-10-22  Nick Clifton  <nickc@redhat.com>
 867
 868         * rx-dis.c (get_size_name): New function.  Provides safe
 869         access to name array.
 870         (get_opsize_name): Likewise.
 871         (print_insn_rx): Use the accessor functions.
 872
 873 2019-10-16  Nick Clifton  <nickc@redhat.com>
 874
 875         * rx-dis.c (get_register_name): New function.  Provides safe
 876         access to name array.
 877         (get_condition_name, get_flag_name, get_double_register_name)
 878         (get_double_register_high_name, get_double_register_low_name)
 879         (get_double_control_register_name, get_double_condition_name):
 880         Likewise.
 881         (print_insn_rx): Use the accessor functions.
 882
 883 2019-10-09  Nick Clifton  <nickc@redhat.com>
 884
 885         PR 25041
 886         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 887         instructions.
 888
 889 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 890
 891         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 892         (cmpsd): Likewise. Move EsSeg to other operand.
 893         * opcodes/i386-tbl.h: Re-generate.
 894
 895 2019-09-23  Alan Modra  <amodra@gmail.com>
 896
 897         * m68k-dis.c: Include cpu-m68k.h
 898
 899 2019-09-23  Alan Modra  <amodra@gmail.com>
 900
 901         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 902         "elf/mips.h" earlier.
 903
 904 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 905
 906         PR gas/25012
 907         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 908         with SReg operand.
 909         * i386-tbl.h: Re-generate.
 910
 911 2019-09-18  Alan Modra  <amodra@gmail.com>
 912
 913         * arc-ext.c: Update throughout for bfd section macro changes.
 914
 915 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 916
 917         * Makefile.in: Re-generate.
 918         * configure: Re-generate.
 919
 920 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 921
 922         * riscv-opc.c (riscv_opcodes): Change subset field
 923         to insn_class field for all instructions.
 924         (riscv_insn_types): Likewise.
 925
 926 2019-09-16  Phil Blundell  <pb@pbcl.net>
 927
 928         * configure: Regenerated.
 929
 930 2019-09-10  Miod Vallat  <miod@online.fr>
 931
 932         PR 24982
 933         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 934
 935 2019-09-09  Phil Blundell  <pb@pbcl.net>
 936
 937         binutils 2.33 branch created.
 938
 939 2019-09-03  Nick Clifton  <nickc@redhat.com>
 940
 941         PR 24961
 942         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 943         greater than zero before indexing via (bufcnt -1).
 944
 945 2019-09-03  Nick Clifton  <nickc@redhat.com>
 946
 947         PR 24958
 948         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 949         (MAX_SPEC_REG_NAME_LEN): Define.
 950         (struct mmix_dis_info): Use defined constants for array lengths.
 951         (get_reg_name): New function.
 952         (get_sprec_reg_name): New function.
 953         (print_insn_mmix): Use new functions.
 954
 955 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 956
 957         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 958         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 959         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 960
 961 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 962
 963         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 964         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 965         (aarch64_sys_reg_supported_p): Update checks for the above.
 966
 967 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 968
 969         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 970         cases MVE_SQRSHRL and MVE_UQRSHLL.
 971         (print_insn_mve): Add case for specifier 'k' to check
 972         specific bit of the instruction.
 973
 974 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 975
 976         PR 24854
 977         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 978         encountering an unknown machine type.
 979         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 980         cases return -1 rather than calling abort.
 981
 982 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 983
 984         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 985         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 986         IgnoreSize.
 987         * i386-tbl.h: Re-generate.
 988
 989 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 990
 991         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 992         instructions.
 993
 994 2019-07-30  Mel Chen <mel.chen@sifive.com>
 995
 996         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 997         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 998
 999         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
1000         fscsr.
1001
1002 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
1003
1004         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
1005         and MPY class instructions.
1006         (parse_option): Add nps400 option.
1007         (print_arc_disassembler_options): Add nps400 info.
1008
1009 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
1010
1011         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
1012         (bspop): Likewise.
1013         (modapp): Likewise.
1014         * arc-opc.c (RAD_CHK): Add.
1015         * arc-tbl.h: Regenerate.
1016
1017 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1018
1019         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
1020         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
1021
1022 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
1023
1024         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
1025         instructions as UNPREDICTABLE.
1026
1027 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
1028
1029         * bpf-desc.c: Regenerated.
1030
1031 2019-07-17  Jan Beulich  <jbeulich@suse.com>
1032
1033         * i386-gen.c (static_assert): Define.
1034         (main): Use it.
1035         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
1036         (Opcode_Modifier_Num): ... this.
1037         (Mem): Delete.
1038
1039 2019-07-16  Jan Beulich  <jbeulich@suse.com>
1040
1041         * i386-gen.c (operand_types): Move RegMem ...
1042         (opcode_modifiers): ... here.
1043         * i386-opc.h (RegMem): Move to opcode modifer enum.
1044         (union i386_operand_type): Move regmem field ...
1045         (struct i386_opcode_modifier): ... here.
1046         * i386-opc.tbl (RegMem): Define.
1047         (mov, movq): Move RegMem on segment, control, debug, and test
1048         register flavors.
1049         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1050         to non-SSE2AVX flavor.
1051         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1052         Move RegMem on register only flavors. Drop IgnoreSize from
1053         legacy encoding flavors.
1054         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1055         flavors.
1056         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1057         register only flavors.
1058         (vmovd): Move RegMem and drop IgnoreSize on register only
1059         flavor. Change opcode and operand order to store form.
1060         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1061
1062 2019-07-16  Jan Beulich  <jbeulich@suse.com>
1063
1064         * i386-gen.c (operand_type_init, operand_types): Replace SReg
1065         entries.
1066         * i386-opc.h (SReg2, SReg3): Replace by ...
1067         (SReg): ... this.
1068         (union i386_operand_type): Replace sreg fields.
1069         * i386-opc.tbl (mov, ): Use SReg.
1070         (push, pop): Likewies. Drop i386 and x86-64 specific segment
1071         register flavors.
1072         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1073         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1074
1075 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
1076
1077         * bpf-desc.c: Regenerate.
1078         * bpf-opc.c: Likewise.
1079         * bpf-opc.h: Likewise.
1080
1081 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
1082
1083         * bpf-desc.c: Regenerate.
1084         * bpf-opc.c: Likewise.
1085
1086 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
1087
1088         * arm-dis.c (print_insn_coprocessor): Rename index to
1089         index_operand.
1090
1091 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
1092
1093         * riscv-opc.c (riscv_insn_types): Add r4 type.
1094
1095         * riscv-opc.c (riscv_insn_types): Add b and j type.
1096
1097         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1098         format for sb type and correct s type.
1099
1100 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1101
1102         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1103         SVE FMOV alias of FCPY.
1104
1105 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1106
1107         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1108         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1109
1110 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1111
1112         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1113         registers in an instruction prefixed by MOVPRFX.
1114
1115 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
1116
1117         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1118         sve_size_13 icode to account for variant behaviour of
1119         pmull{t,b}.
1120         * aarch64-dis-2.c: Regenerate.
1121         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1122         sve_size_13 icode to account for variant behaviour of
1123         pmull{t,b}.
1124         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1125         (OP_SVE_VVV_Q_D): Add new qualifier.
1126         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1127         (struct aarch64_opcode): Split pmull{t,b} into those requiring
1128         AES and those not.
1129
1130 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1131
1132         * opcodes/i386-gen.c (operand_type_init): Remove
1133         OPERAND_TYPE_VEC_IMM4 entry.
1134         (operand_types): Remove Vec_Imm4.
1135         * opcodes/i386-opc.h (Vec_Imm4): Delete.
1136         (union i386_operand_type): Remove vec_imm4.
1137         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1138         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1139
1140 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1141
1142         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1143         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1144         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1145         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1146         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1147         monitorx, mwaitx): Drop ImmExt from operand-less forms.
1148         * i386-tbl.h: Re-generate.
1149
1150 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1151
1152         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1153         register operands.
1154         * i386-tbl.h: Re-generate.
1155
1156 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1157
1158         * i386-opc.tbl (C): New.
1159         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1160         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1161         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1162         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1163         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1164         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1165         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1166         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1167         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1168         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1169         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1170         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1171         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1172         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1173         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1174         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1175         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1176         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1177         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1178         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1179         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1180         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1181         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1182         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1183         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1184         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1185         flavors.
1186         * i386-tbl.h: Re-generate.
1187
1188 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1189
1190         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1191         register operands.
1192         * i386-tbl.h: Re-generate.
1193
1194 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1195
1196         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1197         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1198         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1199         * i386-tbl.h: Re-generate.
1200
1201 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1202
1203         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1204         Disp8MemShift from register only templates.
1205         * i386-tbl.h: Re-generate.
1206
1207 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1208
1209         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1210         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1211         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1212         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1213         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1214         EVEX_W_0F11_P_3_M_1): Delete.
1215         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1216         EVEX_W_0F11_P_3): New.
1217         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1218         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1219         MOD_EVEX_0F11_PREFIX_3 table entries.
1220         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1221         PREFIX_EVEX_0F11 table entries.
1222         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1223         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1224         EVEX_W_0F11_P_3_M_{0,1} table entries.
1225
1226 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1227
1228         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1229         Delete.
1230
1231 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1232
1233         PR binutils/24719
1234         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1235         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1236         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1237         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1238         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1239         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1240         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1241         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1242         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1243         PREFIX_EVEX_0F38C6_REG_6 entries.
1244         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1245         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1246         EVEX_W_0F38C7_R_6_P_2 entries.
1247         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1248         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1249         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1250         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1251         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1252         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1253         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1254
1255 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1256
1257         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1258         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1259         VEX_LEN_0F2D_P_3): Delete.
1260         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1261         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1262         (prefix_table): ... here.
1263
1264 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1265
1266         * i386-dis.c (Iq): Delete.
1267         (Id): New.
1268         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1269         TBM insns.
1270         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1271         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1272         (OP_E_memory): Also honor needindex when deciding whether an
1273         address size prefix needs printing.
1274         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1275
1276 2019-06-26  Jim Wilson  <jimw@sifive.com>
1277
1278         PR binutils/24739
1279         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1280         Set info->display_endian to info->endian_code.
1281
1282 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1283
1284         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1285         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1286         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1287         OPERAND_TYPE_ACC64 entries.
1288         * i386-init.h: Re-generate.
1289
1290 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1291
1292         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1293         Delete.
1294         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1295         of dqa_mode.
1296         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1297         entries here.
1298         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1299         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1300
1301 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1302
1303         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1304         variables.
1305
1306 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1307
1308         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1309         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1310         movnti.
1311         * i386-opc.tbl (movnti): Add IgnoreSize.
1312         * i386-tbl.h: Re-generate.
1313
1314 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1315
1316         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1317         * i386-tbl.h: Re-generate.
1318
1319 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1320
1321         * i386-dis-evex.h: Break into ...
1322         * i386-dis-evex-len.h: New file.
1323         * i386-dis-evex-mod.h: Likewise.
1324         * i386-dis-evex-prefix.h: Likewise.
1325         * i386-dis-evex-reg.h: Likewise.
1326         * i386-dis-evex-w.h: Likewise.
1327         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1328         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1329         i386-dis-evex-mod.h.
1330
1331 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1332
1333         PR binutils/24700
1334         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1335         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1336         EVEX_W_0F385B_P_2.
1337         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1338         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1339         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1340         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1341         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1342         EVEX_LEN_0F385B_P_2_W_1.
1343         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1344         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1345         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1346         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1347         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1348         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1349         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1350         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1351         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1352         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1353
1354 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1355
1356         PR binutils/24691
1357         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1358         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1359         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1360         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1361         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1362         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1363         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1364         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1365         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1366         EVEX_LEN_0F3A43_P_2_W_1.
1367         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1368         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1369         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1370         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1371         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1372         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1373         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1374         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1375         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1376         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1377         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1378         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1379
1380 2019-06-14  Nick Clifton  <nickc@redhat.com>
1381
1382         * po/fr.po; Updated French translation.
1383
1384 2019-06-13  Stafford Horne  <shorne@gmail.com>
1385
1386         * or1k-asm.c: Regenerated.
1387         * or1k-desc.c: Regenerated.
1388         * or1k-desc.h: Regenerated.
1389         * or1k-dis.c: Regenerated.
1390         * or1k-ibld.c: Regenerated.
1391         * or1k-opc.c: Regenerated.
1392         * or1k-opc.h: Regenerated.
1393         * or1k-opinst.c: Regenerated.
1394
1395 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1396
1397         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1398
1399 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1400
1401         PR binutils/24633
1402         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1403         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1404         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1405         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1406         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1407         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1408         EVEX_LEN_0F3A1B_P_2_W_1.
1409         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1410         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1411         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1412         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1413         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1414         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1415         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1416         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1417
1418 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1419
1420         PR binutils/24626
1421         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1422         EVEX.vvvv when disassembling VEX and EVEX instructions.
1423         (OP_VEX): Set vex.register_specifier to 0 after readding
1424         vex.register_specifier.
1425         (OP_Vex_2src_1): Likewise.
1426         (OP_Vex_2src_2): Likewise.
1427         (OP_LWP_E): Likewise.
1428         (OP_EX_Vex): Don't check vex.register_specifier.
1429         (OP_XMM_Vex): Likewise.
1430
1431 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1432             Lili Cui  <lili.cui@intel.com>
1433
1434         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1435         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1436         instructions.
1437         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1438         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1439         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1440         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1441         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1442         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1443         * i386-init.h: Regenerated.
1444         * i386-tbl.h: Likewise.
1445
1446 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1447             Lili Cui  <lili.cui@intel.com>
1448
1449         * doc/c-i386.texi: Document enqcmd.
1450         * testsuite/gas/i386/enqcmd-intel.d: New file.
1451         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1452         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1453         * testsuite/gas/i386/enqcmd.d: Likewise.
1454         * testsuite/gas/i386/enqcmd.s: Likewise.
1455         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1456         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1457         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1458         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1459         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1460         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1461         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1462         and x86-64-enqcmd.
1463
1464 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1465
1466         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1467
1468 2019-06-03  Alan Modra  <amodra@gmail.com>
1469
1470         * ppc-dis.c (prefix_opcd_indices): Correct size.
1471
1472 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1473
1474         PR gas/24625
1475         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1476         Disp8ShiftVL.
1477         * i386-tbl.h: Regenerated.
1478
1479 2019-05-24  Alan Modra  <amodra@gmail.com>
1480
1481         * po/POTFILES.in: Regenerate.
1482
1483 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1484             Alan Modra  <amodra@gmail.com>
1485
1486         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1487         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1488         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1489         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1490         XTOP>): Define and add entries.
1491         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1492         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1493         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1494         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1495
1496 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1497             Alan Modra  <amodra@gmail.com>
1498
1499         * ppc-dis.c (ppc_opts): Add "future" entry.
1500         (PREFIX_OPCD_SEGS): Define.
1501         (prefix_opcd_indices): New array.
1502         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1503         (lookup_prefix): New function.
1504         (print_insn_powerpc): Handle 64-bit prefix instructions.
1505         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1506         (PMRR, POWERXX): Define.
1507         (prefix_opcodes): New instruction table.
1508         (prefix_num_opcodes): New constant.
1509
1510 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1511
1512         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1513         * configure: Regenerated.
1514         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1515         and cpu/bpf.opc.
1516         (HFILES): Add bpf-desc.h and bpf-opc.h.
1517         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1518         bpf-ibld.c and bpf-opc.c.
1519         (BPF_DEPS): Define.
1520         * Makefile.in: Regenerated.
1521         * disassemble.c (ARCH_bpf): Define.
1522         (disassembler): Add case for bfd_arch_bpf.
1523         (disassemble_init_for_target): Likewise.
1524         (enum epbf_isa_attr): Define.
1525         * disassemble.h: extern print_insn_bpf.
1526         * bpf-asm.c: Generated.
1527         * bpf-opc.h: Likewise.
1528         * bpf-opc.c: Likewise.
1529         * bpf-ibld.c: Likewise.
1530         * bpf-dis.c: Likewise.
1531         * bpf-desc.h: Likewise.
1532         * bpf-desc.c: Likewise.
1533
1534 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1535
1536         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1537         and VMSR with the new operands.
1538
1539 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1540
1541         * arm-dis.c (enum mve_instructions): New enum
1542         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1543         and cneg.
1544         (mve_opcodes): New instructions as above.
1545         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1546         csneg and csel.
1547         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1548
1549 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1550
1551         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1552         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1553         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1554         uqshl, urshrl and urshr.
1555         (is_mve_okay_in_it): Add new instructions to TRUE list.
1556         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1557         (print_insn_mve): Updated to accept new %j,
1558         %<bitfield>m and %<bitfield>n patterns.
1559
1560 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1561
1562         * mips-opc.c (mips_builtin_opcodes): Change source register
1563         constraint for DAUI.
1564
1565 2019-05-20  Nick Clifton  <nickc@redhat.com>
1566
1567         * po/fr.po: Updated French translation.
1568
1569 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1570             Michael Collison <michael.collison@arm.com>
1571
1572         * arm-dis.c (thumb32_opcodes): Add new instructions.
1573         (enum mve_instructions): Likewise.
1574         (enum mve_undefined): Add new reasons.
1575         (is_mve_encoding_conflict): Handle new instructions.
1576         (is_mve_undefined): Likewise.
1577         (is_mve_unpredictable): Likewise.
1578         (print_mve_undefined): Likewise.
1579         (print_mve_size): Likewise.
1580
1581 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1582             Michael Collison <michael.collison@arm.com>
1583
1584         * arm-dis.c (thumb32_opcodes): Add new instructions.
1585         (enum mve_instructions): Likewise.
1586         (is_mve_encoding_conflict): Handle new instructions.
1587         (is_mve_undefined): Likewise.
1588         (is_mve_unpredictable): Likewise.
1589         (print_mve_size): Likewise.
1590
1591 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1592             Michael Collison <michael.collison@arm.com>
1593
1594         * arm-dis.c (thumb32_opcodes): Add new instructions.
1595         (enum mve_instructions): Likewise.
1596         (is_mve_encoding_conflict): Likewise.
1597         (is_mve_unpredictable): Likewise.
1598         (print_mve_size): Likewise.
1599
1600 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1601             Michael Collison <michael.collison@arm.com>
1602
1603         * arm-dis.c (thumb32_opcodes): Add new instructions.
1604         (enum mve_instructions): Likewise.
1605         (is_mve_encoding_conflict): Handle new instructions.
1606         (is_mve_undefined): Likewise.
1607         (is_mve_unpredictable): Likewise.
1608         (print_mve_size): Likewise.
1609
1610 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1611             Michael Collison <michael.collison@arm.com>
1612
1613         * arm-dis.c (thumb32_opcodes): Add new instructions.
1614         (enum mve_instructions): Likewise.
1615         (is_mve_encoding_conflict): Handle new instructions.
1616         (is_mve_undefined): Likewise.
1617         (is_mve_unpredictable): Likewise.
1618         (print_mve_size): Likewise.
1619         (print_insn_mve): Likewise.
1620
1621 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1622             Michael Collison <michael.collison@arm.com>
1623
1624         * arm-dis.c (thumb32_opcodes): Add new instructions.
1625         (print_insn_thumb32): Handle new instructions.
1626
1627 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1628             Michael Collison <michael.collison@arm.com>
1629
1630         * arm-dis.c (enum mve_instructions): Add new instructions.
1631         (enum mve_undefined): Add new reasons.
1632         (is_mve_encoding_conflict): Handle new instructions.
1633         (is_mve_undefined): Likewise.
1634         (is_mve_unpredictable): Likewise.
1635         (print_mve_undefined): Likewise.
1636         (print_mve_size): Likewise.
1637         (print_mve_shift_n): Likewise.
1638         (print_insn_mve): Likewise.
1639
1640 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1641             Michael Collison <michael.collison@arm.com>
1642
1643         * arm-dis.c (enum mve_instructions): Add new instructions.
1644         (is_mve_encoding_conflict): Handle new instructions.
1645         (is_mve_unpredictable): Likewise.
1646         (print_mve_rotate): Likewise.
1647         (print_mve_size): Likewise.
1648         (print_insn_mve): Likewise.
1649
1650 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1651             Michael Collison <michael.collison@arm.com>
1652
1653         * arm-dis.c (enum mve_instructions): Add new instructions.
1654         (is_mve_encoding_conflict): Handle new instructions.
1655         (is_mve_unpredictable): Likewise.
1656         (print_mve_size): Likewise.
1657         (print_insn_mve): Likewise.
1658
1659 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1660             Michael Collison <michael.collison@arm.com>
1661
1662         * arm-dis.c (enum mve_instructions): Add new instructions.
1663         (enum mve_undefined): Add new reasons.
1664         (is_mve_encoding_conflict): Handle new instructions.
1665         (is_mve_undefined): Likewise.
1666         (is_mve_unpredictable): Likewise.
1667         (print_mve_undefined): Likewise.
1668         (print_mve_size): Likewise.
1669         (print_insn_mve): Likewise.
1670
1671 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1672             Michael Collison <michael.collison@arm.com>
1673
1674         * arm-dis.c (enum mve_instructions): Add new instructions.
1675         (is_mve_encoding_conflict): Handle new instructions.
1676         (is_mve_undefined): Likewise.
1677         (is_mve_unpredictable): Likewise.
1678         (print_mve_size): Likewise.
1679         (print_insn_mve): Likewise.
1680
1681 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1682             Michael Collison <michael.collison@arm.com>
1683
1684         * arm-dis.c (enum mve_instructions): Add new instructions.
1685         (enum mve_unpredictable): Add new reasons.
1686         (enum mve_undefined): Likewise.
1687         (is_mve_okay_in_it): Handle new isntructions.
1688         (is_mve_encoding_conflict): Likewise.
1689         (is_mve_undefined): Likewise.
1690         (is_mve_unpredictable): Likewise.
1691         (print_mve_vmov_index): Likewise.
1692         (print_simd_imm8): Likewise.
1693         (print_mve_undefined): Likewise.
1694         (print_mve_unpredictable): Likewise.
1695         (print_mve_size): Likewise.
1696         (print_insn_mve): Likewise.
1697
1698 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1699             Michael Collison <michael.collison@arm.com>
1700
1701         * arm-dis.c (enum mve_instructions): Add new instructions.
1702         (enum mve_unpredictable): Add new reasons.
1703         (enum mve_undefined): Likewise.
1704         (is_mve_encoding_conflict): Handle new instructions.
1705         (is_mve_undefined): Likewise.
1706         (is_mve_unpredictable): Likewise.
1707         (print_mve_undefined): Likewise.
1708         (print_mve_unpredictable): Likewise.
1709         (print_mve_rounding_mode): Likewise.
1710         (print_mve_vcvt_size): Likewise.
1711         (print_mve_size): Likewise.
1712         (print_insn_mve): Likewise.
1713
1714 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1715             Michael Collison <michael.collison@arm.com>
1716
1717         * arm-dis.c (enum mve_instructions): Add new instructions.
1718         (enum mve_unpredictable): Add new reasons.
1719         (enum mve_undefined): Likewise.
1720         (is_mve_undefined): Handle new instructions.
1721         (is_mve_unpredictable): Likewise.
1722         (print_mve_undefined): Likewise.
1723         (print_mve_unpredictable): Likewise.
1724         (print_mve_size): Likewise.
1725         (print_insn_mve): Likewise.
1726
1727 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1728             Michael Collison <michael.collison@arm.com>
1729
1730         * arm-dis.c (enum mve_instructions): Add new instructions.
1731         (enum mve_undefined): Add new reasons.
1732         (insns): Add new instructions.
1733         (is_mve_encoding_conflict):
1734         (print_mve_vld_str_addr): New print function.
1735         (is_mve_undefined): Handle new instructions.
1736         (is_mve_unpredictable): Likewise.
1737         (print_mve_undefined): Likewise.
1738         (print_mve_size): Likewise.
1739         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1740         (print_insn_mve):  Handle new operands.
1741
1742 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1743             Michael Collison <michael.collison@arm.com>
1744
1745         * arm-dis.c (enum mve_instructions): Add new instructions.
1746         (enum mve_unpredictable): Add new reasons.
1747         (is_mve_encoding_conflict): Handle new instructions.
1748         (is_mve_unpredictable): Likewise.
1749         (mve_opcodes): Add new instructions.
1750         (print_mve_unpredictable): Handle new reasons.
1751         (print_mve_register_blocks): New print function.
1752         (print_mve_size): Handle new instructions.
1753         (print_insn_mve): Likewise.
1754
1755 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1756             Michael Collison <michael.collison@arm.com>
1757
1758         * arm-dis.c (enum mve_instructions): Add new instructions.
1759         (enum mve_unpredictable): Add new reasons.
1760         (enum mve_undefined): Likewise.
1761         (is_mve_encoding_conflict): Handle new instructions.
1762         (is_mve_undefined): Likewise.
1763         (is_mve_unpredictable): Likewise.
1764         (coprocessor_opcodes): Move NEON VDUP from here...
1765         (neon_opcodes): ... to here.
1766         (mve_opcodes): Add new instructions.
1767         (print_mve_undefined):  Handle new reasons.
1768         (print_mve_unpredictable): Likewise.
1769         (print_mve_size): Handle new instructions.
1770         (print_insn_neon): Handle vdup.
1771         (print_insn_mve): Handle new operands.
1772
1773 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1774             Michael Collison <michael.collison@arm.com>
1775
1776         * arm-dis.c (enum mve_instructions): Add new instructions.
1777         (enum mve_unpredictable): Add new values.
1778         (mve_opcodes): Add new instructions.
1779         (vec_condnames): New array with vector conditions.
1780         (mve_predicatenames): New array with predicate suffixes.
1781         (mve_vec_sizename): New array with vector sizes.
1782         (enum vpt_pred_state): New enum with vector predication states.
1783         (struct vpt_block): New struct type for vpt blocks.
1784         (vpt_block_state): Global struct to keep track of state.
1785         (mve_extract_pred_mask): New helper function.
1786         (num_instructions_vpt_block): Likewise.
1787         (mark_outside_vpt_block): Likewise.
1788         (mark_inside_vpt_block): Likewise.
1789         (invert_next_predicate_state): Likewise.
1790         (update_next_predicate_state): Likewise.
1791         (update_vpt_block_state): Likewise.
1792         (is_vpt_instruction): Likewise.
1793         (is_mve_encoding_conflict): Add entries for new instructions.
1794         (is_mve_unpredictable): Likewise.
1795         (print_mve_unpredictable): Handle new cases.
1796         (print_instruction_predicate): Likewise.
1797         (print_mve_size): New function.
1798         (print_vec_condition): New function.
1799         (print_insn_mve): Handle vpt blocks and new print operands.
1800
1801 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1802
1803         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1804         8, 14 and 15 for Armv8.1-M Mainline.
1805
1806 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1807             Michael Collison <michael.collison@arm.com>
1808
1809         * arm-dis.c (enum mve_instructions): New enum.
1810         (enum mve_unpredictable): Likewise.
1811         (enum mve_undefined): Likewise.
1812         (struct mopcode32): New struct.
1813         (is_mve_okay_in_it): New function.
1814         (is_mve_architecture): Likewise.
1815         (arm_decode_field): Likewise.
1816         (arm_decode_field_multiple): Likewise.
1817         (is_mve_encoding_conflict): Likewise.
1818         (is_mve_undefined): Likewise.
1819         (is_mve_unpredictable): Likewise.
1820         (print_mve_undefined): Likewise.
1821         (print_mve_unpredictable): Likewise.
1822         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1823         (print_insn_mve): New function.
1824         (print_insn_thumb32): Handle MVE architecture.
1825         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1826
1827 2019-05-10  Nick Clifton  <nickc@redhat.com>
1828
1829         PR 24538
1830         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1831         end of the table prematurely.
1832
1833 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1834
1835         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1836         macros for R6.
1837
1838 2019-05-11  Alan Modra  <amodra@gmail.com>
1839
1840         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1841         when -Mraw is in effect.
1842
1843 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1844
1845         * aarch64-dis-2.c: Regenerate.
1846         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1847         (OP_SVE_BBB): New variant set.
1848         (OP_SVE_DDDD): New variant set.
1849         (OP_SVE_HHH): New variant set.
1850         (OP_SVE_HHHU): New variant set.
1851         (OP_SVE_SSS): New variant set.
1852         (OP_SVE_SSSU): New variant set.
1853         (OP_SVE_SHH): New variant set.
1854         (OP_SVE_SBBU): New variant set.
1855         (OP_SVE_DSS): New variant set.
1856         (OP_SVE_DHHU): New variant set.
1857         (OP_SVE_VMV_HSD_BHS): New variant set.
1858         (OP_SVE_VVU_HSD_BHS): New variant set.
1859         (OP_SVE_VVVU_SD_BH): New variant set.
1860         (OP_SVE_VVVU_BHSD): New variant set.
1861         (OP_SVE_VVV_QHD_DBS): New variant set.
1862         (OP_SVE_VVV_HSD_BHS): New variant set.
1863         (OP_SVE_VVV_HSD_BHS2): New variant set.
1864         (OP_SVE_VVV_BHS_HSD): New variant set.
1865         (OP_SVE_VV_BHS_HSD): New variant set.
1866         (OP_SVE_VVV_SD): New variant set.
1867         (OP_SVE_VVU_BHS_HSD): New variant set.
1868         (OP_SVE_VZVV_SD): New variant set.
1869         (OP_SVE_VZVV_BH): New variant set.
1870         (OP_SVE_VZV_SD): New variant set.
1871         (aarch64_opcode_table): Add sve2 instructions.
1872
1873 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1874
1875         * aarch64-asm-2.c: Regenerated.
1876         * aarch64-dis-2.c: Regenerated.
1877         * aarch64-opc-2.c: Regenerated.
1878         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1879         for SVE_SHLIMM_UNPRED_22.
1880         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1881         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1882         operand.
1883
1884 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1885
1886         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1887         sve_size_tsz_bhs iclass encode.
1888         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1889         sve_size_tsz_bhs iclass decode.
1890
1891 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1892
1893         * aarch64-asm-2.c: Regenerated.
1894         * aarch64-dis-2.c: Regenerated.
1895         * aarch64-opc-2.c: Regenerated.
1896         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1897         for SVE_Zm4_11_INDEX.
1898         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1899         (fields): Handle SVE_i2h field.
1900         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1901         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1902
1903 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1904
1905         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1906         sve_shift_tsz_bhsd iclass encode.
1907         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1908         sve_shift_tsz_bhsd iclass decode.
1909
1910 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1911
1912         * aarch64-asm-2.c: Regenerated.
1913         * aarch64-dis-2.c: Regenerated.
1914         * aarch64-opc-2.c: Regenerated.
1915         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1916         (aarch64_encode_variant_using_iclass): Handle
1917         sve_shift_tsz_hsd iclass encode.
1918         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1919         sve_shift_tsz_hsd iclass decode.
1920         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1921         for SVE_SHRIMM_UNPRED_22.
1922         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1923         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1924         operand.
1925
1926 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1927
1928         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1929         sve_size_013 iclass encode.
1930         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1931         sve_size_013 iclass decode.
1932
1933 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1934
1935         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1936         sve_size_bh iclass encode.
1937         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1938         sve_size_bh iclass decode.
1939
1940 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1941
1942         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1943         sve_size_sd2 iclass encode.
1944         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1945         sve_size_sd2 iclass decode.
1946         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1947         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1948
1949 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1950
1951         * aarch64-asm-2.c: Regenerated.
1952         * aarch64-dis-2.c: Regenerated.
1953         * aarch64-opc-2.c: Regenerated.
1954         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1955         for SVE_ADDR_ZX.
1956         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1957         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1958
1959 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1960
1961         * aarch64-asm-2.c: Regenerated.
1962         * aarch64-dis-2.c: Regenerated.
1963         * aarch64-opc-2.c: Regenerated.
1964         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1965         for SVE_Zm3_11_INDEX.
1966         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1967         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1968         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1969         fields.
1970         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1971
1972 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1973
1974         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1975         sve_size_hsd2 iclass encode.
1976         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1977         sve_size_hsd2 iclass decode.
1978         * aarch64-opc.c (fields): Handle SVE_size field.
1979         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1980
1981 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1982
1983         * aarch64-asm-2.c: Regenerated.
1984         * aarch64-dis-2.c: Regenerated.
1985         * aarch64-opc-2.c: Regenerated.
1986         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1987         for SVE_IMM_ROT3.
1988         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1989         (fields): Handle SVE_rot3 field.
1990         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1991         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1992
1993 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1994
1995         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1996         instructions.
1997
1998 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1999
2000         * aarch64-tbl.h
2001         (aarch64_feature_sve2, aarch64_feature_sve2aes,
2002         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
2003         aarch64_feature_sve2bitperm): New feature sets.
2004         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
2005         for feature set addresses.
2006         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
2007         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2008
2009 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
2010             Faraz Shahbazker  <fshahbazker@wavecomp.com>
2011
2012         * mips-dis.c (mips_calculate_combination_ases): Add ISA
2013         argument and set ASE_EVA_R6 appropriately.
2014         (set_default_mips_dis_options): Pass ISA to above.
2015         (parse_mips_dis_option): Likewise.
2016         * mips-opc.c (EVAR6): New macro.
2017         (mips_builtin_opcodes): Add llwpe, scwpe.
2018
2019 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
2020
2021         * aarch64-asm-2.c: Regenerated.
2022         * aarch64-dis-2.c: Regenerated.
2023         * aarch64-opc-2.c: Regenerated.
2024         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
2025         AARCH64_OPND_TME_UIMM16.
2026         (aarch64_print_operand): Likewise.
2027         * aarch64-tbl.h (QL_IMM_NIL): New.
2028         (TME): New.
2029         (_TME_INSN): New.
2030         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2031
2032 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
2033
2034         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
2035
2036 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
2037             Faraz Shahbazker  <fshahbazker@wavecomp.com>
2038
2039         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2040
2041 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
2042
2043         * s12z-opc.h: Add extern "C" bracketing to help
2044         users who wish to use this interface in c++ code.
2045
2046 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
2047
2048         * s12z-opc.c (bm_decode): Handle bit map operations with the
2049         "reserved0" mode.
2050
2051 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2052
2053         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2054         specifier.  Add entries for VLDR and VSTR of system registers.
2055         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2056         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
2057         of %J and %K format specifier.
2058
2059 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2060
2061         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2062         Add new entries for VSCCLRM instruction.
2063         (print_insn_coprocessor): Handle new %C format control code.
2064
2065 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2066
2067         * arm-dis.c (enum isa): New enum.
2068         (struct sopcode32): New structure.
2069         (coprocessor_opcodes): change type of entries to struct sopcode32 and
2070         set isa field of all current entries to ANY.
2071         (print_insn_coprocessor): Change type of insn to struct sopcode32.
2072         Only match an entry if its isa field allows the current mode.
2073
2074 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2075
2076         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
2077         CLRM.
2078         (print_insn_thumb32): Add logic to print %n CLRM register list.
2079
2080 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2081
2082         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2083         and %Q patterns.
2084
2085 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2086
2087         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2088         (print_insn_thumb32): Edit the switch case for %Z.
2089
2090 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2091
2092         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2093
2094 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2095
2096         * arm-dis.c (thumb32_opcodes): New instruction bfl.
2097
2098 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2099
2100         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2101
2102 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2103
2104         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2105         Arm register with r13 and r15 unpredictable.
2106         (thumb32_opcodes): New instructions for bfx and bflx.
2107
2108 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2109
2110         * arm-dis.c (thumb32_opcodes): New instructions for bf.
2111
2112 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2113
2114         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2115
2116 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2117
2118         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2119
2120 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2121
2122         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2123
2124 2019-04-12  John Darrington <john@darrington.wattle.id.au>
2125
2126         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2127         "optr". ("operator" is a reserved word in c++).
2128
2129 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2130
2131         * aarch64-opc.c (aarch64_print_operand): Add case for
2132         AARCH64_OPND_Rt_SP.
2133         (verify_constraints): Likewise.
2134         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2135         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2136         to accept Rt|SP as first operand.
2137         (AARCH64_OPERANDS): Add new Rt_SP.
2138         * aarch64-asm-2.c: Regenerated.
2139         * aarch64-dis-2.c: Regenerated.
2140         * aarch64-opc-2.c: Regenerated.
2141
2142 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2143
2144         * aarch64-asm-2.c: Regenerated.
2145         * aarch64-dis-2.c: Likewise.
2146         * aarch64-opc-2.c: Likewise.
2147         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2148
2149 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
2150
2151         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2152
2153 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
2154
2155         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2156         * i386-init.h: Regenerated.
2157
2158 2019-04-07  Alan Modra  <amodra@gmail.com>
2159
2160         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2161         op_separator to control printing of spaces, comma and parens
2162         rather than need_comma, need_paren and spaces vars.
2163
2164 2019-04-07  Alan Modra  <amodra@gmail.com>
2165
2166         PR 24421
2167         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2168         (print_insn_neon, print_insn_arm): Likewise.
2169
2170 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
2171
2172         * i386-dis-evex.h (evex_table): Updated to support BF16
2173         instructions.
2174         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2175         and EVEX_W_0F3872_P_3.
2176         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2177         (cpu_flags): Add bitfield for CpuAVX512_BF16.
2178         * i386-opc.h (enum): Add CpuAVX512_BF16.
2179         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2180         * i386-opc.tbl: Add AVX512 BF16 instructions.
2181         * i386-init.h: Regenerated.
2182         * i386-tbl.h: Likewise.
2183
2184 2019-04-05  Alan Modra  <amodra@gmail.com>
2185
2186         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2187         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2188         to favour printing of "-" branch hint when using the "y" bit.
2189         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2190
2191 2019-04-05  Alan Modra  <amodra@gmail.com>
2192
2193         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2194         opcode until first operand is output.
2195
2196 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2197
2198         PR gas/24349
2199         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2200         (valid_bo_post_v2): Add support for 'at' branch hints.
2201         (insert_bo): Only error on branch on ctr.
2202         (get_bo_hint_mask): New function.
2203         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2204         for inserting 'at' branch hints.
2205         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2206         for extracting 'at' branch hints.
2207         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2208         (BOE): Delete operand.
2209         (BOM, BOP): New operands.
2210         (RM): Update value.
2211         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2212         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2213         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2214         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2215         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2216         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2217         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2218         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2219         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2220         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2221         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2222         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2223         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2224         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2225         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2226         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2227         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2228         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2229         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2230         bttarl+>: New extended mnemonics.
2231
2232 2019-03-28  Alan Modra  <amodra@gmail.com>
2233
2234         PR 24390
2235         * ppc-opc.c (BTF): Define.
2236         (powerpc_opcodes): Use for mtfsb*.
2237         * ppc-dis.c (print_insn_powerpc): Print fields with both
2238         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2239
2240 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2241
2242         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2243         (mapping_symbol_for_insn): Implement new algorithm.
2244         (print_insn): Remove duplicate code.
2245
2246 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2247
2248         * aarch64-dis.c (print_insn_aarch64):
2249         Implement override.
2250
2251 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2252
2253         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2254         order.
2255
2256 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2257
2258         * aarch64-dis.c (last_stop_offset): New.
2259         (print_insn_aarch64): Use stop_offset.
2260
2261 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2262
2263         PR gas/24359
2264         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2265         CPU_ANY_AVX2_FLAGS.
2266         * i386-init.h: Regenerated.
2267
2268 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2269
2270         PR gas/24348
2271         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2272         vmovdqu16, vmovdqu32 and vmovdqu64.
2273         * i386-tbl.h: Regenerated.
2274
2275 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2276
2277         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2278         from vstrszb, vstrszh, and vstrszf.
2279
2280 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2281
2282         * s390-opc.txt: Add instruction descriptions.
2283
2284 2019-02-08  Jim Wilson  <jimw@sifive.com>
2285
2286         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2287         <bne>: Likewise.
2288
2289 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2290
2291         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2292
2293 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2294
2295         PR binutils/23212
2296         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2297         * aarch64-opc.c (verify_elem_sd): New.
2298         (fields): Add FLD_sz entr.
2299         * aarch64-tbl.h (_SIMD_INSN): New.
2300         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2301         fmulx scalar and vector by element isns.
2302
2303 2019-02-07  Nick Clifton  <nickc@redhat.com>
2304
2305         * po/sv.po: Updated Swedish translation.
2306
2307 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2308
2309         * s390-mkopc.c (main): Accept arch13 as cpu string.
2310         * s390-opc.c: Add new instruction formats and instruction opcode
2311         masks.
2312         * s390-opc.txt: Add new arch13 instructions.
2313
2314 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2315
2316         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2317         (aarch64_opcode): Change encoding for stg, stzg
2318         st2g and st2zg.
2319         * aarch64-asm-2.c: Regenerated.
2320         * aarch64-dis-2.c: Regenerated.
2321         * aarch64-opc-2.c: Regenerated.
2322
2323 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2324
2325         * aarch64-asm-2.c: Regenerated.
2326         * aarch64-dis-2.c: Likewise.
2327         * aarch64-opc-2.c: Likewise.
2328         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2329
2330 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2331             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2332
2333         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2334         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2335         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2336         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2337         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2338         case for ldstgv_indexed.
2339         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2340         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2341         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2342         * aarch64-asm-2.c: Regenerated.
2343         * aarch64-dis-2.c: Regenerated.
2344         * aarch64-opc-2.c: Regenerated.
2345
2346 2019-01-23  Nick Clifton  <nickc@redhat.com>
2347
2348         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2349
2350 2019-01-21  Nick Clifton  <nickc@redhat.com>
2351
2352         * po/de.po: Updated German translation.
2353         * po/uk.po: Updated Ukranian translation.
2354
2355 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2356         * mips-dis.c (mips_arch_choices): Fix typo in
2357         gs464, gs464e and gs264e descriptors.
2358
2359 2019-01-19  Nick Clifton  <nickc@redhat.com>
2360
2361         * configure: Regenerate.
2362         * po/opcodes.pot: Regenerate.
2363
2364 2018-06-24  Nick Clifton  <nickc@redhat.com>
2365
2366         2.32 branch created.
2367
2368 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2369
2370         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2371         if it is null.
2372         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2373         zero.
2374
2375 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2376
2377         * configure: Regenerate.
2378
2379 2019-01-07  Alan Modra  <amodra@gmail.com>
2380
2381         * configure: Regenerate.
2382         * po/POTFILES.in: Regenerate.
2383
2384 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2385
2386         * s12z-opc.c: New file.
2387         * s12z-opc.h: New file.
2388         * s12z-dis.c: Removed all code not directly related to display
2389         of instructions.  Used the interface provided by the new files
2390         instead.
2391         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2392         * Makefile.in: Regenerate.
2393         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2394         * configure: Regenerate.
2395
2396 2019-01-01  Alan Modra  <amodra@gmail.com>
2397
2398         Update year range in copyright notice of all files.
2399
2400 For older changes see ChangeLog-2018
2401 \f
2402 Copyright (C) 2019 Free Software Foundation, Inc.
2403
2404 Copying and distribution of this file, with or without modification,
2405 are permitted in any medium without royalty provided the copyright
2406 notice and this notice are preserved.
2407
2408 Local Variables:
2409 mode: change-log
2410 left-margin: 8
2411 fill-column: 74
2412 version-control: never
2413 End: