opcodes/ChangeLog

   1 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
   2
   3         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
   4         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
   5         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
   6
   7 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
   8
   9         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
  10         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
  11         (aarch64_sys_reg_supported_p): Update checks for the above.
  12
  13 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
  14
  15         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
  16         cases MVE_SQRSHRL and MVE_UQRSHLL.
  17         (print_insn_mve): Add case for specifier 'k' to check
  18         specific bit of the instruction.
  19
  20 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
  21
  22         PR 24854
  23         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
  24         encountering an unknown machine type.
  25         (print_insn_arc): Handle arc_insn_length returning 0.  In error
  26         cases return -1 rather than calling abort.
  27
  28 2019-08-07  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
  31         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
  32         IgnoreSize.
  33         * i386-tbl.h: Re-generate.
  34
  35 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
  36
  37         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
  38         instructions.
  39
  40 2019-07-30  Mel Chen <mel.chen@sifive.com>
  41
  42         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
  43         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
  44
  45         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
  46         fscsr.
  47
  48 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
  49
  50         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
  51         and MPY class instructions.
  52         (parse_option): Add nps400 option.
  53         (print_arc_disassembler_options): Add nps400 info.
  54
  55 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
  56
  57         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
  58         (bspop): Likewise.
  59         (modapp): Likewise.
  60         * arc-opc.c (RAD_CHK): Add.
  61         * arc-tbl.h: Regenerate.
  62
  63 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  64
  65         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
  66         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
  67
  68 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
  69
  70         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
  71         instructions as UNPREDICTABLE.
  72
  73 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
  74
  75         * bpf-desc.c: Regenerated.
  76
  77 2019-07-17  Jan Beulich  <jbeulich@suse.com>
  78
  79         * i386-gen.c (static_assert): Define.
  80         (main): Use it.
  81         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
  82         (Opcode_Modifier_Num): ... this.
  83         (Mem): Delete.
  84
  85 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-gen.c (operand_types): Move RegMem ...
  88         (opcode_modifiers): ... here.
  89         * i386-opc.h (RegMem): Move to opcode modifer enum.
  90         (union i386_operand_type): Move regmem field ...
  91         (struct i386_opcode_modifier): ... here.
  92         * i386-opc.tbl (RegMem): Define.
  93         (mov, movq): Move RegMem on segment, control, debug, and test
  94         register flavors.
  95         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
  96         to non-SSE2AVX flavor.
  97         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
  98         Move RegMem on register only flavors. Drop IgnoreSize from
  99         legacy encoding flavors.
 100         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 101         flavors.
 102         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 103         register only flavors.
 104         (vmovd): Move RegMem and drop IgnoreSize on register only
 105         flavor. Change opcode and operand order to store form.
 106         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 107
 108 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 109
 110         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 111         entries.
 112         * i386-opc.h (SReg2, SReg3): Replace by ...
 113         (SReg): ... this.
 114         (union i386_operand_type): Replace sreg fields.
 115         * i386-opc.tbl (mov, ): Use SReg.
 116         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 117         register flavors.
 118         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 119         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 120
 121 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 122
 123         * bpf-desc.c: Regenerate.
 124         * bpf-opc.c: Likewise.
 125         * bpf-opc.h: Likewise.
 126
 127 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 128
 129         * bpf-desc.c: Regenerate.
 130         * bpf-opc.c: Likewise.
 131
 132 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 133
 134         * arm-dis.c (print_insn_coprocessor): Rename index to
 135         index_operand.
 136
 137 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 138
 139         * riscv-opc.c (riscv_insn_types): Add r4 type.
 140
 141         * riscv-opc.c (riscv_insn_types): Add b and j type.
 142
 143         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 144         format for sb type and correct s type.
 145
 146 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 147
 148         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 149         SVE FMOV alias of FCPY.
 150
 151 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 152
 153         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 154         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 155
 156 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 157
 158         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 159         registers in an instruction prefixed by MOVPRFX.
 160
 161 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 162
 163         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 164         sve_size_13 icode to account for variant behaviour of
 165         pmull{t,b}.
 166         * aarch64-dis-2.c: Regenerate.
 167         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 168         sve_size_13 icode to account for variant behaviour of
 169         pmull{t,b}.
 170         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 171         (OP_SVE_VVV_Q_D): Add new qualifier.
 172         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 173         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 174         AES and those not.
 175
 176 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 177
 178         * opcodes/i386-gen.c (operand_type_init): Remove
 179         OPERAND_TYPE_VEC_IMM4 entry.
 180         (operand_types): Remove Vec_Imm4.
 181         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 182         (union i386_operand_type): Remove vec_imm4.
 183         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 184         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 185
 186 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 187
 188         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 189         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 190         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 191         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 192         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 193         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 194         * i386-tbl.h: Re-generate.
 195
 196 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 197
 198         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 199         register operands.
 200         * i386-tbl.h: Re-generate.
 201
 202 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 203
 204         * i386-opc.tbl (C): New.
 205         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 206         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 207         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 208         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 209         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 210         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 211         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 212         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 213         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 214         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 215         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 216         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 217         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 218         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 219         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 220         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 221         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 222         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 223         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 224         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 225         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 226         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 227         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 228         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 229         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 230         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 231         flavors.
 232         * i386-tbl.h: Re-generate.
 233
 234 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 235
 236         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 237         register operands.
 238         * i386-tbl.h: Re-generate.
 239
 240 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 241
 242         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 243         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 244         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 245         * i386-tbl.h: Re-generate.
 246
 247 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 248
 249         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 250         Disp8MemShift from register only templates.
 251         * i386-tbl.h: Re-generate.
 252
 253 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 254
 255         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 256         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 257         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 258         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 259         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 260         EVEX_W_0F11_P_3_M_1): Delete.
 261         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 262         EVEX_W_0F11_P_3): New.
 263         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 264         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 265         MOD_EVEX_0F11_PREFIX_3 table entries.
 266         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 267         PREFIX_EVEX_0F11 table entries.
 268         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 269         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 270         EVEX_W_0F11_P_3_M_{0,1} table entries.
 271
 272 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 273
 274         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 275         Delete.
 276
 277 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 278
 279         PR binutils/24719
 280         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 281         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 282         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 283         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 284         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 285         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 286         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 287         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 288         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 289         PREFIX_EVEX_0F38C6_REG_6 entries.
 290         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 291         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 292         EVEX_W_0F38C7_R_6_P_2 entries.
 293         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 294         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 295         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 296         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 297         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 298         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 299         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 300
 301 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 302
 303         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 304         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 305         VEX_LEN_0F2D_P_3): Delete.
 306         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 307         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 308         (prefix_table): ... here.
 309
 310 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 311
 312         * i386-dis.c (Iq): Delete.
 313         (Id): New.
 314         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 315         TBM insns.
 316         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 317         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 318         (OP_E_memory): Also honor needindex when deciding whether an
 319         address size prefix needs printing.
 320         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 321
 322 2019-06-26  Jim Wilson  <jimw@sifive.com>
 323
 324         PR binutils/24739
 325         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 326         Set info->display_endian to info->endian_code.
 327
 328 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 329
 330         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 331         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 332         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 333         OPERAND_TYPE_ACC64 entries.
 334         * i386-init.h: Re-generate.
 335
 336 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 339         Delete.
 340         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 341         of dqa_mode.
 342         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 343         entries here.
 344         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 345         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 346
 347 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 348
 349         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 350         variables.
 351
 352 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 353
 354         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 355         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 356         movnti.
 357         * i386-opc.tbl (movnti): Add IgnoreSize.
 358         * i386-tbl.h: Re-generate.
 359
 360 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 361
 362         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 363         * i386-tbl.h: Re-generate.
 364
 365 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 366
 367         * i386-dis-evex.h: Break into ...
 368         * i386-dis-evex-len.h: New file.
 369         * i386-dis-evex-mod.h: Likewise.
 370         * i386-dis-evex-prefix.h: Likewise.
 371         * i386-dis-evex-reg.h: Likewise.
 372         * i386-dis-evex-w.h: Likewise.
 373         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 374         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 375         i386-dis-evex-mod.h.
 376
 377 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 378
 379         PR binutils/24700
 380         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 381         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 382         EVEX_W_0F385B_P_2.
 383         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 384         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 385         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 386         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 387         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 388         EVEX_LEN_0F385B_P_2_W_1.
 389         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 390         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 391         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 392         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 393         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 394         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 395         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 396         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 397         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 398         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 399
 400 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 401
 402         PR binutils/24691
 403         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 404         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 405         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 406         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 407         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 408         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 409         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 410         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 411         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 412         EVEX_LEN_0F3A43_P_2_W_1.
 413         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 414         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 415         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 416         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 417         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 418         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 419         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 420         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 421         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 422         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 423         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 424         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 425
 426 2019-06-14  Nick Clifton  <nickc@redhat.com>
 427
 428         * po/fr.po; Updated French translation.
 429
 430 2019-06-13  Stafford Horne  <shorne@gmail.com>
 431
 432         * or1k-asm.c: Regenerated.
 433         * or1k-desc.c: Regenerated.
 434         * or1k-desc.h: Regenerated.
 435         * or1k-dis.c: Regenerated.
 436         * or1k-ibld.c: Regenerated.
 437         * or1k-opc.c: Regenerated.
 438         * or1k-opc.h: Regenerated.
 439         * or1k-opinst.c: Regenerated.
 440
 441 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 442
 443         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 444
 445 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 446
 447         PR binutils/24633
 448         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 449         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 450         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 451         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 452         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 453         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 454         EVEX_LEN_0F3A1B_P_2_W_1.
 455         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 456         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 457         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 458         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 459         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 460         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 461         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 462         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 463
 464 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 465
 466         PR binutils/24626
 467         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 468         EVEX.vvvv when disassembling VEX and EVEX instructions.
 469         (OP_VEX): Set vex.register_specifier to 0 after readding
 470         vex.register_specifier.
 471         (OP_Vex_2src_1): Likewise.
 472         (OP_Vex_2src_2): Likewise.
 473         (OP_LWP_E): Likewise.
 474         (OP_EX_Vex): Don't check vex.register_specifier.
 475         (OP_XMM_Vex): Likewise.
 476
 477 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 478             Lili Cui  <lili.cui@intel.com>
 479
 480         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 481         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 482         instructions.
 483         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 484         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 485         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 486         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 487         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 488         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 489         * i386-init.h: Regenerated.
 490         * i386-tbl.h: Likewise.
 491
 492 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 493             Lili Cui  <lili.cui@intel.com>
 494
 495         * doc/c-i386.texi: Document enqcmd.
 496         * testsuite/gas/i386/enqcmd-intel.d: New file.
 497         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 498         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 499         * testsuite/gas/i386/enqcmd.d: Likewise.
 500         * testsuite/gas/i386/enqcmd.s: Likewise.
 501         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 502         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 503         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 504         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 505         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 506         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 507         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 508         and x86-64-enqcmd.
 509
 510 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 511
 512         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 513
 514 2019-06-03  Alan Modra  <amodra@gmail.com>
 515
 516         * ppc-dis.c (prefix_opcd_indices): Correct size.
 517
 518 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 519
 520         PR gas/24625
 521         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 522         Disp8ShiftVL.
 523         * i386-tbl.h: Regenerated.
 524
 525 2019-05-24  Alan Modra  <amodra@gmail.com>
 526
 527         * po/POTFILES.in: Regenerate.
 528
 529 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 530             Alan Modra  <amodra@gmail.com>
 531
 532         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 533         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 534         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 535         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 536         XTOP>): Define and add entries.
 537         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 538         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 539         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 540         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 541
 542 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 543             Alan Modra  <amodra@gmail.com>
 544
 545         * ppc-dis.c (ppc_opts): Add "future" entry.
 546         (PREFIX_OPCD_SEGS): Define.
 547         (prefix_opcd_indices): New array.
 548         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 549         (lookup_prefix): New function.
 550         (print_insn_powerpc): Handle 64-bit prefix instructions.
 551         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 552         (PMRR, POWERXX): Define.
 553         (prefix_opcodes): New instruction table.
 554         (prefix_num_opcodes): New constant.
 555
 556 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 557
 558         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 559         * configure: Regenerated.
 560         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 561         and cpu/bpf.opc.
 562         (HFILES): Add bpf-desc.h and bpf-opc.h.
 563         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 564         bpf-ibld.c and bpf-opc.c.
 565         (BPF_DEPS): Define.
 566         * Makefile.in: Regenerated.
 567         * disassemble.c (ARCH_bpf): Define.
 568         (disassembler): Add case for bfd_arch_bpf.
 569         (disassemble_init_for_target): Likewise.
 570         (enum epbf_isa_attr): Define.
 571         * disassemble.h: extern print_insn_bpf.
 572         * bpf-asm.c: Generated.
 573         * bpf-opc.h: Likewise.
 574         * bpf-opc.c: Likewise.
 575         * bpf-ibld.c: Likewise.
 576         * bpf-dis.c: Likewise.
 577         * bpf-desc.h: Likewise.
 578         * bpf-desc.c: Likewise.
 579
 580 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 581
 582         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 583         and VMSR with the new operands.
 584
 585 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 586
 587         * arm-dis.c (enum mve_instructions): New enum
 588         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 589         and cneg.
 590         (mve_opcodes): New instructions as above.
 591         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 592         csneg and csel.
 593         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 594
 595 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 596
 597         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 598         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 599         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 600         uqshl, urshrl and urshr.
 601         (is_mve_okay_in_it): Add new instructions to TRUE list.
 602         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 603         (print_insn_mve): Updated to accept new %j,
 604         %<bitfield>m and %<bitfield>n patterns.
 605
 606 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 607
 608         * mips-opc.c (mips_builtin_opcodes): Change source register
 609         constraint for DAUI.
 610
 611 2019-05-20  Nick Clifton  <nickc@redhat.com>
 612
 613         * po/fr.po: Updated French translation.
 614
 615 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 616             Michael Collison <michael.collison@arm.com>
 617
 618         * arm-dis.c (thumb32_opcodes): Add new instructions.
 619         (enum mve_instructions): Likewise.
 620         (enum mve_undefined): Add new reasons.
 621         (is_mve_encoding_conflict): Handle new instructions.
 622         (is_mve_undefined): Likewise.
 623         (is_mve_unpredictable): Likewise.
 624         (print_mve_undefined): Likewise.
 625         (print_mve_size): Likewise.
 626
 627 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 628             Michael Collison <michael.collison@arm.com>
 629
 630         * arm-dis.c (thumb32_opcodes): Add new instructions.
 631         (enum mve_instructions): Likewise.
 632         (is_mve_encoding_conflict): Handle new instructions.
 633         (is_mve_undefined): Likewise.
 634         (is_mve_unpredictable): Likewise.
 635         (print_mve_size): Likewise.
 636
 637 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 638             Michael Collison <michael.collison@arm.com>
 639
 640         * arm-dis.c (thumb32_opcodes): Add new instructions.
 641         (enum mve_instructions): Likewise.
 642         (is_mve_encoding_conflict): Likewise.
 643         (is_mve_unpredictable): Likewise.
 644         (print_mve_size): Likewise.
 645
 646 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 647             Michael Collison <michael.collison@arm.com>
 648
 649         * arm-dis.c (thumb32_opcodes): Add new instructions.
 650         (enum mve_instructions): Likewise.
 651         (is_mve_encoding_conflict): Handle new instructions.
 652         (is_mve_undefined): Likewise.
 653         (is_mve_unpredictable): Likewise.
 654         (print_mve_size): Likewise.
 655
 656 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 657             Michael Collison <michael.collison@arm.com>
 658
 659         * arm-dis.c (thumb32_opcodes): Add new instructions.
 660         (enum mve_instructions): Likewise.
 661         (is_mve_encoding_conflict): Handle new instructions.
 662         (is_mve_undefined): Likewise.
 663         (is_mve_unpredictable): Likewise.
 664         (print_mve_size): Likewise.
 665         (print_insn_mve): Likewise.
 666
 667 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 668             Michael Collison <michael.collison@arm.com>
 669
 670         * arm-dis.c (thumb32_opcodes): Add new instructions.
 671         (print_insn_thumb32): Handle new instructions.
 672
 673 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 674             Michael Collison <michael.collison@arm.com>
 675
 676         * arm-dis.c (enum mve_instructions): Add new instructions.
 677         (enum mve_undefined): Add new reasons.
 678         (is_mve_encoding_conflict): Handle new instructions.
 679         (is_mve_undefined): Likewise.
 680         (is_mve_unpredictable): Likewise.
 681         (print_mve_undefined): Likewise.
 682         (print_mve_size): Likewise.
 683         (print_mve_shift_n): Likewise.
 684         (print_insn_mve): Likewise.
 685
 686 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 687             Michael Collison <michael.collison@arm.com>
 688
 689         * arm-dis.c (enum mve_instructions): Add new instructions.
 690         (is_mve_encoding_conflict): Handle new instructions.
 691         (is_mve_unpredictable): Likewise.
 692         (print_mve_rotate): Likewise.
 693         (print_mve_size): Likewise.
 694         (print_insn_mve): Likewise.
 695
 696 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 697             Michael Collison <michael.collison@arm.com>
 698
 699         * arm-dis.c (enum mve_instructions): Add new instructions.
 700         (is_mve_encoding_conflict): Handle new instructions.
 701         (is_mve_unpredictable): Likewise.
 702         (print_mve_size): Likewise.
 703         (print_insn_mve): Likewise.
 704
 705 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 706             Michael Collison <michael.collison@arm.com>
 707
 708         * arm-dis.c (enum mve_instructions): Add new instructions.
 709         (enum mve_undefined): Add new reasons.
 710         (is_mve_encoding_conflict): Handle new instructions.
 711         (is_mve_undefined): Likewise.
 712         (is_mve_unpredictable): Likewise.
 713         (print_mve_undefined): Likewise.
 714         (print_mve_size): Likewise.
 715         (print_insn_mve): Likewise.
 716
 717 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 718             Michael Collison <michael.collison@arm.com>
 719
 720         * arm-dis.c (enum mve_instructions): Add new instructions.
 721         (is_mve_encoding_conflict): Handle new instructions.
 722         (is_mve_undefined): Likewise.
 723         (is_mve_unpredictable): Likewise.
 724         (print_mve_size): Likewise.
 725         (print_insn_mve): Likewise.
 726
 727 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 728             Michael Collison <michael.collison@arm.com>
 729
 730         * arm-dis.c (enum mve_instructions): Add new instructions.
 731         (enum mve_unpredictable): Add new reasons.
 732         (enum mve_undefined): Likewise.
 733         (is_mve_okay_in_it): Handle new isntructions.
 734         (is_mve_encoding_conflict): Likewise.
 735         (is_mve_undefined): Likewise.
 736         (is_mve_unpredictable): Likewise.
 737         (print_mve_vmov_index): Likewise.
 738         (print_simd_imm8): Likewise.
 739         (print_mve_undefined): Likewise.
 740         (print_mve_unpredictable): Likewise.
 741         (print_mve_size): Likewise.
 742         (print_insn_mve): Likewise.
 743
 744 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 745             Michael Collison <michael.collison@arm.com>
 746
 747         * arm-dis.c (enum mve_instructions): Add new instructions.
 748         (enum mve_unpredictable): Add new reasons.
 749         (enum mve_undefined): Likewise.
 750         (is_mve_encoding_conflict): Handle new instructions.
 751         (is_mve_undefined): Likewise.
 752         (is_mve_unpredictable): Likewise.
 753         (print_mve_undefined): Likewise.
 754         (print_mve_unpredictable): Likewise.
 755         (print_mve_rounding_mode): Likewise.
 756         (print_mve_vcvt_size): Likewise.
 757         (print_mve_size): Likewise.
 758         (print_insn_mve): Likewise.
 759
 760 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 761             Michael Collison <michael.collison@arm.com>
 762
 763         * arm-dis.c (enum mve_instructions): Add new instructions.
 764         (enum mve_unpredictable): Add new reasons.
 765         (enum mve_undefined): Likewise.
 766         (is_mve_undefined): Handle new instructions.
 767         (is_mve_unpredictable): Likewise.
 768         (print_mve_undefined): Likewise.
 769         (print_mve_unpredictable): Likewise.
 770         (print_mve_size): Likewise.
 771         (print_insn_mve): Likewise.
 772
 773 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 774             Michael Collison <michael.collison@arm.com>
 775
 776         * arm-dis.c (enum mve_instructions): Add new instructions.
 777         (enum mve_undefined): Add new reasons.
 778         (insns): Add new instructions.
 779         (is_mve_encoding_conflict):
 780         (print_mve_vld_str_addr): New print function.
 781         (is_mve_undefined): Handle new instructions.
 782         (is_mve_unpredictable): Likewise.
 783         (print_mve_undefined): Likewise.
 784         (print_mve_size): Likewise.
 785         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 786         (print_insn_mve):  Handle new operands.
 787
 788 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 789             Michael Collison <michael.collison@arm.com>
 790
 791         * arm-dis.c (enum mve_instructions): Add new instructions.
 792         (enum mve_unpredictable): Add new reasons.
 793         (is_mve_encoding_conflict): Handle new instructions.
 794         (is_mve_unpredictable): Likewise.
 795         (mve_opcodes): Add new instructions.
 796         (print_mve_unpredictable): Handle new reasons.
 797         (print_mve_register_blocks): New print function.
 798         (print_mve_size): Handle new instructions.
 799         (print_insn_mve): Likewise.
 800
 801 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 802             Michael Collison <michael.collison@arm.com>
 803
 804         * arm-dis.c (enum mve_instructions): Add new instructions.
 805         (enum mve_unpredictable): Add new reasons.
 806         (enum mve_undefined): Likewise.
 807         (is_mve_encoding_conflict): Handle new instructions.
 808         (is_mve_undefined): Likewise.
 809         (is_mve_unpredictable): Likewise.
 810         (coprocessor_opcodes): Move NEON VDUP from here...
 811         (neon_opcodes): ... to here.
 812         (mve_opcodes): Add new instructions.
 813         (print_mve_undefined):  Handle new reasons.
 814         (print_mve_unpredictable): Likewise.
 815         (print_mve_size): Handle new instructions.
 816         (print_insn_neon): Handle vdup.
 817         (print_insn_mve): Handle new operands.
 818
 819 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 820             Michael Collison <michael.collison@arm.com>
 821
 822         * arm-dis.c (enum mve_instructions): Add new instructions.
 823         (enum mve_unpredictable): Add new values.
 824         (mve_opcodes): Add new instructions.
 825         (vec_condnames): New array with vector conditions.
 826         (mve_predicatenames): New array with predicate suffixes.
 827         (mve_vec_sizename): New array with vector sizes.
 828         (enum vpt_pred_state): New enum with vector predication states.
 829         (struct vpt_block): New struct type for vpt blocks.
 830         (vpt_block_state): Global struct to keep track of state.
 831         (mve_extract_pred_mask): New helper function.
 832         (num_instructions_vpt_block): Likewise.
 833         (mark_outside_vpt_block): Likewise.
 834         (mark_inside_vpt_block): Likewise.
 835         (invert_next_predicate_state): Likewise.
 836         (update_next_predicate_state): Likewise.
 837         (update_vpt_block_state): Likewise.
 838         (is_vpt_instruction): Likewise.
 839         (is_mve_encoding_conflict): Add entries for new instructions.
 840         (is_mve_unpredictable): Likewise.
 841         (print_mve_unpredictable): Handle new cases.
 842         (print_instruction_predicate): Likewise.
 843         (print_mve_size): New function.
 844         (print_vec_condition): New function.
 845         (print_insn_mve): Handle vpt blocks and new print operands.
 846
 847 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 848
 849         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 850         8, 14 and 15 for Armv8.1-M Mainline.
 851
 852 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 853             Michael Collison <michael.collison@arm.com>
 854
 855         * arm-dis.c (enum mve_instructions): New enum.
 856         (enum mve_unpredictable): Likewise.
 857         (enum mve_undefined): Likewise.
 858         (struct mopcode32): New struct.
 859         (is_mve_okay_in_it): New function.
 860         (is_mve_architecture): Likewise.
 861         (arm_decode_field): Likewise.
 862         (arm_decode_field_multiple): Likewise.
 863         (is_mve_encoding_conflict): Likewise.
 864         (is_mve_undefined): Likewise.
 865         (is_mve_unpredictable): Likewise.
 866         (print_mve_undefined): Likewise.
 867         (print_mve_unpredictable): Likewise.
 868         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 869         (print_insn_mve): New function.
 870         (print_insn_thumb32): Handle MVE architecture.
 871         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 872
 873 2019-05-10  Nick Clifton  <nickc@redhat.com>
 874
 875         PR 24538
 876         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 877         end of the table prematurely.
 878
 879 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 880
 881         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 882         macros for R6.
 883
 884 2019-05-11  Alan Modra  <amodra@gmail.com>
 885
 886         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 887         when -Mraw is in effect.
 888
 889 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 890
 891         * aarch64-dis-2.c: Regenerate.
 892         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 893         (OP_SVE_BBB): New variant set.
 894         (OP_SVE_DDDD): New variant set.
 895         (OP_SVE_HHH): New variant set.
 896         (OP_SVE_HHHU): New variant set.
 897         (OP_SVE_SSS): New variant set.
 898         (OP_SVE_SSSU): New variant set.
 899         (OP_SVE_SHH): New variant set.
 900         (OP_SVE_SBBU): New variant set.
 901         (OP_SVE_DSS): New variant set.
 902         (OP_SVE_DHHU): New variant set.
 903         (OP_SVE_VMV_HSD_BHS): New variant set.
 904         (OP_SVE_VVU_HSD_BHS): New variant set.
 905         (OP_SVE_VVVU_SD_BH): New variant set.
 906         (OP_SVE_VVVU_BHSD): New variant set.
 907         (OP_SVE_VVV_QHD_DBS): New variant set.
 908         (OP_SVE_VVV_HSD_BHS): New variant set.
 909         (OP_SVE_VVV_HSD_BHS2): New variant set.
 910         (OP_SVE_VVV_BHS_HSD): New variant set.
 911         (OP_SVE_VV_BHS_HSD): New variant set.
 912         (OP_SVE_VVV_SD): New variant set.
 913         (OP_SVE_VVU_BHS_HSD): New variant set.
 914         (OP_SVE_VZVV_SD): New variant set.
 915         (OP_SVE_VZVV_BH): New variant set.
 916         (OP_SVE_VZV_SD): New variant set.
 917         (aarch64_opcode_table): Add sve2 instructions.
 918
 919 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 920
 921         * aarch64-asm-2.c: Regenerated.
 922         * aarch64-dis-2.c: Regenerated.
 923         * aarch64-opc-2.c: Regenerated.
 924         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 925         for SVE_SHLIMM_UNPRED_22.
 926         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 927         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 928         operand.
 929
 930 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 931
 932         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 933         sve_size_tsz_bhs iclass encode.
 934         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 935         sve_size_tsz_bhs iclass decode.
 936
 937 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 938
 939         * aarch64-asm-2.c: Regenerated.
 940         * aarch64-dis-2.c: Regenerated.
 941         * aarch64-opc-2.c: Regenerated.
 942         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 943         for SVE_Zm4_11_INDEX.
 944         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 945         (fields): Handle SVE_i2h field.
 946         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 947         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 948
 949 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 950
 951         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 952         sve_shift_tsz_bhsd iclass encode.
 953         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 954         sve_shift_tsz_bhsd iclass decode.
 955
 956 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 957
 958         * aarch64-asm-2.c: Regenerated.
 959         * aarch64-dis-2.c: Regenerated.
 960         * aarch64-opc-2.c: Regenerated.
 961         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 962         (aarch64_encode_variant_using_iclass): Handle
 963         sve_shift_tsz_hsd iclass encode.
 964         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 965         sve_shift_tsz_hsd iclass decode.
 966         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 967         for SVE_SHRIMM_UNPRED_22.
 968         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 969         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 970         operand.
 971
 972 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 973
 974         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 975         sve_size_013 iclass encode.
 976         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 977         sve_size_013 iclass decode.
 978
 979 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 980
 981         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 982         sve_size_bh iclass encode.
 983         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 984         sve_size_bh iclass decode.
 985
 986 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 987
 988         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 989         sve_size_sd2 iclass encode.
 990         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 991         sve_size_sd2 iclass decode.
 992         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 993         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 994
 995 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 996
 997         * aarch64-asm-2.c: Regenerated.
 998         * aarch64-dis-2.c: Regenerated.
 999         * aarch64-opc-2.c: Regenerated.
1000         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1001         for SVE_ADDR_ZX.
1002         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1003         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1004
1005 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1006
1007         * aarch64-asm-2.c: Regenerated.
1008         * aarch64-dis-2.c: Regenerated.
1009         * aarch64-opc-2.c: Regenerated.
1010         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1011         for SVE_Zm3_11_INDEX.
1012         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1013         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1014         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1015         fields.
1016         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1017
1018 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1019
1020         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1021         sve_size_hsd2 iclass encode.
1022         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1023         sve_size_hsd2 iclass decode.
1024         * aarch64-opc.c (fields): Handle SVE_size field.
1025         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1026
1027 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1028
1029         * aarch64-asm-2.c: Regenerated.
1030         * aarch64-dis-2.c: Regenerated.
1031         * aarch64-opc-2.c: Regenerated.
1032         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1033         for SVE_IMM_ROT3.
1034         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1035         (fields): Handle SVE_rot3 field.
1036         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1037         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1038
1039 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1040
1041         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1042         instructions.
1043
1044 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1045
1046         * aarch64-tbl.h
1047         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1048         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1049         aarch64_feature_sve2bitperm): New feature sets.
1050         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1051         for feature set addresses.
1052         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1053         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1054
1055 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1056             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1057
1058         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1059         argument and set ASE_EVA_R6 appropriately.
1060         (set_default_mips_dis_options): Pass ISA to above.
1061         (parse_mips_dis_option): Likewise.
1062         * mips-opc.c (EVAR6): New macro.
1063         (mips_builtin_opcodes): Add llwpe, scwpe.
1064
1065 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1066
1067         * aarch64-asm-2.c: Regenerated.
1068         * aarch64-dis-2.c: Regenerated.
1069         * aarch64-opc-2.c: Regenerated.
1070         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1071         AARCH64_OPND_TME_UIMM16.
1072         (aarch64_print_operand): Likewise.
1073         * aarch64-tbl.h (QL_IMM_NIL): New.
1074         (TME): New.
1075         (_TME_INSN): New.
1076         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1077
1078 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1079
1080         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1081
1082 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1083             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1084
1085         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1086
1087 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1088
1089         * s12z-opc.h: Add extern "C" bracketing to help
1090         users who wish to use this interface in c++ code.
1091
1092 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1093
1094         * s12z-opc.c (bm_decode): Handle bit map operations with the
1095         "reserved0" mode.
1096
1097 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1098
1099         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1100         specifier.  Add entries for VLDR and VSTR of system registers.
1101         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1102         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1103         of %J and %K format specifier.
1104
1105 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1106
1107         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1108         Add new entries for VSCCLRM instruction.
1109         (print_insn_coprocessor): Handle new %C format control code.
1110
1111 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1112
1113         * arm-dis.c (enum isa): New enum.
1114         (struct sopcode32): New structure.
1115         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1116         set isa field of all current entries to ANY.
1117         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1118         Only match an entry if its isa field allows the current mode.
1119
1120 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1121
1122         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1123         CLRM.
1124         (print_insn_thumb32): Add logic to print %n CLRM register list.
1125
1126 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1127
1128         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1129         and %Q patterns.
1130
1131 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1132
1133         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1134         (print_insn_thumb32): Edit the switch case for %Z.
1135
1136 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1137
1138         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1139
1140 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1141
1142         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1143
1144 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1145
1146         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1147
1148 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1149
1150         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1151         Arm register with r13 and r15 unpredictable.
1152         (thumb32_opcodes): New instructions for bfx and bflx.
1153
1154 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1155
1156         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1157
1158 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1159
1160         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1161
1162 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1163
1164         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1165
1166 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1167
1168         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1169
1170 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1171
1172         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1173         "optr". ("operator" is a reserved word in c++).
1174
1175 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1176
1177         * aarch64-opc.c (aarch64_print_operand): Add case for
1178         AARCH64_OPND_Rt_SP.
1179         (verify_constraints): Likewise.
1180         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1181         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1182         to accept Rt|SP as first operand.
1183         (AARCH64_OPERANDS): Add new Rt_SP.
1184         * aarch64-asm-2.c: Regenerated.
1185         * aarch64-dis-2.c: Regenerated.
1186         * aarch64-opc-2.c: Regenerated.
1187
1188 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1189
1190         * aarch64-asm-2.c: Regenerated.
1191         * aarch64-dis-2.c: Likewise.
1192         * aarch64-opc-2.c: Likewise.
1193         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1194
1195 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1196
1197         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1198
1199 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1200
1201         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1202         * i386-init.h: Regenerated.
1203
1204 2019-04-07  Alan Modra  <amodra@gmail.com>
1205
1206         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1207         op_separator to control printing of spaces, comma and parens
1208         rather than need_comma, need_paren and spaces vars.
1209
1210 2019-04-07  Alan Modra  <amodra@gmail.com>
1211
1212         PR 24421
1213         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1214         (print_insn_neon, print_insn_arm): Likewise.
1215
1216 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1217
1218         * i386-dis-evex.h (evex_table): Updated to support BF16
1219         instructions.
1220         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1221         and EVEX_W_0F3872_P_3.
1222         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1223         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1224         * i386-opc.h (enum): Add CpuAVX512_BF16.
1225         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1226         * i386-opc.tbl: Add AVX512 BF16 instructions.
1227         * i386-init.h: Regenerated.
1228         * i386-tbl.h: Likewise.
1229
1230 2019-04-05  Alan Modra  <amodra@gmail.com>
1231
1232         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1233         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1234         to favour printing of "-" branch hint when using the "y" bit.
1235         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1236
1237 2019-04-05  Alan Modra  <amodra@gmail.com>
1238
1239         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1240         opcode until first operand is output.
1241
1242 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1243
1244         PR gas/24349
1245         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1246         (valid_bo_post_v2): Add support for 'at' branch hints.
1247         (insert_bo): Only error on branch on ctr.
1248         (get_bo_hint_mask): New function.
1249         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1250         for inserting 'at' branch hints.
1251         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1252         for extracting 'at' branch hints.
1253         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1254         (BOE): Delete operand.
1255         (BOM, BOP): New operands.
1256         (RM): Update value.
1257         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1258         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1259         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1260         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1261         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1262         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1263         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1264         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1265         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1266         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1267         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1268         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1269         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1270         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1271         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1272         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1273         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1274         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1275         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1276         bttarl+>: New extended mnemonics.
1277
1278 2019-03-28  Alan Modra  <amodra@gmail.com>
1279
1280         PR 24390
1281         * ppc-opc.c (BTF): Define.
1282         (powerpc_opcodes): Use for mtfsb*.
1283         * ppc-dis.c (print_insn_powerpc): Print fields with both
1284         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1285
1286 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1287
1288         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1289         (mapping_symbol_for_insn): Implement new algorithm.
1290         (print_insn): Remove duplicate code.
1291
1292 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1293
1294         * aarch64-dis.c (print_insn_aarch64):
1295         Implement override.
1296
1297 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1298
1299         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1300         order.
1301
1302 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1303
1304         * aarch64-dis.c (last_stop_offset): New.
1305         (print_insn_aarch64): Use stop_offset.
1306
1307 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1308
1309         PR gas/24359
1310         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1311         CPU_ANY_AVX2_FLAGS.
1312         * i386-init.h: Regenerated.
1313
1314 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1315
1316         PR gas/24348
1317         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1318         vmovdqu16, vmovdqu32 and vmovdqu64.
1319         * i386-tbl.h: Regenerated.
1320
1321 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1322
1323         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1324         from vstrszb, vstrszh, and vstrszf.
1325
1326 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1327
1328         * s390-opc.txt: Add instruction descriptions.
1329
1330 2019-02-08  Jim Wilson  <jimw@sifive.com>
1331
1332         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1333         <bne>: Likewise.
1334
1335 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1336
1337         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1338
1339 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1340
1341         PR binutils/23212
1342         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1343         * aarch64-opc.c (verify_elem_sd): New.
1344         (fields): Add FLD_sz entr.
1345         * aarch64-tbl.h (_SIMD_INSN): New.
1346         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1347         fmulx scalar and vector by element isns.
1348
1349 2019-02-07  Nick Clifton  <nickc@redhat.com>
1350
1351         * po/sv.po: Updated Swedish translation.
1352
1353 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1354
1355         * s390-mkopc.c (main): Accept arch13 as cpu string.
1356         * s390-opc.c: Add new instruction formats and instruction opcode
1357         masks.
1358         * s390-opc.txt: Add new arch13 instructions.
1359
1360 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1361
1362         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1363         (aarch64_opcode): Change encoding for stg, stzg
1364         st2g and st2zg.
1365         * aarch64-asm-2.c: Regenerated.
1366         * aarch64-dis-2.c: Regenerated.
1367         * aarch64-opc-2.c: Regenerated.
1368
1369 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1370
1371         * aarch64-asm-2.c: Regenerated.
1372         * aarch64-dis-2.c: Likewise.
1373         * aarch64-opc-2.c: Likewise.
1374         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1375
1376 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1377             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1378
1379         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1380         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1381         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1382         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1383         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1384         case for ldstgv_indexed.
1385         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1386         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1387         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1388         * aarch64-asm-2.c: Regenerated.
1389         * aarch64-dis-2.c: Regenerated.
1390         * aarch64-opc-2.c: Regenerated.
1391
1392 2019-01-23  Nick Clifton  <nickc@redhat.com>
1393
1394         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1395
1396 2019-01-21  Nick Clifton  <nickc@redhat.com>
1397
1398         * po/de.po: Updated German translation.
1399         * po/uk.po: Updated Ukranian translation.
1400
1401 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1402         * mips-dis.c (mips_arch_choices): Fix typo in
1403         gs464, gs464e and gs264e descriptors.
1404
1405 2019-01-19  Nick Clifton  <nickc@redhat.com>
1406
1407         * configure: Regenerate.
1408         * po/opcodes.pot: Regenerate.
1409
1410 2018-06-24  Nick Clifton  <nickc@redhat.com>
1411
1412         2.32 branch created.
1413
1414 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1415
1416         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1417         if it is null.
1418         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1419         zero.
1420
1421 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1422
1423         * configure: Regenerate.
1424
1425 2019-01-07  Alan Modra  <amodra@gmail.com>
1426
1427         * configure: Regenerate.
1428         * po/POTFILES.in: Regenerate.
1429
1430 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1431
1432         * s12z-opc.c: New file.
1433         * s12z-opc.h: New file.
1434         * s12z-dis.c: Removed all code not directly related to display
1435         of instructions.  Used the interface provided by the new files
1436         instead.
1437         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1438         * Makefile.in: Regenerate.
1439         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1440         * configure: Regenerate.
1441
1442 2019-01-01  Alan Modra  <amodra@gmail.com>
1443
1444         Update year range in copyright notice of all files.
1445
1446 For older changes see ChangeLog-2018
1447 \f
1448 Copyright (C) 2019 Free Software Foundation, Inc.
1449
1450 Copying and distribution of this file, with or without modification,
1451 are permitted in any medium without royalty provided the copyright
1452 notice and this notice are preserved.
1453
1454 Local Variables:
1455 mode: change-log
1456 left-margin: 8
1457 fill-column: 74
1458 version-control: never
1459 End: