opcodes/ChangeLog

   1 2010-12-11 Mingming Sun <mingm.sun@gmail.com>
   2
   3         * mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
   4         fixed point instructions.
   5
   6 2010-12-09  Mike Frysinger  <vapier@gentoo.org>
   7
   8         * .gitignore: New file.
   9
  10 2010-11-25  Alan Modra  <amodra@gmail.com>
  11
  12         * po/es.po: Update.
  13         * po/fr.po: Update.
  14         * po/nl.po: Update.
  15         * po/zh_CN.po: Update.
  16
  17 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
  18
  19         * mips-dis.c (mips_arch_choices): Add loongson3a.
  20         * mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
  21         (mips_builtin_opcodes): Modify some instructions' membership from
  22         IL2F to IL2F|IL3A.
  23
  24 2010-11-10  Nick Clifton  <nickc@redhat.com>
  25
  26         * po/fi.po: Updated Finnish translation.
  27
  28 2010-11-05  Tristan Gingold  <gingold@adacore.com>
  29
  30         * po/opcodes.pot: Regenerate
  31
  32 2010-10-28  Maciej W. Rozycki  <macro@codesourcery.com>
  33
  34         * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld".
  35
  36 2010-10-28  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  37
  38         * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
  39
  40 2010-10-25  Chao-ying Fu  <fu@mips.com>
  41
  42         * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
  43
  44 2010-10-25  Nathan Sidwell  <nathan@codesourcery.com>
  45
  46         * tic6x-dis.c: Add attribution.
  47
  48 2010-10-22  Alan Modra  <amodra@gmail.com>
  49
  50         * Makefile.am (CLEANFILES): Add stamp-lm32.  Sort.
  51         * Makefile.in: Regenerate.
  52
  53 2010-10-18  Maciej W. Rozycki  <macro@linux-mips.org>
  54
  55         * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
  56         macros before their corresponding MIPS III hardware instructions.
  57
  58 2010-10-16  H.J. Lu  <hongjiu.lu@intel.com>
  59
  60         * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
  61
  62         * i386-init.h: Regenerated.
  63
  64 2010-10-15  Mike Frysinger  <vapier@gentoo.org>
  65
  66         * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M.
  67
  68 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
  69
  70         * i386-opc.tbl: Remove CheckRegSize from movq.
  71         * i386-tbl.h: Regenerated.
  72
  73 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
  74
  75         * i386-opc.tbl: Remove CheckRegSize from instructions with
  76         0, 1 or fixed operands.
  77         * i386-tbl.h: Regenerated.
  78
  79 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
  80
  81         * i386-gen.c (opcode_modifiers): Add CheckRegSize.
  82
  83         * i386-opc.h (CheckRegSize): New.
  84         (i386_opcode_modifier): Add checkregsize.
  85
  86         * i386-opc.tbl: Add CheckRegSize to instructions which
  87         require register size check.
  88         * i386-tbl.h: Regenerated.
  89
  90 2010-10-12  Andreas Schwab  <schwab@linux-m68k.org>
  91
  92         * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
  93
  94 2010-10-11  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  95
  96         * s390-opc.c: Make the instruction masks for the load/store on
  97         condition instructions to cover the condition code mask as well.
  98         * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
  99
 100 2010-10-11  Jan Kratochvil  <jan.kratochvil@redhat.com>
 101             Jiang Jilin  <freephp@gmail.com>
 102
 103         * Makefile.am (libopcodes_a_SOURCES): New as empty.
 104         * Makefile.in: Regenerate.
 105
 106 2010-10-09  Matt Rice  <ratmice@gmail.com>
 107
 108         * fr30-desc.h: Regenerate.
 109         * frv-desc.h: Regenerate.
 110         * ip2k-desc.h: Regenerate.
 111         * iq2000-desc.h: Regenerate.
 112         * lm32-desc.h: Regenerate.
 113         * m32c-desc.h: Regenerate.
 114         * m32r-desc.h: Regenerate.
 115         * mep-desc.h: Regenerate.
 116         * mep-opc.c: Regenerate.
 117         * mt-desc.h: Regenerate.
 118         * openrisc-desc.h: Regenerate.
 119         * xc16x-desc.h: Regenerate.
 120         * xstormy16-desc.h: Regenerate.
 121
 122 2010-10-08  Pierre Muller  <muller@ics.u-strasbg.fr>
 123
 124         Fix build with -DDEBUG=7
 125         * frv-opc.c: Regenerate.
 126         * or32-dis.c (DEBUG): Don't redefine.
 127         (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
 128         Adapt DEBUG code to some type changes throughout.
 129         * or32-opc.c (or32_extract): Likewise.
 130
 131 2010-10-07  Bernd Schmidt  <bernds@codesourcery.com>
 132
 133         * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
 134         in SPKERNEL instructions.
 135
 136 2010-10-02  H.J. Lu  <hongjiu.lu@intel.com>
 137
 138         PR binutils/12076
 139         * i386-dis.c (RMAL): Remove duplicate.
 140
 141 2010-09-30  Pierre Muller  <muller@ics.u-strasbg.fr>
 142
 143         * s390-mkopc.c (main): Exit with error 1 if sscanf fails
 144         to parse all 6 parameters.
 145
 146 2010-09-28  Pierre Muller  <muller@ics.u-strasbg.fr>
 147
 148         * s390-mkopc.c (main): Change description array size to 80.
 149         Add maximum length of 79 to description parsing.
 150
 151 2010-09-27  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 152
 153         * configure: Regenerate.
 154
 155 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 156
 157         * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
 158         (main): Recognize the new CPU string.
 159         * s390-opc.c: Add new instruction formats and masks.
 160         * s390-opc.txt: Add new z196 instructions.
 161
 162 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 163
 164         * s390-dis.c (print_insn_s390): Pick instruction with most
 165         specific mask.
 166         * s390-opc.c: Add unused bits to the insn mask.
 167         * s390-opc.txt: Reorder some instructions to prefer more recent
 168         versions.
 169
 170 2010-09-27  Tejas Belagod  <tejas.belagod@arm.com>
 171
 172         * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
 173         correction to unaligned PCs while printing comment.
 174
 175 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 176
 177         * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
 178         (thumb32_opcodes): Likewise.
 179         (banked_regname): New function.
 180         (print_insn_arm): Add Virtualization Extensions support.
 181         (print_insn_thumb32): Likewise.
 182
 183 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 184
 185         * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
 186         ARM state.
 187
 188 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 189
 190         * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
 191         (thumb32_opcodes): Likewise.
 192
 193 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 194
 195         * arm-dis.c (arm_opcodes): Add support for pldw.
 196         (thumb32_opcodes): Likewise.
 197
 198 2010-09-22  Robin Getz  <robin.getz@analog.com>
 199
 200         * bfin-dis.c (fmtconst): Cast address to 32bits.
 201
 202 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 203
 204         * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
 205
 206 2010-09-22  Robin Getz  <robin.getz@analog.com>
 207
 208         * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
 209         Reject P6/P7 to TESTSET.
 210         (decode_PushPopReg_0): Check for parallel insns.  Reject pushing
 211         SP onto the stack.
 212         (decode_PushPopMultiple_0): Check for parallel insns.  Make sure
 213         P/D fields match all the time.
 214         (decode_CCflag_0): Check for parallel insns.  Verify x/y fields
 215         are 0 for accumulator compares.
 216         (decode_CC2stat_0): Check for parallel insns.  Reject CC<op>CC.
 217         (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
 218         decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
 219         decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 220         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 221         decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
 222         insns.
 223         (decode_dagMODim_0): Verify br field for IREG ops.
 224         (decode_LDST_0): Reject preg load into same preg.
 225         (_print_insn_bfin): Handle returns for ILLEGAL decodes.
 226         (print_insn_bfin): Likewise.
 227
 228 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 229
 230         * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
 231
 232 2010-09-22  Robin Getz  <robin.getz@analog.com>
 233
 234         * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
 235
 236 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 237
 238         * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
 239
 240 2010-09-22  Robin Getz  <robin.getz@analog.com>
 241
 242         * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
 243         register values greater than 8.
 244         (IS_RESERVEDREG, allreg, mostreg): New helpers.
 245         (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
 246         (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
 247         (decode_CC2dreg_0): Check valid CC register number.
 248
 249 2010-09-22  Robin Getz  <robin.getz@analog.com>
 250
 251         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
 252
 253 2010-09-22  Robin Getz  <robin.getz@analog.com>
 254
 255         * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
 256         (reg_names): Likewise.
 257         (decode_statbits): Likewise; while reformatting to make manageable.
 258
 259 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 260
 261         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
 262         (decode_pseudoOChar_0): New function.
 263         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
 264
 265 2010-09-22  Robin Getz  <robin.getz@analog.com>
 266
 267         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
 268         LSHIFT instead of SHIFT.
 269
 270 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 271
 272         * bfin-dis.c (constant_formats): Constify the whole structure.
 273         (fmtconst): Add const to return value.
 274         (reg_names): Mark const.
 275         (decode_multfunc): Mark s0/s1 as const.
 276         (decode_macfunc): Mark a/sop as const.
 277
 278 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
 279
 280         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
 281
 282 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 283
 284         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
 285         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
 286
 287 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
 288
 289         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
 290         dlx_insn_type array.
 291
 292 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 293
 294         PR binutils/11960
 295         * i386-dis.c (sIv): New.
 296         (dis386): Replace Iq with sIv on "pushT".
 297         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
 298         (x86_64_table): Replace {T|}/{P|} with P.
 299         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
 300         (OP_sI): Update v_mode.  Remove w_mode.
 301
 302 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
 303
 304         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
 305         on E500 and E500MC.
 306
 307 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
 308
 309         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
 310         prefetchw.
 311
 312 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 313
 314         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
 315         to processor flags for PENTIUMPRO processors and later.
 316         * i386-opc.h (enum): Add CpuNop.
 317         (i386_cpu_flags): Add cpunop bit.
 318         * i386-opc.tbl: Change nop cpu_flags.
 319         * i386-init.h: Regenerated.
 320         * i386-tbl.h: Likewise.
 321
 322 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 323
 324         * i386-opc.h (enum): Fix typos in comments.
 325
 326 2010-08-06  Alan Modra  <amodra@gmail.com>
 327
 328         * disassemble.c: Formatting.
 329         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 330
 331 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 332
 333         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
 334         * i386-tbl.h: Regenerated.
 335
 336 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 337
 338         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
 339
 340         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
 341         * i386-tbl.h: Regenerated.
 342
 343 2010-07-29  DJ Delorie  <dj@redhat.com>
 344
 345         * rx-decode.opc (SRR): New.
 346         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
 347         r0,r0) and NOP3 (max r0,r0) special cases.
 348         * rx-decode.c: Regenerate.
 349
 350 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
 351
 352         * i386-dis.c: Add 0F to VEX opcode enums.
 353
 354 2010-07-27  DJ Delorie  <dj@redhat.com>
 355
 356         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
 357         (rx_decode_opcode): Likewise.
 358         * rx-decode.c: Regenerate.
 359
 360 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 361             Ina Pandit  <ina.pandit@kpitcummins.com>
 362
 363         * v850-dis.c (v850_sreg_names): Updated structure for system
 364         registers.
 365         (float_cc_names): new structure for condition codes.
 366         (print_value): Update the function that prints value.
 367         (get_operand_value): New function to get the operand value.
 368         (disassemble): Updated to handle the disassembly of instructions.
 369         (print_insn_v850): Updated function to print instruction for different
 370         families.
 371         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 372         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 373         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 374         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 375         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 376         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 377         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 378         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 379         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 380         (v850_operands): Update with the relocation name. Also update
 381         the instructions with specific set of processors.
 382
 383 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 384
 385         * arm-dis.c (print_insn_arm): Add cases for printing more
 386         symbolic operands.
 387         (print_insn_thumb32): Likewise.
 388
 389 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 390
 391         * mips-dis.c (print_insn_mips): Correct branch instruction type
 392         determination.
 393
 394 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 395
 396         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 397         type and delay slot determination.
 398         (print_insn_mips16): Extend branch instruction type and delay
 399         slot determination to cover all instructions.
 400         * mips16-opc.c (BR): Remove macro.
 401         (UBR, CBR): New macros.
 402         (mips16_opcodes): Update branch annotation for "b", "beqz",
 403         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 404         and "jrc".
 405
 406 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 407
 408         AVX Programming Reference (June, 2010)
 409         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 410         * i386-opc.tbl: Likewise.
 411         * i386-tbl.h: Regenerated.
 412
 413 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 414
 415         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 416
 417 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 418
 419         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 420         ppc_cpu_t before inverting.
 421         (ppc_parse_cpu): Likewise.
 422         (print_insn_powerpc): Likewise.
 423
 424 2010-07-03  Alan Modra  <amodra@gmail.com>
 425
 426         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 427         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 428         (PPC64, MFDEC2): Update.
 429         (NON32, NO371): Define.
 430         (powerpc_opcode): Update to not use old opcode flags, and avoid
 431         -m601 duplicates.
 432
 433 2010-07-03  DJ Delorie  <dj@delorie.com>
 434
 435         * m32c-ibld.c: Regenerate.
 436
 437 2010-07-03  Alan Modra  <amodra@gmail.com>
 438
 439         * ppc-opc.c (PWR2COM): Define.
 440         (PPCPWR2): Add PPC_OPCODE_COMMON.
 441         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 442         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 443         "rac" from -mcom.
 444
 445 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 446
 447         AVX Programming Reference (June, 2010)
 448         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 449         (PREFIX_0FAE_REG_1): Likewise.
 450         (PREFIX_0FAE_REG_2): Likewise.
 451         (PREFIX_0FAE_REG_3): Likewise.
 452         (PREFIX_VEX_3813): Likewise.
 453         (PREFIX_VEX_3A1D): Likewise.
 454         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 455         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 456         PREFIX_VEX_3A1D.
 457         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 458         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 459         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 460
 461         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 462         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 463         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 464
 465         * i386-opc.h (CpuXsaveopt): New.
 466         (CpuFSGSBase): Likewise.
 467         (CpuRdRnd): Likewise.
 468         (CpuF16C): Likewise.
 469         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 470         cpuf16c.
 471
 472         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 473         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 474         * i386-init.h: Regenerated.
 475         * i386-tbl.h: Likewise.
 476
 477 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 478
 479         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 480         and mtocrf on EFS.
 481
 482 2010-06-29  Alan Modra  <amodra@gmail.com>
 483
 484         * maxq-dis.c: Delete file.
 485         * Makefile.am: Remove references to maxq.
 486         * configure.in: Likewise.
 487         * disassemble.c: Likewise.
 488         * Makefile.in: Regenerate.
 489         * configure: Regenerate.
 490         * po/POTFILES.in: Regenerate.
 491
 492 2010-06-29  Alan Modra  <amodra@gmail.com>
 493
 494         * mep-dis.c: Regenerate.
 495
 496 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 497
 498         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 499
 500 2010-06-27  Alan Modra  <amodra@gmail.com>
 501
 502         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 503         (decodeInstr): Likewise.
 504         * dlx-dis.c (print_insn_dlx): Likewise.
 505         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 506         * maxq-dis.c (check_move, print_insn): Likewise.
 507         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 508         * msp430-dis.c (msp430_branchinstr): Likewise.
 509         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 510         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 511         * sparc-dis.c (print_insn_sparc): Likewise.
 512         * fr30-asm.c: Regenerate.
 513         * frv-asm.c: Regenerate.
 514         * ip2k-asm.c: Regenerate.
 515         * iq2000-asm.c: Regenerate.
 516         * lm32-asm.c: Regenerate.
 517         * m32c-asm.c: Regenerate.
 518         * m32r-asm.c: Regenerate.
 519         * mep-asm.c: Regenerate.
 520         * mt-asm.c: Regenerate.
 521         * openrisc-asm.c: Regenerate.
 522         * xc16x-asm.c: Regenerate.
 523         * xstormy16-asm.c: Regenerate.
 524
 525 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 526
 527         PR gas/11673
 528         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 529
 530 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 531
 532         PR binutils/11676
 533         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 534
 535 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 536
 537         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 538         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 539         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 540         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 541         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 542         Treat lwsync as msync on e500.
 543
 544 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 545
 546         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 547
 548 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 549
 550         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 551         constants is the same on 32-bit and 64-bit hosts.
 552
 553 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 554
 555         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 556         .short directives so that they can be reassembled.
 557
 558 2010-05-26  Catherine Moore <clm@codesourcery.com>
 559             David Ung  <davidu@mips.com>
 560
 561         * mips-opc.c: Change membership to I1 for instructions ssnop and
 562         ehb.
 563
 564 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 565
 566         * i386-dis.c (sib): New.
 567         (get_sib): Likewise.
 568         (print_insn): Call get_sib.
 569         OP_E_memory): Use sib.
 570
 571 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 572
 573         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 574         * mips-opc.c (I16): Remove.
 575         (mips_builtin_op): Reclassify jalx.
 576
 577 2010-05-19  Alan Modra  <amodra@gmail.com>
 578
 579         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 580         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 581
 582 2010-05-13  Alan Modra  <amodra@gmail.com>
 583
 584         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 585
 586 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 587
 588         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 589         format.
 590         (print_insn_thumb16): Add support for new %W format.
 591
 592 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 593
 594         * Makefile.in: Regenerate with automake 1.11.1.
 595         * aclocal.m4: Ditto.
 596
 597 2010-05-05  Nick Clifton  <nickc@redhat.com>
 598
 599         * po/es.po: Updated Spanish translation.
 600
 601 2010-04-22  Nick Clifton  <nickc@redhat.com>
 602
 603         * po/opcodes.pot: Updated by the Translation project.
 604         * po/vi.po: Updated Vietnamese translation.
 605
 606 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 607
 608         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 609         bits in opcode.
 610
 611 2010-04-09  Nick Clifton  <nickc@redhat.com>
 612
 613         * i386-dis.c (print_insn): Remove unused variable op.
 614         (OP_sI): Remove unused variable mask.
 615
 616 2010-04-07  Alan Modra  <amodra@gmail.com>
 617
 618         * configure: Regenerate.
 619
 620 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 621
 622         * ppc-opc.c (RBOPT): New define.
 623         ("dccci"): Enable for PPCA2.  Make operands optional.
 624         ("iccci"): Likewise.  Do not deprecate for PPC476.
 625
 626 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 627
 628         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 629
 630 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 631
 632         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 633         * Makefile.in: Regenerate.
 634         * configure.in (bfd_tic6x_arch): New.
 635         * configure: Regenerate.
 636         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 637         (disassembler): Handle TI C6X.
 638         * tic6x-dis.c: New.
 639
 640 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 641
 642         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 643
 644 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 645
 646         * dis-buf.c (buffer_read_memory): Give error for reading just
 647         before the start of memory.
 648
 649 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 650             Quentin Neill <quentin.neill@amd.com>
 651
 652         * i386-dis.c (OP_LWP_I): Removed.
 653         (reg_table): Do not use OP_LWP_I, use Iq.
 654         (OP_LWPCB_E): Remove use of names16.
 655         (OP_LWP_E): Same.
 656         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 657         should not set the Vex.length bit.
 658         * i386-tbl.h: Regenerated.
 659
 660 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 661
 662         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 663
 664 2010-02-24  Nick Clifton  <nickc@redhat.com>
 665
 666         PR binutils/6773
 667         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 668         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 669         (thumb32_opcodes): Likewise.
 670
 671 2010-02-15  Nick Clifton  <nickc@redhat.com>
 672
 673         * po/vi.po: Updated Vietnamese translation.
 674
 675 2010-02-12  Doug Evans  <dje@sebabeach.org>
 676
 677         * lm32-opinst.c: Regenerate.
 678
 679 2010-02-11  Doug Evans  <dje@sebabeach.org>
 680
 681         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 682         (print_address): Delete CGEN_PRINT_ADDRESS.
 683         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 684         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 685         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 686         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 687
 688         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 689         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 690         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 691         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 692         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 693         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 694         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 695         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 696         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 697         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 698         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 699         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 700
 701 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 702
 703         * i386-dis.c: Update copyright.
 704         * i386-gen.c: Likewise.
 705         * i386-opc.h: Likewise.
 706         * i386-opc.tbl: Likewise.
 707
 708 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 709             Sebastian Pop  <sebastian.pop@amd.com>
 710
 711         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 712         function to handle 5th imm8 operand.
 713         (PREFIX_VEX_3A48): Added.
 714         (PREFIX_VEX_3A49): Added.
 715         (VEX_W_3A48_P_2): Added.
 716         (VEX_W_3A49_P_2): Added.
 717         (prefix table): Added entries for PREFIX_VEX_3A48
 718         and PREFIX_VEX_3A49.
 719         (vex table): Added entries for VEX_W_3A48_P_2 and
 720         and VEX_W_3A49_P_2.
 721         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 722         for Vec_Imm4 operands.
 723         * i386-opc.h (enum): Added Vec_Imm4.
 724         (i386_operand_type): Added vec_imm4.
 725         * i386-opc.tbl: Add entries for vpermilp[ds].
 726         * i386-init.h: Regenerated.
 727         * i386-tbl.h: Regenerated.
 728
 729 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 730
 731         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 732         and "pwr7".  Move "a2" into alphabetical order.
 733
 734 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 735
 736         * ppc-dis.c (ppc_opts): Add titan entry.
 737         * ppc-opc.c (TITAN, MULHW): Define.
 738         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 739
 740 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 741
 742         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 743         to CPU_BDVER1_FLAGS
 744         * i386-init.h: Regenerated.
 745
 746 2010-02-03  Anthony Green  <green@moxielogic.com>
 747
 748         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 749         0x0f, and make 0x00 an illegal instruction.
 750
 751 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 752
 753         * opcodes/arm-dis.c (struct arm_private_data): New.
 754         (print_insn_coprocessor, print_insn_arm): Update to use struct
 755         arm_private_data.
 756         (is_mapping_symbol, get_map_sym_type): New functions.
 757         (get_sym_code_type): Check the symbol's section.  Do not check
 758         mapping symbols.
 759         (print_insn): Default to disassembling ARM mode code.  Check
 760         for mapping symbols separately from other symbols.  Use
 761         struct arm_private_data.
 762
 763 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 764
 765         * i386-dis.c (EXVexWdqScalar): New.
 766         (vex_scalar_w_dq_mode): Likewise.
 767         (prefix_table): Update entries for PREFIX_VEX_3899,
 768         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 769         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 770         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 771         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 772         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 773         (OP_EX): Likewise.
 774
 775 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 776
 777         * i386-dis.c (XMScalar): New.
 778         (EXdScalar): Likewise.
 779         (EXqScalar): Likewise.
 780         (EXqScalarS): Likewise.
 781         (VexScalar): Likewise.
 782         (EXdVexScalarS): Likewise.
 783         (EXqVexScalarS): Likewise.
 784         (XMVexScalar): Likewise.
 785         (scalar_mode): Likewise.
 786         (d_scalar_mode): Likewise.
 787         (d_scalar_swap_mode): Likewise.
 788         (q_scalar_mode): Likewise.
 789         (q_scalar_swap_mode): Likewise.
 790         (vex_scalar_mode): Likewise.
 791         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 792         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 793         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 794         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 795         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 796         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 797         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 798         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 799         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 800         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 801         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 802         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 803         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 804         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 805         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 806         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 807         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 808         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 809         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 810         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 811         q_scalar_mode, q_scalar_swap_mode.
 812         (OP_XMM): Handle scalar_mode.
 813         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 814         and q_scalar_swap_mode.
 815         (OP_VEX): Handle vex_scalar_mode.
 816
 817 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 818
 819         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 820
 821 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 822
 823         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 824
 825 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 826
 827         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 828
 829 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 830
 831         * i386-dis.c (Bad_Opcode): New.
 832         (bad_opcode): Likewise.
 833         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 834         (dis386_twobyte): Likewise.
 835         (reg_table): Likewise.
 836         (prefix_table): Likewise.
 837         (x86_64_table): Likewise.
 838         (vex_len_table): Likewise.
 839         (vex_w_table): Likewise.
 840         (mod_table): Likewise.
 841         (rm_table): Likewise.
 842         (float_reg): Likewise.
 843         (reg_table): Remove trailing "(bad)" entries.
 844         (prefix_table): Likewise.
 845         (x86_64_table): Likewise.
 846         (vex_len_table): Likewise.
 847         (vex_w_table): Likewise.
 848         (mod_table): Likewise.
 849         (rm_table): Likewise.
 850         (get_valid_dis386): Handle bytemode 0.
 851
 852 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 853
 854         * i386-opc.h (VEXScalar): New.
 855
 856         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 857         instructions.
 858         * i386-tbl.h: Regenerated.
 859
 860 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 861
 862         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 863
 864         * i386-opc.tbl: Add xsave64 and xrstor64.
 865         * i386-tbl.h: Regenerated.
 866
 867 2010-01-20  Nick Clifton  <nickc@redhat.com>
 868
 869         PR 11170
 870         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 871         based post-indexed addressing.
 872
 873 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 874
 875         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 876         * i386-tbl.h: Regenerated.
 877
 878 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 879
 880         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 881         comments.
 882
 883 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 884
 885         * i386-dis.c (names_mm): New.
 886         (intel_names_mm): Likewise.
 887         (att_names_mm): Likewise.
 888         (names_xmm): Likewise.
 889         (intel_names_xmm): Likewise.
 890         (att_names_xmm): Likewise.
 891         (names_ymm): Likewise.
 892         (intel_names_ymm): Likewise.
 893         (att_names_ymm): Likewise.
 894         (print_insn): Set names_mm, names_xmm and names_ymm.
 895         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 896         (OP_XMM): Likewise.
 897         (OP_EM): Likewise.
 898         (OP_EMC): Likewise.
 899         (OP_MXC): Likewise.
 900         (OP_EX): Likewise.
 901         (XMM_Fixup): Likewise.
 902         (OP_VEX): Likewise.
 903         (OP_EX_VexReg): Likewise.
 904         (OP_Vex_2src): Likewise.
 905         (OP_Vex_2src_1): Likewise.
 906         (OP_Vex_2src_2): Likewise.
 907         (OP_REG_VexI4): Likewise.
 908
 909 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 910
 911         * i386-dis.c (print_insn): Update comments.
 912
 913 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 914
 915         * i386-dis.c (rex_original): Removed.
 916         (ckprefix): Remove rex_original.
 917         (print_insn): Update comments.
 918
 919 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 920
 921         * Makefile.in: Regenerate.
 922         * configure: Regenerate.
 923
 924 2010-01-07  Doug Evans  <dje@sebabeach.org>
 925
 926         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 927         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 928         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 929         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 930         * xstormy16-ibld.c: Regenerate.
 931
 932 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 933
 934         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 935         * i386-init.h: Regenerated.
 936
 937 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 938
 939         * arm-dis.c (print_insn): Fixed search for next symbol and data
 940         dumping condition, and the initial mapping symbol state.
 941
 942 2010-01-05  Doug Evans  <dje@sebabeach.org>
 943
 944         * cgen-ibld.in: #include "cgen/basic-modes.h".
 945         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 946         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 947         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 948         * xstormy16-ibld.c: Regenerate.
 949
 950 2010-01-04  Nick Clifton  <nickc@redhat.com>
 951
 952         PR 11123
 953         * arm-dis.c (print_insn_coprocessor): Initialise value.
 954
 955 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 956
 957         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 958
 959 2010-01-02  Doug Evans  <dje@sebabeach.org>
 960
 961         * cgen-asm.in: Update copyright year.
 962         * cgen-dis.in: Update copyright year.
 963         * cgen-ibld.in: Update copyright year.
 964         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 965         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 966         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 967         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 968         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 969         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 970         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 971         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 972         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 973         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 974         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 975         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 976         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 977         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 978         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 979         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 980         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 981         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 982         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 983         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 984         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 985
 986 For older changes see ChangeLog-2009
 987 \f
 988 Local Variables:
 989 mode: change-log
 990 left-margin: 8
 991 fill-column: 74
 992 version-control: never
 993 End: