opcodes/ChangeLog

   1 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
   2
   3         * ppc-opc.c: Add comment accidentally removed by old commit.
   4         (MTMSRD_L): Delete.
   5
   6 2015-06-04  Nick Clifton  <nickc@redhat.com>
   7
   8         PR 18474
   9         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
  10
  11 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  12
  13         * arm-dis.c (arm_opcodes): Add "setpan".
  14         (thumb_opcodes): Add "setpan".
  15
  16 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  17
  18         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
  19         macros.
  20
  21 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  22
  23         * aarch64-tbl.h (aarch64_feature_rdma): New.
  24         (RDMA): New.
  25         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
  26         * aarch64-asm-2.c: Regenerate.
  27         * aarch64-dis-2.c: Regenerate.
  28         * aarch64-opc-2.c: Regenerate.
  29
  30 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  31
  32         * aarch64-tbl.h (aarch64_feature_lor): New.
  33         (LOR): New.
  34         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
  35         "stllrb", "stllrh".
  36         * aarch64-asm-2.c: Regenerate.
  37         * aarch64-dis-2.c: Regenerate.
  38         * aarch64-opc-2.c: Regenerate.
  39
  40 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
  41
  42         * aarch64-opc.c (F_ARCHEXT): New.
  43         (aarch64_sys_regs): Add "pan".
  44         (aarch64_sys_reg_supported_p): New.
  45         (aarch64_pstatefields): Add "pan".
  46         (aarch64_pstatefield_supported_p): New.
  47
  48 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  49
  50         * i386-tbl.h: Regenerate.
  51
  52 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  53
  54         * i386-dis.c (print_insn): Swap rounding mode specifier and
  55         general purpose register in Intel mode.
  56
  57 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  58
  59         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
  60         * i386-tbl.h: Regenerate.
  61
  62 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
  63
  64         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
  65         * i386-init.h: Regenerated.
  66
  67 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
  68
  69         PR binutis/18386
  70         * i386-dis.c: Add comments for '@'.
  71         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
  72         (enum x86_64_isa): New.
  73         (isa64): Likewise.
  74         (print_i386_disassembler_options): Add amd64 and intel64.
  75         (print_insn): Handle amd64 and intel64.
  76         (putop): Handle '@'.
  77         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
  78         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
  79         * i386-opc.h (AMD64): New.
  80         (CpuIntel64): Likewise.
  81         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
  82         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
  83         Mark direct call/jmp without Disp16|Disp32 as Intel64.
  84         * i386-init.h: Regenerated.
  85         * i386-tbl.h: Likewise.
  86
  87 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
  88
  89         * ppc-opc.c (IH) New define.
  90         (powerpc_opcodes) <wait>: Do not enable for POWER7.
  91         <tlbie>: Add RS operand for POWER7.
  92         <slbia>: Add IH operand for POWER6.
  93
  94 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
  95
  96         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
  97         direct branch.
  98         (jmp): Likewise.
  99         * i386-tbl.h: Regenerated.
 100
 101 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 102
 103         * configure.ac: Support bfd_iamcu_arch.
 104         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 105         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 106         CPU_IAMCU_COMPAT_FLAGS.
 107         (cpu_flags): Add CpuIAMCU.
 108         * i386-opc.h (CpuIAMCU): New.
 109         (i386_cpu_flags): Add cpuiamcu.
 110         * configure: Regenerated.
 111         * i386-init.h: Likewise.
 112         * i386-tbl.h: Likewise.
 113
 114 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 115
 116         PR binutis/18386
 117         * i386-dis.c (X86_64_E8): New.
 118         (X86_64_E9): Likewise.
 119         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 120         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 121         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 122         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 123         (putop): Handle '^'.
 124         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 125         REX_W.
 126
 127 2015-04-30  DJ Delorie  <dj@redhat.com>
 128
 129         * disassemble.c (disassembler): Choose suitable disassembler based
 130         on E_ABI.
 131         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 132         it to decode mul/div insns.
 133         * rl78-decode.c: Regenerate.
 134         * rl78-dis.c (print_insn_rl78): Rename to...
 135         (print_insn_rl78_common): ...this, take ISA parameter.
 136         (print_insn_rl78): New.
 137         (print_insn_rl78_g10): New.
 138         (print_insn_rl78_g13): New.
 139         (print_insn_rl78_g14): New.
 140         (rl78_get_disassembler): New.
 141
 142 2015-04-29  Nick Clifton  <nickc@redhat.com>
 143
 144         * po/fr.po: Updated French translation.
 145
 146 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 147
 148         * ppc-opc.c (DCBT_EO): New define.
 149         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 150         <lharx>: Likewise.
 151         <stbcx.>: Likewise.
 152         <sthcx.>: Likewise.
 153         <waitrsv>: Do not enable for POWER7 and later.
 154         <waitimpl>: Likewise.
 155         <dcbt>: Default to the two operand form of the instruction for all
 156         "old" cpus.  For "new" cpus, use the operand ordering that matches
 157         whether the cpu is server or embedded.
 158         <dcbtst>: Likewise.
 159
 160 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 161
 162         * s390-opc.c: New instruction type VV0UU2.
 163         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 164         and WFC.
 165
 166 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 169         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 170         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 171         (vfpclasspd, vfpclassps): Add %XZ.
 172
 173 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 174
 175         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 176         (PREFIX_UD_REPZ): Likewise.
 177         (PREFIX_UD_REPNZ): Likewise.
 178         (PREFIX_UD_DATA): Likewise.
 179         (PREFIX_UD_ADDR): Likewise.
 180         (PREFIX_UD_LOCK): Likewise.
 181
 182 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 183
 184         * i386-dis.c (prefix_requirement): Removed.
 185         (print_insn): Don't set prefix_requirement.  Check
 186         dp->prefix_requirement instead of prefix_requirement.
 187
 188 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 189
 190         PR binutils/17898
 191         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 192         (PREFIX_MOD_0_0FC7_REG_6): This.
 193         (PREFIX_MOD_3_0FC7_REG_6): New.
 194         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 195         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 196         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 197         PREFIX_MOD_3_0FC7_REG_7.
 198         (mod_table): Replace PREFIX_0FC7_REG_6 with
 199         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 200         PREFIX_MOD_3_0FC7_REG_7.
 201
 202 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 203
 204         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 205         (PREFIX_MANDATORY_REPNZ): Likewise.
 206         (PREFIX_MANDATORY_DATA): Likewise.
 207         (PREFIX_MANDATORY_ADDR): Likewise.
 208         (PREFIX_MANDATORY_LOCK): Likewise.
 209         (PREFIX_MANDATORY): Likewise.
 210         (PREFIX_UD_SHIFT): Set to 8
 211         (PREFIX_UD_REPZ): Updated.
 212         (PREFIX_UD_REPNZ): Likewise.
 213         (PREFIX_UD_DATA): Likewise.
 214         (PREFIX_UD_ADDR): Likewise.
 215         (PREFIX_UD_LOCK): Likewise.
 216         (PREFIX_IGNORED_SHIFT): New.
 217         (PREFIX_IGNORED_REPZ): Likewise.
 218         (PREFIX_IGNORED_REPNZ): Likewise.
 219         (PREFIX_IGNORED_DATA): Likewise.
 220         (PREFIX_IGNORED_ADDR): Likewise.
 221         (PREFIX_IGNORED_LOCK): Likewise.
 222         (PREFIX_OPCODE): Likewise.
 223         (PREFIX_IGNORED): Likewise.
 224         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 225         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 226         (three_byte_table): Likewise.
 227         (mod_table): Likewise.
 228         (mandatory_prefix): Renamed to ...
 229         (prefix_requirement): This.
 230         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 231         Update PREFIX_90 entry.
 232         (get_valid_dis386): Check prefix_requirement to see if a prefix
 233         should be ignored.
 234         (print_insn): Replace mandatory_prefix with prefix_requirement.
 235
 236 2015-04-15  Renlin Li  <renlin.li@arm.com>
 237
 238         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 239         use it for ssat and ssat16.
 240         (print_insn_thumb32): Add handle case for 'D' control code.
 241
 242 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 243             H.J. Lu  <hongjiu.lu@intel.com>
 244
 245         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 246         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 247         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 248         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 249         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 250         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 251         Fill prefix_requirement field.
 252         (struct dis386): Add prefix_requirement field.
 253         (dis386): Fill prefix_requirement field.
 254         (dis386_twobyte): Ditto.
 255         (twobyte_has_mandatory_prefix_: Remove.
 256         (reg_table): Fill prefix_requirement field.
 257         (prefix_table): Ditto.
 258         (x86_64_table): Ditto.
 259         (three_byte_table): Ditto.
 260         (xop_table): Ditto.
 261         (vex_table): Ditto.
 262         (vex_len_table): Ditto.
 263         (vex_w_table): Ditto.
 264         (mod_table): Ditto.
 265         (bad_opcode): Ditto.
 266         (print_insn): Use prefix_requirement.
 267         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 268         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 269         (float_reg): Ditto.
 270
 271 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 272
 273         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 274
 275 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 276
 277         * Makefile.in: Regenerated.
 278
 279 2015-03-25  Anton Blanchard  <anton@samba.org>
 280
 281         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 282         powerpc_opcd_indices and vle_opcd_indices once.
 283
 284 2015-03-25  Anton Blanchard  <anton@samba.org>
 285
 286         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 287
 288 2015-03-24  Terry Guo  <terry.guo@arm.com>
 289
 290         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 291         (opcode16): Likewise.
 292         (coprocessor_opcodes): Replace bit with feature struct.
 293         (neon_opcodes): Likewise.
 294         (arm_opcodes): Likewise.
 295         (thumb_opcodes): Likewise.
 296         (thumb32_opcodes): Likewise.
 297         (print_insn_coprocessor): Likewise.
 298         (print_insn_arm): Likewise.
 299         (select_arm_features): Follow new feature struct.
 300
 301 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 302
 303         * i386-dis.c (rm_table): Add clzero.
 304         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 305         Add CPU_CLZERO_FLAGS.
 306         (cpu_flags): Add CpuCLZERO.
 307         * i386-opc.h: Add CpuCLZERO.
 308         * i386-opc.tbl: Add clzero.
 309         * i386-init.h: Re-generated.
 310         * i386-tbl.h: Re-generated.
 311
 312 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 313
 314         * mips-opc.c (decode_mips_operand): Fix constraint issues
 315         with u and y operands.
 316
 317 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 318
 319         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 320
 321 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 322
 323         * s390-opc.c: Add new IBM z13 instructions.
 324         * s390-opc.txt: Likewise.
 325
 326 2015-03-10  Renlin Li  <renlin.li@arm.com>
 327
 328         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 329         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 330         related alias.
 331         * aarch64-asm-2.c: Regenerate.
 332         * aarch64-dis-2.c: Likewise.
 333         * aarch64-opc-2.c: Likewise.
 334
 335 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 336
 337         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 338
 339 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 340
 341         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 342         arch_sh_up.
 343         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 344         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 345
 346 2015-02-23  Vinay  <Vinay.G@kpit.com>
 347
 348         * rl78-decode.opc (MOV): Added space between two operands for
 349         'mov' instruction in index addressing mode.
 350         * rl78-decode.c: Regenerate.
 351
 352 2015-02-19  Pedro Alves  <palves@redhat.com>
 353
 354         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 355
 356 2015-02-10  Pedro Alves  <palves@redhat.com>
 357             Tom Tromey  <tromey@redhat.com>
 358
 359         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 360         microblaze_and, microblaze_xor.
 361         * microblaze-opc.h (opcodes): Adjust.
 362
 363 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 364
 365         * Makefile.am: Add FT32 files.
 366         * configure.ac: Handle FT32.
 367         * disassemble.c (disassembler): Call print_insn_ft32.
 368         * ft32-dis.c: New file.
 369         * ft32-opc.c: New file.
 370         * Makefile.in: Regenerate.
 371         * configure: Regenerate.
 372         * po/POTFILES.in: Regenerate.
 373
 374 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 375
 376         * nds32-asm.c (keyword_sr): Add new system registers.
 377
 378 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 379
 380         * s390-dis.c (s390_extract_operand): Support vector register
 381         operands.
 382         (s390_print_insn_with_opcode): Support new operands types and add
 383         new handling of optional operands.
 384         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 385         and include opcode/s390.h instead.
 386         (struct op_struct): New field `flags'.
 387         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 388         (dumpTable): Dump flags.
 389         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 390         string.
 391         * s390-opc.c: Add new operands types, instruction formats, and
 392         instruction masks.
 393         (s390_opformats): Add new formats for .insn.
 394         * s390-opc.txt: Add new instructions.
 395
 396 2015-01-01  Alan Modra  <amodra@gmail.com>
 397
 398         Update year range in copyright notice of all files.
 399
 400 For older changes see ChangeLog-2014
 401 \f
 402 Copyright (C) 2015 Free Software Foundation, Inc.
 403
 404 Copying and distribution of this file, with or without modification,
 405 are permitted in any medium without royalty provided the copyright
 406 notice and this notice are preserved.
 407
 408 Local Variables:
 409 mode: change-log
 410 left-margin: 8
 411 fill-column: 74
 412 version-control: never
 413 End: