1 2017-07-18 Nick Clifton <nickc@redhat.com>
4 * aarch64-opc.c: Fix spelling typos.
5 * i386-dis.c: Likewise.
7 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
9 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
10 max_addr_offset and octets variables to size_t.
12 2017-07-12 Alan Modra <amodra@gmail.com>
14 * po/da.po: Update from translationproject.org/latest/opcodes/.
22 * po/pt_BR.po: Likewise.
28 * po/zh_CN.po: Likewise.
30 2017-07-11 Yao Qi <yao.qi@linaro.org>
31 Alan Modra <amodra@gmail.com>
33 * cgen.sh: Mark generated files read-only.
34 * epiphany-asm.c: Regenerate.
35 * epiphany-desc.c: Regenerate.
36 * epiphany-desc.h: Regenerate.
37 * epiphany-dis.c: Regenerate.
38 * epiphany-ibld.c: Regenerate.
39 * epiphany-opc.c: Regenerate.
40 * epiphany-opc.h: Regenerate.
41 * fr30-asm.c: Regenerate.
42 * fr30-desc.c: Regenerate.
43 * fr30-desc.h: Regenerate.
44 * fr30-dis.c: Regenerate.
45 * fr30-ibld.c: Regenerate.
46 * fr30-opc.c: Regenerate.
47 * fr30-opc.h: Regenerate.
48 * frv-asm.c: Regenerate.
49 * frv-desc.c: Regenerate.
50 * frv-desc.h: Regenerate.
51 * frv-dis.c: Regenerate.
52 * frv-ibld.c: Regenerate.
53 * frv-opc.c: Regenerate.
54 * frv-opc.h: Regenerate.
55 * ip2k-asm.c: Regenerate.
56 * ip2k-desc.c: Regenerate.
57 * ip2k-desc.h: Regenerate.
58 * ip2k-dis.c: Regenerate.
59 * ip2k-ibld.c: Regenerate.
60 * ip2k-opc.c: Regenerate.
61 * ip2k-opc.h: Regenerate.
62 * iq2000-asm.c: Regenerate.
63 * iq2000-desc.c: Regenerate.
64 * iq2000-desc.h: Regenerate.
65 * iq2000-dis.c: Regenerate.
66 * iq2000-ibld.c: Regenerate.
67 * iq2000-opc.c: Regenerate.
68 * iq2000-opc.h: Regenerate.
69 * lm32-asm.c: Regenerate.
70 * lm32-desc.c: Regenerate.
71 * lm32-desc.h: Regenerate.
72 * lm32-dis.c: Regenerate.
73 * lm32-ibld.c: Regenerate.
74 * lm32-opc.c: Regenerate.
75 * lm32-opc.h: Regenerate.
76 * lm32-opinst.c: Regenerate.
77 * m32c-asm.c: Regenerate.
78 * m32c-desc.c: Regenerate.
79 * m32c-desc.h: Regenerate.
80 * m32c-dis.c: Regenerate.
81 * m32c-ibld.c: Regenerate.
82 * m32c-opc.c: Regenerate.
83 * m32c-opc.h: Regenerate.
84 * m32r-asm.c: Regenerate.
85 * m32r-desc.c: Regenerate.
86 * m32r-desc.h: Regenerate.
87 * m32r-dis.c: Regenerate.
88 * m32r-ibld.c: Regenerate.
89 * m32r-opc.c: Regenerate.
90 * m32r-opc.h: Regenerate.
91 * m32r-opinst.c: Regenerate.
92 * mep-asm.c: Regenerate.
93 * mep-desc.c: Regenerate.
94 * mep-desc.h: Regenerate.
95 * mep-dis.c: Regenerate.
96 * mep-ibld.c: Regenerate.
97 * mep-opc.c: Regenerate.
98 * mep-opc.h: Regenerate.
99 * mt-asm.c: Regenerate.
100 * mt-desc.c: Regenerate.
101 * mt-desc.h: Regenerate.
102 * mt-dis.c: Regenerate.
103 * mt-ibld.c: Regenerate.
104 * mt-opc.c: Regenerate.
105 * mt-opc.h: Regenerate.
106 * or1k-asm.c: Regenerate.
107 * or1k-desc.c: Regenerate.
108 * or1k-desc.h: Regenerate.
109 * or1k-dis.c: Regenerate.
110 * or1k-ibld.c: Regenerate.
111 * or1k-opc.c: Regenerate.
112 * or1k-opc.h: Regenerate.
113 * or1k-opinst.c: Regenerate.
114 * xc16x-asm.c: Regenerate.
115 * xc16x-desc.c: Regenerate.
116 * xc16x-desc.h: Regenerate.
117 * xc16x-dis.c: Regenerate.
118 * xc16x-ibld.c: Regenerate.
119 * xc16x-opc.c: Regenerate.
120 * xc16x-opc.h: Regenerate.
121 * xstormy16-asm.c: Regenerate.
122 * xstormy16-desc.c: Regenerate.
123 * xstormy16-desc.h: Regenerate.
124 * xstormy16-dis.c: Regenerate.
125 * xstormy16-ibld.c: Regenerate.
126 * xstormy16-opc.c: Regenerate.
127 * xstormy16-opc.h: Regenerate.
129 2017-07-07 Alan Modra <amodra@gmail.com>
131 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
132 * m32c-dis.c: Regenerate.
133 * mep-dis.c: Regenerate.
135 2017-07-05 Borislav Petkov <bp@suse.de>
137 * i386-dis.c: Enable ModRM.reg /6 aliases.
139 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
141 * opcodes/arm-dis.c: Support MVFR2 in disassembly
144 2017-07-04 Tristan Gingold <gingold@adacore.com>
146 * configure: Regenerate.
148 2017-07-03 Tristan Gingold <gingold@adacore.com>
150 * po/opcodes.pot: Regenerate.
152 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
154 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
155 entries to the MSA ASE instruction block.
157 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
158 Maciej W. Rozycki <macro@imgtec.com>
160 * micromips-opc.c (XPA, XPAVZ): New macros.
161 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
164 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
165 Maciej W. Rozycki <macro@imgtec.com>
167 * micromips-opc.c (I36): New macro.
168 (micromips_opcodes): Add "eretnc".
170 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
171 Andrew Bennett <andrew.bennett@imgtec.com>
173 * mips-dis.c (mips_calculate_combination_ases): Handle the
175 (parse_mips_ase_option): New function.
176 (parse_mips_dis_option): Factor out ASE option handling to the
177 new function. Call `mips_calculate_combination_ases'.
178 * mips-opc.c (XPAVZ): New macro.
179 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
180 "mfhgc0", "mthc0" and "mthgc0".
182 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
184 * mips-dis.c (mips_calculate_combination_ases): New function.
185 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
186 calculation to the new function.
187 (set_default_mips_dis_options): Call the new function.
189 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
191 * arc-dis.c (parse_disassembler_options): Use
192 FOR_EACH_DISASSEMBLER_OPTION.
194 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
196 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
197 disassembler option strings.
198 (parse_cpu_option): Likewise.
200 2017-06-28 Tamar Christina <tamar.christina@arm.com>
202 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
203 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
204 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
205 (aarch64_feature_dotprod, DOT_INSN): New.
207 * aarch64-dis-2.c: Regenerated.
209 2017-06-28 Jiong Wang <jiong.wang@arm.com>
211 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
213 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
214 Matthew Fortune <matthew.fortune@imgtec.com>
215 Andrew Bennett <andrew.bennett@imgtec.com>
217 * mips-formats.h (INT_BIAS): New macro.
218 (INT_ADJ): Redefine in INT_BIAS terms.
219 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
220 (mips_print_save_restore): New function.
221 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
222 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
224 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
225 (print_mips16_insn_arg): Call `mips_print_save_restore' for
226 OP_SAVE_RESTORE_LIST handling, factored out from here.
227 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
228 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
229 (mips_builtin_opcodes): Add "restore" and "save" entries.
230 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
232 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
234 2017-06-23 Andrew Waterman <andrew@sifive.com>
236 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
237 alias; do not mark SLTI instruction as an alias.
239 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
241 * i386-dis.c (RM_0FAE_REG_5): Removed.
242 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
243 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
244 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
245 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
246 PREFIX_MOD_3_0F01_REG_5_RM_0.
247 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
248 PREFIX_MOD_3_0FAE_REG_5.
249 (mod_table): Update MOD_0FAE_REG_5.
250 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
251 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
252 * i386-tbl.h: Regenerated.
254 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
256 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
257 * i386-opc.tbl: Likewise.
258 * i386-tbl.h: Regenerated.
260 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
262 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
264 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
267 2017-06-19 Nick Clifton <nickc@redhat.com>
270 * score-dis.c (score_opcodes): Add sentinel.
272 2017-06-16 Alan Modra <amodra@gmail.com>
274 * rx-decode.c: Regenerate.
276 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
279 * i386-dis.c (OP_E_register): Check valid bnd register.
282 2017-06-15 Nick Clifton <nickc@redhat.com>
285 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
288 2017-06-15 Nick Clifton <nickc@redhat.com>
291 * rl78-decode.opc (OP_BUF_LEN): Define.
292 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
293 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
295 * rl78-decode.c: Regenerate.
297 2017-06-15 Nick Clifton <nickc@redhat.com>
300 * bfin-dis.c (gregs): Clip index to prevent overflow.
305 2017-06-14 Nick Clifton <nickc@redhat.com>
308 * score7-dis.c (score_opcodes): Add sentinel.
310 2017-06-14 Yao Qi <yao.qi@linaro.org>
312 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
313 * arm-dis.c: Likewise.
314 * ia64-dis.c: Likewise.
315 * mips-dis.c: Likewise.
316 * spu-dis.c: Likewise.
317 * disassemble.h (print_insn_aarch64): New declaration, moved from
319 (print_insn_big_arm, print_insn_big_mips): Likewise.
320 (print_insn_i386, print_insn_ia64): Likewise.
321 (print_insn_little_arm, print_insn_little_mips): Likewise.
323 2017-06-14 Nick Clifton <nickc@redhat.com>
326 * rx-decode.opc: Include libiberty.h
327 (GET_SCALE): New macro - validates access to SCALE array.
328 (GET_PSCALE): New macro - validates access to PSCALE array.
329 (DIs, SIs, S2Is, rx_disp): Use new macros.
330 * rx-decode.c: Regenerate.
332 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
334 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
336 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
338 * arc-dis.c (enforced_isa_mask): Declare.
339 (cpu_types): Likewise.
340 (parse_cpu_option): New function.
341 (parse_disassembler_options): Use it.
342 (print_insn_arc): Use enforced_isa_mask.
343 (print_arc_disassembler_options): Document new options.
345 2017-05-24 Yao Qi <yao.qi@linaro.org>
347 * alpha-dis.c: Include disassemble.h, don't include
349 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
350 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
351 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
352 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
353 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
354 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
355 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
356 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
357 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
358 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
359 * moxie-dis.c, msp430-dis.c, mt-dis.c:
360 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
361 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
362 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
363 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
364 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
365 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
366 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
367 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
368 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
369 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
370 * z80-dis.c, z8k-dis.c: Likewise.
371 * disassemble.h: New file.
373 2017-05-24 Yao Qi <yao.qi@linaro.org>
375 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
376 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
378 2017-05-24 Yao Qi <yao.qi@linaro.org>
380 * disassemble.c (disassembler): Add arguments a, big and mach.
383 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
385 * i386-dis.c (NOTRACK_Fixup): New.
387 (NOTRACK_PREFIX): Likewise.
388 (last_active_prefix): Likewise.
389 (reg_table): Use NOTRACK on indirect call and jmp.
390 (ckprefix): Set last_active_prefix.
391 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
392 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
393 * i386-opc.h (NoTrackPrefixOk): New.
394 (i386_opcode_modifier): Add notrackprefixok.
395 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
397 * i386-tbl.h: Regenerated.
399 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
401 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
403 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
405 (print_insn_sparc): Handle new operand types.
406 * sparc-opc.c (MASK_M8): Define.
408 (v6notlet): Likewise.
419 (v9andleon): Likewise.
422 (HWS2_VM8): Likewise.
423 (sparc_opcode_archs): Add entry for "m8".
424 (sparc_opcodes): Add OSA2017 and M8 instructions
425 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
427 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
428 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
429 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
430 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
431 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
432 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
433 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
434 ASI_CORE_SELECT_COMMIT_NHT.
436 2017-05-18 Alan Modra <amodra@gmail.com>
438 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
439 * aarch64-dis.c: Likewise.
440 * aarch64-gen.c: Likewise.
441 * aarch64-opc.c: Likewise.
443 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
444 Matthew Fortune <matthew.fortune@imgtec.com>
446 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
447 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
448 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
449 (print_insn_arg) <OP_REG28>: Add handler.
450 (validate_insn_args) <OP_REG28>: Handle.
451 (print_mips16_insn_arg): Handle MIPS16 instructions that require
452 32-bit encoding and 9-bit immediates.
453 (print_insn_mips16): Handle MIPS16 instructions that require
454 32-bit encoding and MFC0/MTC0 operand decoding.
455 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
456 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
457 (RD_C0, WR_C0, E2, E2MT): New macros.
458 (mips16_opcodes): Add entries for MIPS16e2 instructions:
459 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
460 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
461 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
462 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
463 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
464 instructions, "swl", "swr", "sync" and its "sync_acquire",
465 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
466 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
467 regular/extended entries for original MIPS16 ISA revision
468 instructions whose extended forms are subdecoded in the MIPS16e2
469 ISA revision: "li", "sll" and "srl".
471 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
473 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
474 reference in CP0 move operand decoding.
476 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
478 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
480 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
482 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
484 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
485 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
486 "sync_rmb" and "sync_wmb" as aliases.
487 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
488 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
490 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
492 * arc-dis.c (parse_option): Update quarkse_em option..
493 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
495 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
497 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
499 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
501 2017-05-01 Michael Clark <michaeljclark@mac.com>
503 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
506 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
508 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
509 and branches and not synthetic data instructions.
511 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
513 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
515 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
517 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
518 * arc-opc.c (insert_r13el): New function.
520 * arc-tbl.h: Add new enter/leave variants.
522 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
524 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
526 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
528 * mips-dis.c (print_mips_disassembler_options): Add
531 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
533 * mips16-opc.c (AL): New macro.
534 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
535 of "ld" and "lw" as aliases.
537 2017-04-24 Tamar Christina <tamar.christina@arm.com>
539 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
542 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
543 Alan Modra <amodra@gmail.com>
545 * ppc-opc.c (ELEV): Define.
546 (vle_opcodes): Add se_rfgi and e_sc.
547 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
550 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
552 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
554 2017-04-21 Nick Clifton <nickc@redhat.com>
557 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
560 2017-04-13 Alan Modra <amodra@gmail.com>
562 * epiphany-desc.c: Regenerate.
563 * fr30-desc.c: Regenerate.
564 * frv-desc.c: Regenerate.
565 * ip2k-desc.c: Regenerate.
566 * iq2000-desc.c: Regenerate.
567 * lm32-desc.c: Regenerate.
568 * m32c-desc.c: Regenerate.
569 * m32r-desc.c: Regenerate.
570 * mep-desc.c: Regenerate.
571 * mt-desc.c: Regenerate.
572 * or1k-desc.c: Regenerate.
573 * xc16x-desc.c: Regenerate.
574 * xstormy16-desc.c: Regenerate.
576 2017-04-11 Alan Modra <amodra@gmail.com>
578 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
579 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
580 PPC_OPCODE_TMR for e6500.
581 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
582 (PPCVEC3): Define as PPC_OPCODE_POWER9.
583 (PPCVSX2): Define as PPC_OPCODE_POWER8.
584 (PPCVSX3): Define as PPC_OPCODE_POWER9.
585 (PPCHTM): Define as PPC_OPCODE_POWER8.
586 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
588 2017-04-10 Alan Modra <amodra@gmail.com>
590 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
591 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
592 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
593 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
595 2017-04-09 Pip Cet <pipcet@gmail.com>
597 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
598 appropriate floating-point precision directly.
600 2017-04-07 Alan Modra <amodra@gmail.com>
602 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
603 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
604 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
605 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
606 vector instructions with E6500 not PPCVEC2.
608 2017-04-06 Pip Cet <pipcet@gmail.com>
610 * Makefile.am: Add wasm32-dis.c.
611 * configure.ac: Add wasm32-dis.c to wasm32 target.
612 * disassemble.c: Add wasm32 disassembler code.
613 * wasm32-dis.c: New file.
614 * Makefile.in: Regenerate.
615 * configure: Regenerate.
616 * po/POTFILES.in: Regenerate.
617 * po/opcodes.pot: Regenerate.
619 2017-04-05 Pedro Alves <palves@redhat.com>
621 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
622 * arm-dis.c (parse_arm_disassembler_options): Constify.
623 * ppc-dis.c (powerpc_init_dialect): Constify local.
624 * vax-dis.c (parse_disassembler_options): Constify.
626 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
628 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
631 2017-03-30 Pip Cet <pipcet@gmail.com>
633 * configure.ac: Add (empty) bfd_wasm32_arch target.
634 * configure: Regenerate
635 * po/opcodes.pot: Regenerate.
637 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
639 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
641 * opcodes/sparc-opc.c (asi_table): New ASIs.
643 2017-03-29 Alan Modra <amodra@gmail.com>
645 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
647 (lookup_powerpc): Don't special case -1 dialect. Handle
649 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
650 lookup_powerpc call, pass it on second.
652 2017-03-27 Alan Modra <amodra@gmail.com>
655 * ppc-dis.c (struct ppc_mopt): Comment.
656 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
658 2017-03-27 Rinat Zelig <rinat@mellanox.com>
660 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
661 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
662 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
663 (insert_nps_misc_imm_offset): New function.
664 (extract_nps_misc imm_offset): New function.
665 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
666 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
668 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
670 * s390-mkopc.c (main): Remove vx2 check.
671 * s390-opc.txt: Remove vx2 instruction flags.
673 2017-03-21 Rinat Zelig <rinat@mellanox.com>
675 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
676 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
677 (insert_nps_imm_offset): New function.
678 (extract_nps_imm_offset): New function.
679 (insert_nps_imm_entry): New function.
680 (extract_nps_imm_entry): New function.
682 2017-03-17 Alan Modra <amodra@gmail.com>
685 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
686 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
687 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
689 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
691 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
695 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
697 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
699 2017-03-13 Andrew Waterman <andrew@sifive.com>
701 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
706 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
708 * i386-gen.c (opcode_modifiers): Replace S with Load.
709 * i386-opc.h (S): Removed.
711 (i386_opcode_modifier): Replace s with load.
712 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
713 and {evex}. Replace S with Load.
714 * i386-tbl.h: Regenerated.
716 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
718 * i386-opc.tbl: Use CpuCET on rdsspq.
719 * i386-tbl.h: Regenerated.
721 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
723 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
724 <vsx>: Do not use PPC_OPCODE_VSX3;
726 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
728 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
730 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
732 * i386-dis.c (REG_0F1E_MOD_3): New enum.
733 (MOD_0F1E_PREFIX_1): Likewise.
734 (MOD_0F38F5_PREFIX_2): Likewise.
735 (MOD_0F38F6_PREFIX_0): Likewise.
736 (RM_0F1E_MOD_3_REG_7): Likewise.
737 (PREFIX_MOD_0_0F01_REG_5): Likewise.
738 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
739 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
740 (PREFIX_0F1E): Likewise.
741 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
742 (PREFIX_0F38F5): Likewise.
743 (dis386_twobyte): Use PREFIX_0F1E.
744 (reg_table): Add REG_0F1E_MOD_3.
745 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
746 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
747 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
748 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
749 (three_byte_table): Use PREFIX_0F38F5.
750 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
751 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
752 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
753 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
754 PREFIX_MOD_3_0F01_REG_5_RM_2.
755 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
756 (cpu_flags): Add CpuCET.
757 * i386-opc.h (CpuCET): New enum.
758 (CpuUnused): Commented out.
759 (i386_cpu_flags): Add cpucet.
760 * i386-opc.tbl: Add Intel CET instructions.
761 * i386-init.h: Regenerated.
762 * i386-tbl.h: Likewise.
764 2017-03-06 Alan Modra <amodra@gmail.com>
767 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
768 (extract_raq, extract_ras, extract_rbx): New functions.
769 (powerpc_operands): Use opposite corresponding insert function.
771 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
772 register restriction.
774 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
776 * disassemble.c Include "safe-ctype.h".
777 (disassemble_init_for_target): Handle s390 init.
778 (remove_whitespace_and_extra_commas): New function.
779 (disassembler_options_cmp): Likewise.
780 * arm-dis.c: Include "libiberty.h".
782 (regnames): Use long disassembler style names.
783 Add force-thumb and no-force-thumb options.
784 (NUM_ARM_REGNAMES): Rename from this...
785 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
786 (get_arm_regname_num_options): Delete.
787 (set_arm_regname_option): Likewise.
788 (get_arm_regnames): Likewise.
789 (parse_disassembler_options): Likewise.
790 (parse_arm_disassembler_option): Rename from this...
791 (parse_arm_disassembler_options): ...to this. Make static.
792 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
793 (print_insn): Use parse_arm_disassembler_options.
794 (disassembler_options_arm): New function.
795 (print_arm_disassembler_options): Handle updated regnames.
796 * ppc-dis.c: Include "libiberty.h".
797 (ppc_opts): Add "32" and "64" entries.
798 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
799 (powerpc_init_dialect): Add break to switch statement.
800 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
801 (disassembler_options_powerpc): New function.
802 (print_ppc_disassembler_options): Use ARRAY_SIZE.
803 Remove printing of "32" and "64".
804 * s390-dis.c: Include "libiberty.h".
805 (init_flag): Remove unneeded variable.
806 (struct s390_options_t): New structure type.
807 (options): New structure.
808 (init_disasm): Rename from this...
809 (disassemble_init_s390): ...to this. Add initializations for
810 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
811 (print_insn_s390): Delete call to init_disasm.
812 (disassembler_options_s390): New function.
813 (print_s390_disassembler_options): Print using information from
815 * po/opcodes.pot: Regenerate.
817 2017-02-28 Jan Beulich <jbeulich@suse.com>
819 * i386-dis.c (PCMPESTR_Fixup): New.
820 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
821 (prefix_table): Use PCMPESTR_Fixup.
822 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
824 (vex_w_table): Delete VPCMPESTR{I,M} entries.
825 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
826 Split 64-bit and non-64-bit variants.
827 * opcodes/i386-tbl.h: Re-generate.
829 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
831 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
832 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
833 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
834 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
835 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
836 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
837 (OP_SVE_V_HSD): New macros.
838 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
839 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
840 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
841 (aarch64_opcode_table): Add new SVE instructions.
842 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
843 for rotation operands. Add new SVE operands.
844 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
845 (ins_sve_quad_index): Likewise.
846 (ins_imm_rotate): Split into...
847 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
848 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
849 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
851 (aarch64_ins_sve_addr_ri_s4): New function.
852 (aarch64_ins_sve_quad_index): Likewise.
853 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
854 * aarch64-asm-2.c: Regenerate.
855 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
856 (ext_sve_quad_index): Likewise.
857 (ext_imm_rotate): Split into...
858 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
859 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
860 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
862 (aarch64_ext_sve_addr_ri_s4): New function.
863 (aarch64_ext_sve_quad_index): Likewise.
864 (aarch64_ext_sve_index): Allow quad indices.
865 (do_misc_decoding): Likewise.
866 * aarch64-dis-2.c: Regenerate.
867 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
869 (OPD_F_OD_MASK): Widen by one bit.
870 (OPD_F_NO_ZR): Bump accordingly.
871 (get_operand_field_width): New function.
872 * aarch64-opc.c (fields): Add new SVE fields.
873 (operand_general_constraint_met_p): Handle new SVE operands.
874 (aarch64_print_operand): Likewise.
875 * aarch64-opc-2.c: Regenerate.
877 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
879 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
880 (aarch64_feature_compnum): ...this.
881 (SIMD_V8_3): Replace with...
883 (CNUM_INSN): New macro.
884 (aarch64_opcode_table): Use it for the complex number instructions.
886 2017-02-24 Jan Beulich <jbeulich@suse.com>
888 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
890 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
892 Add support for associating SPARC ASIs with an architecture level.
893 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
894 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
895 decoding of SPARC ASIs.
897 2017-02-23 Jan Beulich <jbeulich@suse.com>
899 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
900 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
902 2017-02-21 Jan Beulich <jbeulich@suse.com>
904 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
905 1 (instead of to itself). Correct typo.
907 2017-02-14 Andrew Waterman <andrew@sifive.com>
909 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
912 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
914 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
915 (aarch64_sys_reg_supported_p): Handle them.
917 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
919 * arc-opc.c (UIMM6_20R): Define.
920 (SIMM12_20): Use above.
921 (SIMM12_20R): Define.
922 (SIMM3_5_S): Use above.
923 (UIMM7_A32_11R_S): Define.
924 (UIMM7_9_S): Use above.
925 (UIMM3_13R_S): Define.
926 (SIMM11_A32_7_S): Use above.
928 (UIMM10_A32_8_S): Use above.
929 (UIMM8_8R_S): Define.
931 (arc_relax_opcodes): Use all above defines.
933 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
935 * arc-regs.h: Distinguish some of the registers different on
936 ARC700 and HS38 cpus.
938 2017-02-14 Alan Modra <amodra@gmail.com>
941 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
942 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
944 2017-02-11 Stafford Horne <shorne@gmail.com>
945 Alan Modra <amodra@gmail.com>
947 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
948 Use insn_bytes_value and insn_int_value directly instead. Don't
949 free allocated memory until function exit.
951 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
953 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
955 2017-02-03 Nick Clifton <nickc@redhat.com>
958 * aarch64-opc.c (print_register_list): Ensure that the register
959 list index will fir into the tb buffer.
960 (print_register_offset_address): Likewise.
961 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
963 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
966 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
967 instructions when the previous fetch packet ends with a 32-bit
970 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
972 * pru-opc.c: Remove vague reference to a future GDB port.
974 2017-01-20 Nick Clifton <nickc@redhat.com>
976 * po/ga.po: Updated Irish translation.
978 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
980 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
982 2017-01-13 Yao Qi <yao.qi@linaro.org>
984 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
985 if FETCH_DATA returns 0.
986 (m68k_scan_mask): Likewise.
987 (print_insn_m68k): Update code to handle -1 return value.
989 2017-01-13 Yao Qi <yao.qi@linaro.org>
991 * m68k-dis.c (enum print_insn_arg_error): New.
992 (NEXTBYTE): Replace -3 with
993 PRINT_INSN_ARG_MEMORY_ERROR.
994 (NEXTULONG): Likewise.
995 (NEXTSINGLE): Likewise.
996 (NEXTDOUBLE): Likewise.
997 (NEXTDOUBLE): Likewise.
998 (NEXTPACKED): Likewise.
999 (FETCH_ARG): Likewise.
1000 (FETCH_DATA): Update comments.
1001 (print_insn_arg): Update comments. Replace magic numbers with
1003 (match_insn_m68k): Likewise.
1005 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1007 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1008 * i386-dis-evex.h (evex_table): Updated.
1009 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1010 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1011 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1012 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1013 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1014 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1015 * i386-init.h: Regenerate.
1016 * i386-tbl.h: Ditto.
1018 2017-01-12 Yao Qi <yao.qi@linaro.org>
1020 * msp430-dis.c (msp430_singleoperand): Return -1 if
1021 msp430dis_opcode_signed returns false.
1022 (msp430_doubleoperand): Likewise.
1023 (msp430_branchinstr): Return -1 if
1024 msp430dis_opcode_unsigned returns false.
1025 (msp430x_calla_instr): Likewise.
1026 (print_insn_msp430): Likewise.
1028 2017-01-05 Nick Clifton <nickc@redhat.com>
1031 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1032 could not be matched.
1033 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1036 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1038 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1039 (aarch64_opcode_table): Use RCPC_INSN.
1041 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1043 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1045 * riscv-opcodes/all-opcodes: Likewise.
1047 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1049 * riscv-dis.c (print_insn_args): Add fall through comment.
1051 2017-01-03 Nick Clifton <nickc@redhat.com>
1053 * po/sr.po: New Serbian translation.
1054 * configure.ac (ALL_LINGUAS): Add sr.
1055 * configure: Regenerate.
1057 2017-01-02 Alan Modra <amodra@gmail.com>
1059 * epiphany-desc.h: Regenerate.
1060 * epiphany-opc.h: Regenerate.
1061 * fr30-desc.h: Regenerate.
1062 * fr30-opc.h: Regenerate.
1063 * frv-desc.h: Regenerate.
1064 * frv-opc.h: Regenerate.
1065 * ip2k-desc.h: Regenerate.
1066 * ip2k-opc.h: Regenerate.
1067 * iq2000-desc.h: Regenerate.
1068 * iq2000-opc.h: Regenerate.
1069 * lm32-desc.h: Regenerate.
1070 * lm32-opc.h: Regenerate.
1071 * m32c-desc.h: Regenerate.
1072 * m32c-opc.h: Regenerate.
1073 * m32r-desc.h: Regenerate.
1074 * m32r-opc.h: Regenerate.
1075 * mep-desc.h: Regenerate.
1076 * mep-opc.h: Regenerate.
1077 * mt-desc.h: Regenerate.
1078 * mt-opc.h: Regenerate.
1079 * or1k-desc.h: Regenerate.
1080 * or1k-opc.h: Regenerate.
1081 * xc16x-desc.h: Regenerate.
1082 * xc16x-opc.h: Regenerate.
1083 * xstormy16-desc.h: Regenerate.
1084 * xstormy16-opc.h: Regenerate.
1086 2017-01-02 Alan Modra <amodra@gmail.com>
1088 Update year range in copyright notice of all files.
1090 For older changes see ChangeLog-2016
1092 Copyright (C) 2017 Free Software Foundation, Inc.
1094 Copying and distribution of this file, with or without modification,
1095 are permitted in any medium without royalty provided the copyright
1096 notice and this notice are preserved.
1102 version-control: never