opcodes/ChangeLog

   1 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
   4
   5 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   6
   7         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
   8
   9 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
  10
  11         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
  12
  13 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
  14
  15         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
  16         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
  17         xor3>: Delete mnemonics.
  18         <cp_abort>: Rename mnemonic from ...
  19         <cpabort>: ...to this.
  20         <setb>: Change to a X form instruction.
  21         <sync>: Change to 1 operand form.
  22         <copy>: Delete mnemonic.
  23         <copy_first>: Rename mnemonic from ...
  24         <copy>: ...to this.
  25         <paste, paste.>: Delete mnemonics.
  26         <paste_last>: Rename mnemonic from ...
  27         <paste.>: ...to this.
  28
  29 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  30
  31         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
  32
  33 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
  34
  35         * s390-mkopc.c (main): Support alternate arch strings.
  36
  37 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
  38
  39         * s390-opc.txt: Fix kmctr instruction type.
  40
  41 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
  42
  43         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
  44         * i386-init.h: Regenerated.
  45
  46 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
  47
  48         * opcodes/arc-dis.c (print_insn_arc): Changed.
  49
  50 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
  51
  52         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
  53         camellia_fl.
  54
  55 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  56
  57         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
  58         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
  59         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
  60
  61 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
  62
  63         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
  64         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
  65         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
  66         PREFIX_MOD_3_0FAE_REG_4.
  67         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
  68         PREFIX_MOD_3_0FAE_REG_4.
  69         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
  70         (cpu_flags): Add CpuPTWRITE.
  71         * i386-opc.h (CpuPTWRITE): New.
  72         (i386_cpu_flags): Add cpuptwrite.
  73         * i386-opc.tbl: Add ptwrite instruction.
  74         * i386-init.h: Regenerated.
  75         * i386-tbl.h: Likewise.
  76
  77 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  78
  79         * arc-dis.h: Wrap around in extern "C".
  80
  81 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  82
  83         * aarch64-tbl.h (V8_2_INSN): New macro.
  84         (aarch64_opcode_table): Use it.
  85
  86 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  87
  88         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
  89         CORE_INSN, __FP_INSN and SIMD_INSN.
  90
  91 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  92
  93         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
  94         (aarch64_opcode_table): Update uses accordingly.
  95
  96 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
  97         Kwok Cheung Yeung  <kcy@codesourcery.com>
  98
  99         opcodes/
 100         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 101         'e_cmplwi' to 'e_cmpli' instead.
 102         (OPVUPRT, OPVUPRT_MASK): Define.
 103         (powerpc_opcodes): Add E200Z4 insns.
 104         (vle_opcodes): Add context save/restore insns.
 105
 106 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 107
 108         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 109         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 110         "j".
 111
 112 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 113
 114         * arc-nps400-tbl.h: Change block comments to GNU format.
 115         * arc-dis.c: Add new globals addrtypenames,
 116         addrtypenames_max, and addtypeunknown.
 117         (get_addrtype): New function.
 118         (print_insn_arc): Print colons and address types when
 119         required.
 120         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 121         define insert and extract functions for all address types.
 122         (arc_operands): Add operands for colon and all address
 123         types.
 124         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 125         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 126         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 127         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 128         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 129         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 130
 131 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 132
 133         * configure: Regenerated.
 134
 135 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 136
 137         * arc-dis.c (skipclass): New structure.
 138         (decodelist): New variable.
 139         (is_compatible_p): New function.
 140         (new_element): Likewise.
 141         (skip_class_p): Likewise.
 142         (find_format_from_table): Use skip_class_p function.
 143         (find_format): Decode first the extension instructions.
 144         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 145         e_flags.
 146         (parse_option): New function.
 147         (parse_disassembler_options): Likewise.
 148         (print_arc_disassembler_options): Likewise.
 149         (print_insn_arc): Use parse_disassembler_options function.  Proper
 150         select ARCv2 cpu variant.
 151         * disassemble.c (disassembler_usage): Add ARC disassembler
 152         options.
 153
 154 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 155
 156         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 157         annotation from the "nal" entry and reorder it beyond "bltzal".
 158
 159 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 160
 161         * sparc-opc.c (ldtxa): New macro.
 162         (sparc_opcodes): Use the macro defined above to add entries for
 163         the LDTXA instructions.
 164         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 165         instruction.
 166
 167 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 168
 169         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 170         and "jmpc".
 171
 172 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 173
 174         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 175         (movzb): Adjust to cover all permitted suffixes.
 176         (movzw): New.
 177         * i386-tbl.h: Re-generate.
 178
 179 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 180
 181         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 182         (lgdt): Remove Tbyte from non-64-bit variant.
 183         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 184         xsaves64, xsavec64): Remove Disp16.
 185         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 186         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 187         64-bit variants.
 188         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 189         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 190         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 191         64-bit variants.
 192         * i386-tbl.h: Re-generate.
 193
 194 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 195
 196         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 197         * i386-tbl.h: Re-generate.
 198
 199 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 200
 201         * arm-dis.c (print_insn): Fix typo in comment.
 202
 203 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 204
 205         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 206         range of ldst_elemlist operands.
 207         (print_register_list): Use PRIi64 to print the index.
 208         (aarch64_print_operand): Likewise.
 209
 210 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 211
 212         * mcore-opc.h: Remove sentinal.
 213         * mcore-dis.c (print_insn_mcore): Adjust.
 214
 215 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 216
 217         * arc-opc.c: Correct description of availability of NPS400
 218         features.
 219
 220 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 221
 222         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 223         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 224         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 225         xor3>: New mnemonics.
 226         <setb>: Change to a VX form instruction.
 227         (insert_sh6): Add support for rldixor.
 228         (extract_sh6): Likewise.
 229
 230 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 231
 232         * arc-ext.h: Wrap in extern C.
 233
 234 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 235
 236         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 237         Use same method for determining instruction length on ARC700 and
 238         NPS-400.
 239         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 240         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 241         with the NPS400 subclass.
 242         * arc-opc.c: Likewise.
 243
 244 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 245
 246         * sparc-opc.c (rdasr): New macro.
 247         (wrasr): Likewise.
 248         (rdpr): Likewise.
 249         (wrpr): Likewise.
 250         (rdhpr): Likewise.
 251         (wrhpr): Likewise.
 252         (sparc_opcodes): Use the macros above to fix and expand the
 253         definition of read/write instructions from/to
 254         asr/privileged/hyperprivileged instructions.
 255         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 256         %hva_mask_nz.  Prefer softint_set and softint_clear over
 257         set_softint and clear_softint.
 258         (print_insn_sparc): Support %ver in Rd.
 259
 260 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 261
 262         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 263         architecture according to the hardware capabilities they require.
 264
 265 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 266
 267         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 268         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 269         bfd_mach_sparc_v9{c,d,e,v,m}.
 270         * sparc-opc.c (MASK_V9C): Define.
 271         (MASK_V9D): Likewise.
 272         (MASK_V9E): Likewise.
 273         (MASK_V9V): Likewise.
 274         (MASK_V9M): Likewise.
 275         (v6): Add MASK_V9{C,D,E,V,M}.
 276         (v6notlet): Likewise.
 277         (v7): Likewise.
 278         (v8): Likewise.
 279         (v9): Likewise.
 280         (v9andleon): Likewise.
 281         (v9a): Likewise.
 282         (v9b): Likewise.
 283         (v9c): Define.
 284         (v9d): Likewise.
 285         (v9e): Likewise.
 286         (v9v): Likewise.
 287         (v9m): Likewise.
 288         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 289
 290 2016-06-15  Nick Clifton  <nickc@redhat.com>
 291
 292         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 293         constants to match expected behaviour.
 294         (nds32_parse_opcode): Likewise.  Also for whitespace.
 295
 296 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 297
 298         * arc-opc.c (extract_rhv1): Extract value from insn.
 299
 300 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 301
 302         * arc-nps400-tbl.h: Add ldbit instruction.
 303         * arc-opc.c: Add flag classes required for ldbit.
 304
 305 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 306
 307         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 308         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 309         support the above instructions.
 310
 311 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 312
 313         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 314         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 315         csma, cbba, zncv, and hofs.
 316         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 317         support the above instructions.
 318
 319 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 320
 321         * arc-nps400-tbl.h: Add andab and orab instructions.
 322
 323 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 324
 325         * arc-nps400-tbl.h: Add addl-like instructions.
 326
 327 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 328
 329         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 330
 331 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 332
 333         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 334         instructions.
 335
 336 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 337
 338         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 339         variable.
 340         (init_disasm): Handle new command line option "insnlength".
 341         (print_s390_disassembler_options): Mention new option in help
 342         output.
 343         (print_insn_s390): Use the encoded insn length when dumping
 344         unknown instructions.
 345
 346 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 347
 348         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 349          to the address and set as symbol address for LDS/ STS immediate operands.
 350
 351 2016-06-07  Alan Modra  <amodra@gmail.com>
 352
 353         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 354         cpu for "vle" to e500.
 355         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 356         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 357         (PPCNONE): Delete, substitute throughout.
 358         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 359         except for major opcode 4 and 31.
 360         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 361
 362 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 363
 364         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 365         ARM_EXT_RAS in relevant entries.
 366
 367 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 368
 369         PR binutils/20196
 370         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 371         opcodes for E6500.
 372
 373 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 374
 375         PR binutis/18386
 376         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 377         (indir_v_mode): New.
 378         Add comments for '&'.
 379         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 380         (putop): Handle '&'.
 381         (intel_operand_size): Handle indir_v_mode.
 382         (OP_E_register): Likewise.
 383         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 384         64-bit indirect call/jmp for AMD64.
 385         * i386-tbl.h: Regenerated
 386
 387 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 388
 389         * arc-dis.c (struct arc_operand_iterator): New structure.
 390         (find_format_from_table): All the old content from find_format,
 391         with some minor adjustments, and parameter renaming.
 392         (find_format_long_instructions): New function.
 393         (find_format): Rewritten.
 394         (arc_insn_length): Add LSB parameter.
 395         (extract_operand_value): New function.
 396         (operand_iterator_next): New function.
 397         (print_insn_arc): Use new functions to find opcode, and iterator
 398         over operands.
 399         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 400         (extract_nps_3bit_dst_short): New function.
 401         (insert_nps_3bit_src2_short): New function.
 402         (extract_nps_3bit_src2_short): New function.
 403         (insert_nps_bitop1_size): New function.
 404         (extract_nps_bitop1_size): New function.
 405         (insert_nps_bitop2_size): New function.
 406         (extract_nps_bitop2_size): New function.
 407         (insert_nps_bitop_mod4_msb): New function.
 408         (extract_nps_bitop_mod4_msb): New function.
 409         (insert_nps_bitop_mod4_lsb): New function.
 410         (extract_nps_bitop_mod4_lsb): New function.
 411         (insert_nps_bitop_dst_pos3_pos4): New function.
 412         (extract_nps_bitop_dst_pos3_pos4): New function.
 413         (insert_nps_bitop_ins_ext): New function.
 414         (extract_nps_bitop_ins_ext): New function.
 415         (arc_operands): Add new operands.
 416         (arc_long_opcodes): New global array.
 417         (arc_num_long_opcodes): New global.
 418         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 419
 420 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 421
 422         * nds32-asm.h: Add extern "C".
 423         * sh-opc.h: Likewise.
 424
 425 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 426
 427         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 428         0,b,limm to the rflt instruction.
 429
 430 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 431
 432         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 433         constant.
 434
 435 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 436
 437         PR gas/20145
 438         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 439         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 440         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 441         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 442         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 443         * i386-init.h: Regenerated.
 444
 445 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 446
 447         PR gas/20145
 448         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 449         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 450         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 451         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 452         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 453         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 454         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 455         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 456         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 457         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 458         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 459         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 460         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 461         CpuRegMask for AVX512.
 462         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 463         and CpuRegMask.
 464         (set_bitfield_from_cpu_flag_init): New function.
 465         (set_bitfield): Remove const on f.  Call
 466         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 467         * i386-opc.h (CpuRegMMX): New.
 468         (CpuRegXMM): Likewise.
 469         (CpuRegYMM): Likewise.
 470         (CpuRegZMM): Likewise.
 471         (CpuRegMask): Likewise.
 472         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 473         and cpuregmask.
 474         * i386-init.h: Regenerated.
 475         * i386-tbl.h: Likewise.
 476
 477 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 478
 479         PR gas/20154
 480         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 481         (opcode_modifiers): Add AMD64 and Intel64.
 482         (main): Properly verify CpuMax.
 483         * i386-opc.h (CpuAMD64): Removed.
 484         (CpuIntel64): Likewise.
 485         (CpuMax): Set to CpuNo64.
 486         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 487         (AMD64): New.
 488         (Intel64): Likewise.
 489         (i386_opcode_modifier): Add amd64 and intel64.
 490         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 491         on call and jmp.
 492         * i386-init.h: Regenerated.
 493         * i386-tbl.h: Likewise.
 494
 495 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 496
 497         PR gas/20154
 498         * i386-gen.c (main): Fail if CpuMax is incorrect.
 499         * i386-opc.h (CpuMax): Set to CpuIntel64.
 500         * i386-tbl.h: Regenerated.
 501
 502 2016-05-27  Nick Clifton  <nickc@redhat.com>
 503
 504         PR target/20150
 505         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 506         (msp430dis_opcode_unsigned): New function.
 507         (msp430dis_opcode_signed): New function.
 508         (msp430_singleoperand): Use the new opcode reading functions.
 509         Only disassenmble bytes if they were successfully read.
 510         (msp430_doubleoperand): Likewise.
 511         (msp430_branchinstr): Likewise.
 512         (msp430x_callx_instr): Likewise.
 513         (print_insn_msp430): Check that it is safe to read bytes before
 514         attempting disassembly.  Use the new opcode reading functions.
 515
 516 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 517
 518         * ppc-opc.c (CY): New define.  Document it.
 519         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 520
 521 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 522
 523         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 524         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 525         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 526         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 527         CPU_ANY_AVX_FLAGS.
 528         * i386-init.h: Regenerated.
 529
 530 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 531
 532         PR gas/20141
 533         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 534         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 535         * i386-init.h: Regenerated.
 536
 537 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 538
 539         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 540         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 541         * i386-init.h: Regenerated.
 542
 543 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 544
 545         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 546         information.
 547         (print_insn_arc): Set insn_type information.
 548         * arc-opc.c (C_CC): Add F_CLASS_COND.
 549         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 550         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 551         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 552         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 553         (brne, brne_s, jeq_s, jne_s): Likewise.
 554
 555 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 556
 557         * arc-tbl.h (neg): New instruction variant.
 558
 559 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 560
 561         * arc-dis.c (find_format, find_format, get_auxreg)
 562         (print_insn_arc): Changed.
 563         * arc-ext.h (INSERT_XOP): Likewise.
 564
 565 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 566
 567         * tic54x-dis.c (sprint_mmr): Adjust.
 568         * tic54x-opc.c: Likewise.
 569
 570 2016-05-19  Alan Modra  <amodra@gmail.com>
 571
 572         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 573
 574 2016-05-19  Alan Modra  <amodra@gmail.com>
 575
 576         * ppc-opc.c: Formatting.
 577         (NSISIGNOPT): Define.
 578         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 579
 580 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 581
 582         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 583         replacing references to `micromips_ase' throughout.
 584         (_print_insn_mips): Don't use file-level microMIPS annotation to
 585         determine the disassembly mode with the symbol table.
 586
 587 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 588
 589         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 590
 591 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 592
 593         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 594         mips64r6.
 595         * mips-opc.c (D34): New macro.
 596         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 597
 598 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 599
 600         * i386-dis.c (prefix_table): Add RDPID instruction.
 601         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 602         (cpu_flags): Add RDPID bitfield.
 603         * i386-opc.h (enum): Add RDPID element.
 604         (i386_cpu_flags): Add RDPID field.
 605         * i386-opc.tbl: Add RDPID instruction.
 606         * i386-init.h: Regenerate.
 607         * i386-tbl.h: Regenerate.
 608
 609 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 610
 611         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 612         branch type of a symbol.
 613         (print_insn): Likewise.
 614
 615 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 616
 617         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 618         Mainline Security Extensions instructions.
 619         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 620         Extensions instructions.
 621         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 622         instructions.
 623         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 624         special registers.
 625
 626 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 627
 628         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 629
 630 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 631
 632         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 633         (arcExtMap_genOpcode): Likewise.
 634         * arc-opc.c (arg_32bit_rc): Define new variable.
 635         (arg_32bit_u6): Likewise.
 636         (arg_32bit_limm): Likewise.
 637
 638 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 639
 640         * aarch64-gen.c (VERIFIER): Define.
 641         * aarch64-opc.c (VERIFIER): Define.
 642         (verify_ldpsw): Use static linkage.
 643         * aarch64-opc.h (verify_ldpsw): Remove.
 644         * aarch64-tbl.h: Use VERIFIER for verifiers.
 645
 646 2016-04-28  Nick Clifton  <nickc@redhat.com>
 647
 648         PR target/19722
 649         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 650         * aarch64-opc.c (verify_ldpsw): New function.
 651         * aarch64-opc.h (verify_ldpsw): New prototype.
 652         * aarch64-tbl.h: Add initialiser for verifier field.
 653         (LDPSW): Set verifier to verify_ldpsw.
 654
 655 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 656
 657         PR binutils/19983
 658         PR binutils/19984
 659         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 660         smaller than address size.
 661
 662 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 663
 664         * alpha-dis.c: Regenerate.
 665         * crx-dis.c: Likewise.
 666         * disassemble.c: Likewise.
 667         * epiphany-opc.c: Likewise.
 668         * fr30-opc.c: Likewise.
 669         * frv-opc.c: Likewise.
 670         * ip2k-opc.c: Likewise.
 671         * iq2000-opc.c: Likewise.
 672         * lm32-opc.c: Likewise.
 673         * lm32-opinst.c: Likewise.
 674         * m32c-opc.c: Likewise.
 675         * m32r-opc.c: Likewise.
 676         * m32r-opinst.c: Likewise.
 677         * mep-opc.c: Likewise.
 678         * mt-opc.c: Likewise.
 679         * or1k-opc.c: Likewise.
 680         * or1k-opinst.c: Likewise.
 681         * tic80-opc.c: Likewise.
 682         * xc16x-opc.c: Likewise.
 683         * xstormy16-opc.c: Likewise.
 684
 685 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 686
 687         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 688         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 689         calcsd, and calcxd instructions.
 690         * arc-opc.c (insert_nps_bitop_size): Delete.
 691         (extract_nps_bitop_size): Delete.
 692         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 693         (extract_nps_qcmp_m3): Define.
 694         (extract_nps_qcmp_m2): Define.
 695         (extract_nps_qcmp_m1): Define.
 696         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 697         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 698         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 699         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 700         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 701         NPS_QCMP_M3.
 702
 703 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 704
 705         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 706
 707 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 708
 709         * Makefile.in: Regenerated with automake 1.11.6.
 710         * aclocal.m4: Likewise.
 711
 712 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 713
 714         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 715         instructions.
 716         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 717         (extract_nps_cmem_uimm16): New function.
 718         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 719
 720 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 721
 722         * arc-dis.c (arc_insn_length): New function.
 723         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 724         (find_format): Change insnLen parameter to unsigned.
 725
 726 2016-04-13  Nick Clifton  <nickc@redhat.com>
 727
 728         PR target/19937
 729         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 730         the LD.B and LD.BU instructions.
 731
 732 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 733
 734         * arc-dis.c (find_format): Check for extension flags.
 735         (print_flags): New function.
 736         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 737         .extAuxRegister.
 738         * arc-ext.c (arcExtMap_coreRegName): Use
 739         LAST_EXTENSION_CORE_REGISTER.
 740         (arcExtMap_coreReadWrite): Likewise.
 741         (dump_ARC_extmap): Update printing.
 742         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 743         (arc_aux_regs): Add cpu field.
 744         * arc-regs.h: Add cpu field, lower case name aux registers.
 745
 746 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 747
 748         * arc-tbl.h: Add rtsc, sleep with no arguments.
 749
 750 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 751
 752         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 753         Initialize.
 754         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 755         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 756         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 757         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 758         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 759         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 760         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 761         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 762         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 763         (arc_opcode arc_opcodes): Null terminate the array.
 764         (arc_num_opcodes): Remove.
 765         * arc-ext.h (INSERT_XOP): Define.
 766         (extInstruction_t): Likewise.
 767         (arcExtMap_instName): Delete.
 768         (arcExtMap_insn): New function.
 769         (arcExtMap_genOpcode): Likewise.
 770         * arc-ext.c (ExtInstruction): Remove.
 771         (create_map): Zero initialize instruction fields.
 772         (arcExtMap_instName): Remove.
 773         (arcExtMap_insn): New function.
 774         (dump_ARC_extmap): More info while debuging.
 775         (arcExtMap_genOpcode): New function.
 776         * arc-dis.c (find_format): New function.
 777         (print_insn_arc): Use find_format.
 778         (arc_get_disassembler): Enable dump_ARC_extmap only when
 779         debugging.
 780
 781 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 782
 783         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 784         instruction bits out.
 785
 786 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 787
 788         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 789         * arc-opc.c (arc_flag_operands): Add new flags.
 790         (arc_flag_classes): Add new classes.
 791
 792 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 793
 794         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 795
 796 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 797
 798         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 799         encode1, rflt, crc16, and crc32 instructions.
 800         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 801         (arc_flag_classes): Add C_NPS_R.
 802         (insert_nps_bitop_size_2b): New function.
 803         (extract_nps_bitop_size_2b): Likewise.
 804         (insert_nps_bitop_uimm8): Likewise.
 805         (extract_nps_bitop_uimm8): Likewise.
 806         (arc_operands): Add new operand entries.
 807
 808 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 809
 810         * arc-regs.h: Add a new subclass field.  Add double assist
 811         accumulator register values.
 812         * arc-tbl.h: Use DPA subclass to mark the double assist
 813         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 814         * arc-opc.c (RSP): Define instead of SP.
 815         (arc_aux_regs): Add the subclass field.
 816
 817 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 818
 819         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 820
 821 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 822
 823         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 824         NPS_R_SRC1.
 825
 826 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 827
 828         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 829         issues.  No functional changes.
 830
 831 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 832
 833         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 834         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 835         (RTT): Remove duplicate.
 836         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 837         (PCT_CONFIG*): Remove.
 838         (D1L, D1H, D2H, D2L): Define.
 839
 840 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 841
 842         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 843
 844 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 845
 846         * arc-tbl.h (invld07): Remove.
 847         * arc-ext-tbl.h: New file.
 848         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 849         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 850
 851 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 852
 853         Fix -Wstack-usage warnings.
 854         * aarch64-dis.c (print_operands): Substitute size.
 855         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 856
 857 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 858
 859         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 860         to get a proper diagnostic when an invalid ASR register is used.
 861
 862 2016-03-22  Nick Clifton  <nickc@redhat.com>
 863
 864         * configure: Regenerate.
 865
 866 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 867
 868         * arc-nps400-tbl.h: New file.
 869         * arc-opc.c: Add top level comment.
 870         (insert_nps_3bit_dst): New function.
 871         (extract_nps_3bit_dst): New function.
 872         (insert_nps_3bit_src2): New function.
 873         (extract_nps_3bit_src2): New function.
 874         (insert_nps_bitop_size): New function.
 875         (extract_nps_bitop_size): New function.
 876         (arc_flag_operands): Add nps400 entries.
 877         (arc_flag_classes): Add nps400 entries.
 878         (arc_operands): Add nps400 entries.
 879         (arc_opcodes): Add nps400 include.
 880
 881 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 882
 883         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 884         the new class enum values.
 885
 886 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 887
 888         * arc-dis.c (print_insn_arc): Handle nps400.
 889
 890 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 891
 892         * arc-opc.c (BASE): Delete.
 893
 894 2016-03-18  Nick Clifton  <nickc@redhat.com>
 895
 896         PR target/19721
 897         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 898         of MOV insn that aliases an ORR insn.
 899
 900 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 901
 902         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 903
 904 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 905
 906         * mcore-opc.h: Add const qualifiers.
 907         * microblaze-opc.h (struct op_code_struct): Likewise.
 908         * sh-opc.h: Likewise.
 909         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 910         (tic4x_print_op): Likewise.
 911
 912 2016-03-02  Alan Modra  <amodra@gmail.com>
 913
 914         * or1k-desc.h: Regenerate.
 915         * fr30-ibld.c: Regenerate.
 916         * rl78-decode.c: Regenerate.
 917
 918 2016-03-01  Nick Clifton  <nickc@redhat.com>
 919
 920         PR target/19747
 921         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 922
 923 2016-02-24  Renlin Li  <renlin.li@arm.com>
 924
 925         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 926         (print_insn_coprocessor): Support fp16 instructions.
 927
 928 2016-02-24  Renlin Li  <renlin.li@arm.com>
 929
 930         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 931         vminnm, vrint(mpna).
 932
 933 2016-02-24  Renlin Li  <renlin.li@arm.com>
 934
 935         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 936         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 937
 938 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 939
 940         * i386-dis.c (print_insn): Parenthesize expression to prevent
 941         truncated addresses.
 942         (OP_J): Likewise.
 943
 944 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 945             Janek van Oirschot  <jvanoirs@synopsys.com>
 946
 947         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 948         variable.
 949
 950 2016-02-04  Nick Clifton  <nickc@redhat.com>
 951
 952         PR target/19561
 953         * msp430-dis.c (print_insn_msp430): Add a special case for
 954         decoding an RRC instruction with the ZC bit set in the extension
 955         word.
 956
 957 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 958
 959         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 960         * epiphany-ibld.c: Regenerate.
 961         * fr30-ibld.c: Regenerate.
 962         * frv-ibld.c: Regenerate.
 963         * ip2k-ibld.c: Regenerate.
 964         * iq2000-ibld.c: Regenerate.
 965         * lm32-ibld.c: Regenerate.
 966         * m32c-ibld.c: Regenerate.
 967         * m32r-ibld.c: Regenerate.
 968         * mep-ibld.c: Regenerate.
 969         * mt-ibld.c: Regenerate.
 970         * or1k-ibld.c: Regenerate.
 971         * xc16x-ibld.c: Regenerate.
 972         * xstormy16-ibld.c: Regenerate.
 973
 974 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 975
 976         * epiphany-dis.c: Regenerated from latest cpu files.
 977
 978 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 979
 980         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 981         test bit.
 982
 983 2016-01-25  Renlin Li  <renlin.li@arm.com>
 984
 985         * arm-dis.c (mapping_symbol_for_insn): New function.
 986         (find_ifthen_state): Call mapping_symbol_for_insn().
 987
 988 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 989
 990         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 991         of MSR UAO immediate operand.
 992
 993 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 994
 995         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 996         instruction support.
 997
 998 2016-01-17  Alan Modra  <amodra@gmail.com>
 999
1000         * configure: Regenerate.
1001
1002 2016-01-14  Nick Clifton  <nickc@redhat.com>
1003
1004         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1005         instructions that can support stack pointer operations.
1006         * rl78-decode.c: Regenerate.
1007         * rl78-dis.c: Fix display of stack pointer in MOVW based
1008         instructions.
1009
1010 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1011
1012         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1013         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1014         erxtatus_el1 and erxaddr_el1.
1015
1016 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1017
1018         * arm-dis.c (arm_opcodes): Add "esb".
1019         (thumb_opcodes): Likewise.
1020
1021 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1022
1023         * ppc-opc.c <xscmpnedp>: Delete.
1024         <xvcmpnedp>: Likewise.
1025         <xvcmpnedp.>: Likewise.
1026         <xvcmpnesp>: Likewise.
1027         <xvcmpnesp.>: Likewise.
1028
1029 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1030
1031         PR gas/13050
1032         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1033         addition to ISA_A.
1034
1035 2016-01-01  Alan Modra  <amodra@gmail.com>
1036
1037         Update year range in copyright notice of all files.
1038
1039 For older changes see ChangeLog-2015
1040 \f
1041 Copyright (C) 2016 Free Software Foundation, Inc.
1042
1043 Copying and distribution of this file, with or without modification,
1044 are permitted in any medium without royalty provided the copyright
1045 notice and this notice are preserved.
1046
1047 Local Variables:
1048 mode: change-log
1049 left-margin: 8
1050 fill-column: 74
1051 version-control: never
1052 End: