opcodes/ChangeLog

   1 2019-12-11  Alan Modra  <amodra@gmail.com>
   2
   3         * vax-dis.c (NEXTLONG): Avoid signed overflow.
   4
   5 2019-12-11  Alan Modra  <amodra@gmail.com>
   6
   7         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
   8         sign extend using shifts.
   9
  10 2019-12-11  Alan Modra  <amodra@gmail.com>
  11
  12         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
  13
  14 2019-12-11  Alan Modra  <amodra@gmail.com>
  15
  16         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
  17         on NULL registertable entry.
  18         (tic4x_hash_opcode): Use unsigned arithmetic.
  19
  20 2019-12-11  Alan Modra  <amodra@gmail.com>
  21
  22         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
  23
  24 2019-12-11  Alan Modra  <amodra@gmail.com>
  25
  26         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
  27         (bit_extract_simple, sign_extend): Likewise.
  28
  29 2019-12-11  Alan Modra  <amodra@gmail.com>
  30
  31         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
  32
  33 2019-12-11  Alan Modra  <amodra@gmail.com>
  34
  35         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
  36
  37 2019-12-11  Alan Modra  <amodra@gmail.com>
  38
  39         * m68k-dis.c (COERCE32): Cast value first.
  40         (NEXTLONG, NEXTULONG): Avoid signed overflow.
  41
  42 2019-12-11  Alan Modra  <amodra@gmail.com>
  43
  44         * h8300-dis.c (extract_immediate): Avoid signed overflow.
  45         (bfd_h8_disassemble): Likewise.
  46
  47 2019-12-11  Alan Modra  <amodra@gmail.com>
  48
  49         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
  50         past end of operands array.
  51
  52 2019-12-11  Alan Modra  <amodra@gmail.com>
  53
  54         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
  55         overflow when collecting bytes of a number.
  56
  57 2019-12-11  Alan Modra  <amodra@gmail.com>
  58
  59         * cris-dis.c (print_with_operands): Avoid signed integer
  60         overflow when collecting bytes of a 32-bit integer.
  61
  62 2019-12-11  Alan Modra  <amodra@gmail.com>
  63
  64         * cr16-dis.c (EXTRACT, SBM): Rewrite.
  65         (cr16_match_opcode): Delete duplicate bcond test.
  66
  67 2019-12-11  Alan Modra  <amodra@gmail.com>
  68
  69         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
  70         (SIGNBIT): New.
  71         (MASKBITS, SIGNEXTEND): Rewrite.
  72         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
  73         unsigned arithmetic, instead assign result of SIGNEXTEND back
  74         to x.
  75         (fmtconst_val): Use 1u in shift expression.
  76
  77 2019-12-11  Alan Modra  <amodra@gmail.com>
  78
  79         * arc-dis.c (find_format_from_table): Use ull constant when
  80         shifting by up to 32.
  81
  82 2019-12-11  Alan Modra  <amodra@gmail.com>
  83
  84         PR 25270
  85         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
  86         false when field is zero for sve_size_tsz_bhs.
  87
  88 2019-12-11  Alan Modra  <amodra@gmail.com>
  89
  90         * epiphany-ibld.c: Regenerate.
  91
  92 2019-12-10  Alan Modra  <amodra@gmail.com>
  93
  94         PR 24960
  95         * disassemble.c (disassemble_free_target): New function.
  96
  97 2019-12-10  Alan Modra  <amodra@gmail.com>
  98
  99         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 100         * disassemble.c (disassemble_init_for_target): Likewise.
 101         * bpf-dis.c: Regenerate.
 102         * epiphany-dis.c: Regenerate.
 103         * fr30-dis.c: Regenerate.
 104         * frv-dis.c: Regenerate.
 105         * ip2k-dis.c: Regenerate.
 106         * iq2000-dis.c: Regenerate.
 107         * lm32-dis.c: Regenerate.
 108         * m32c-dis.c: Regenerate.
 109         * m32r-dis.c: Regenerate.
 110         * mep-dis.c: Regenerate.
 111         * mt-dis.c: Regenerate.
 112         * or1k-dis.c: Regenerate.
 113         * xc16x-dis.c: Regenerate.
 114         * xstormy16-dis.c: Regenerate.
 115
 116 2019-12-10  Alan Modra  <amodra@gmail.com>
 117
 118         * ppc-dis.c (private): Delete variable.
 119         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 120         (powerpc_init_dialect): Don't use global private.
 121
 122 2019-12-10  Alan Modra  <amodra@gmail.com>
 123
 124         * s12z-opc.c: Formatting.
 125
 126 2019-12-08  Alan Modra  <amodra@gmail.com>
 127
 128         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 129         registers.
 130
 131 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 132
 133         * aarch64-tbl.h (aarch64_feature_crypto,
 134         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 135         CRYPTO_V8_2_INSN): Delete.
 136
 137 2019-12-05  Alan Modra  <amodra@gmail.com>
 138
 139         PR 25249
 140         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 141         (struct string_buf): New.
 142         (strbuf): New function.
 143         (get_field): Use strbuf rather than strdup of local temp.
 144         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 145         (get_field_rfsl, get_field_imm15): Likewise.
 146         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 147         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 148         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 149         get_field functions.
 150
 151 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 152
 153         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 154         * i386-tbl.h: Re-generate.
 155
 156 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 159
 160 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 161
 162         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 163         forms.
 164         (xbegin): Drop DefaultSize.
 165         * i386-tbl.h: Re-generate.
 166
 167 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 168
 169         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 170         Change the coproc CRC conditions to use the extension
 171         feature set, second word, base on ARM_EXT2_CRC.
 172
 173 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 174
 175         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 176         * i386-tbl.h: Re-generate.
 177
 178 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 179
 180         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 181         JumpInterSegment, and JumpAbsolute entries.
 182         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 183         JUMP_ABSOLUTE): Define.
 184         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 185         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 186         fields.
 187         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 188         JumpInterSegment): Define.
 189         * i386-tbl.h: Re-generate.
 190
 191 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-gen.c (operand_type_init): Remove
 194         OPERAND_TYPE_JUMPABSOLUTE entry.
 195         (opcode_modifiers): Add JumpAbsolute entry.
 196         (operand_types): Remove JumpAbsolute entry.
 197         * i386-opc.h (JumpAbsolute): Move between enums.
 198         (struct i386_opcode_modifier): Add jumpabsolute field.
 199         (union i386_operand_type): Remove jumpabsolute field.
 200         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 201         * i386-init.h, i386-tbl.h: Re-generate.
 202
 203 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 204
 205         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 206         (operand_types): Remove AnySize entry.
 207         * i386-opc.h (AnySize): Move between enums.
 208         (struct i386_opcode_modifier): Add anysize field.
 209         (OTUnused): Un-comment.
 210         (union i386_operand_type): Remove anysize field.
 211         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 212         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 213         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 214         AnySize.
 215         * i386-tbl.h: Re-generate.
 216
 217 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 218
 219         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 220         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 221         use the floating point register (FPR).
 222
 223 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 224
 225         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 226         cmode 1101.
 227         (is_mve_encoding_conflict): Update cmode conflict checks for
 228         MVE_VMVN_IMM.
 229
 230 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 231
 232         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 233         entry.
 234         (operand_types): Remove EsSeg entry.
 235         (main): Replace stale use of OTMax.
 236         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 237         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 238         (EsSeg): Delete.
 239         (OTUnused): Comment out.
 240         (union i386_operand_type): Remove esseg field.
 241         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 242         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 243         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 244         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 245         * i386-init.h, i386-tbl.h: Re-generate.
 246
 247 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 248
 249         * i386-gen.c (operand_instances): Add RegB entry.
 250         * i386-opc.h (enum operand_instance): Add RegB.
 251         * i386-opc.tbl (RegC, RegD, RegB): Define.
 252         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 253         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 254         monitorx, mwaitx): Drop ImmExt and convert encodings
 255         accordingly.
 256         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 257         (edx, rdx): Add Instance=RegD.
 258         (ebx, rbx): Add Instance=RegB.
 259         * i386-tbl.h: Re-generate.
 260
 261 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 262
 263         * i386-gen.c (operand_type_init): Adjust
 264         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 265         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 266         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 267         (operand_instances): New.
 268         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 269         (output_operand_type): New parameter "instance". Process it.
 270         (process_i386_operand_type): New local variable "instance".
 271         (main): Adjust static assertions.
 272         * i386-opc.h (INSTANCE_WIDTH): Define.
 273         (enum operand_instance): New.
 274         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 275         (union i386_operand_type): Replace acc, inoutportreg, and
 276         shiftcount by instance.
 277         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 278         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 279         Add Instance=.
 280         * i386-init.h, i386-tbl.h: Re-generate.
 281
 282 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 283
 284         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 285         smaxp/sminp entries' "tied_operand" field to 2.
 286
 287 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 288
 289         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 290         "index" local variable by that of the already existing "num".
 291
 292 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 293
 294         PR gas/25167
 295         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 296         * i386-tbl.h: Regenerated.
 297
 298 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 299
 300         * i386-gen.c (operand_type_init): Add Class= to
 301         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 302         OPERAND_TYPE_REGBND entry.
 303         (operand_classes): Add RegMask and RegBND entries.
 304         (operand_types): Drop RegMask and RegBND entry.
 305         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 306         (RegMask, RegBND): Delete.
 307         (union i386_operand_type): Remove regmask and regbnd fields.
 308         * i386-opc.tbl (RegMask, RegBND): Define.
 309         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 310         Class=RegBND.
 311         * i386-init.h, i386-tbl.h: Re-generate.
 312
 313 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 314
 315         * i386-gen.c (operand_type_init): Add Class= to
 316         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 317         OPERAND_TYPE_REGZMM entries.
 318         (operand_classes): Add RegMMX and RegSIMD entries.
 319         (operand_types): Drop RegMMX and RegSIMD entries.
 320         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 321         (RegMMX, RegSIMD): Delete.
 322         (union i386_operand_type): Remove regmmx and regsimd fields.
 323         * i386-opc.tbl (RegMMX): Define.
 324         (RegXMM, RegYMM, RegZMM): Add Class=.
 325         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 326         Class=RegSIMD.
 327         * i386-init.h, i386-tbl.h: Re-generate.
 328
 329 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 330
 331         * i386-gen.c (operand_type_init): Add Class= to
 332         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 333         entries.
 334         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 335         (operand_types): Drop Control, Debug, and Test entries.
 336         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 337         (Control, Debug, Test): Delete.
 338         (union i386_operand_type): Remove control, debug, and test
 339         fields.
 340         * i386-opc.tbl (Control, Debug, Test): Define.
 341         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 342         Class=RegDR, and Test by Class=RegTR.
 343         * i386-init.h, i386-tbl.h: Re-generate.
 344
 345 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 346
 347         * i386-gen.c (operand_type_init): Add Class= to
 348         OPERAND_TYPE_SREG entry.
 349         (operand_classes): Add SReg entry.
 350         (operand_types): Drop SReg entry.
 351         * i386-opc.h (enum operand_class): Add SReg.
 352         (SReg): Delete.
 353         (union i386_operand_type): Remove sreg field.
 354         * i386-opc.tbl (SReg): Define.
 355         * i386-reg.tbl: Replace SReg by Class=SReg.
 356         * i386-init.h, i386-tbl.h: Re-generate.
 357
 358 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 359
 360         * i386-gen.c (operand_type_init): Add Class=. New
 361         OPERAND_TYPE_ANYIMM entry.
 362         (operand_classes): New.
 363         (operand_types): Drop Reg entry.
 364         (output_operand_type): New parameter "class". Process it.
 365         (process_i386_operand_type): New local variable "class".
 366         (main): Adjust static assertions.
 367         * i386-opc.h (CLASS_WIDTH): Define.
 368         (enum operand_class): New.
 369         (Reg): Replace by Class. Adjust comment.
 370         (union i386_operand_type): Replace reg by class.
 371         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 372         Class=.
 373         * i386-reg.tbl: Replace Reg by Class=Reg.
 374         * i386-init.h: Re-generate.
 375
 376 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 377
 378         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 379         (aarch64_opcode_table): Add data gathering hint mnemonic.
 380         * opcodes/aarch64-dis-2.c: Account for new instruction.
 381
 382 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 383
 384         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 385
 386
 387 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 388
 389         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 390         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 391         aarch64_feature_f64mm): New feature sets.
 392         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 393         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 394         instructions.
 395         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 396         macros.
 397         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 398         (OP_SVE_QQQ): New qualifier.
 399         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 400         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 401         the movprfx constraint.
 402         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 403         (aarch64_opcode_table): Define new instructions smmla,
 404         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 405         uzip{1/2}, trn{1/2}.
 406         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 407         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 408         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 409         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 410         Account for new instructions.
 411         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 412         S4x32 operand.
 413         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 414
 415 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 416 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 417
 418         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 419         Armv8.6-A.
 420         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 421         (neon_opcodes): Add bfloat SIMD instructions.
 422         (print_insn_coprocessor): Add new control character %b to print
 423         condition code without checking cp_num.
 424         (print_insn_neon): Account for BFloat16 instructions that have no
 425         special top-byte handling.
 426
 427 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 428 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 429
 430         * arm-dis.c (print_insn_coprocessor,
 431         print_insn_generic_coprocessor): Create wrapper functions around
 432         the implementation of the print_insn_coprocessor control codes.
 433         (print_insn_coprocessor_1): Original print_insn_coprocessor
 434         function that now takes which array to look at as an argument.
 435         (print_insn_arm): Use both print_insn_coprocessor and
 436         print_insn_generic_coprocessor.
 437         (print_insn_thumb32): As above.
 438
 439 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 440 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 441
 442         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 443         in reglane special case.
 444         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 445         aarch64_find_next_opcode): Account for new instructions.
 446         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 447         in reglane special case.
 448         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 449         new AARCH64_OPND_QLF_S_2H qualifier.
 450         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 451         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 452         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 453         sets.
 454         (BFLOAT_SVE, BFLOAT): New feature set macros.
 455         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 456         instructions.
 457         (aarch64_opcode_table): Define new instructions bfdot,
 458         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 459         bfcvtn2, bfcvt.
 460
 461 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 462 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 463
 464         * aarch64-tbl.h (ARMV8_6): New macro.
 465
 466 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 467
 468         * i386-dis.c (prefix_table): Add mcommit.
 469         (rm_table): Add rdpru.
 470         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 471         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 472         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 473         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 474         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 475         * i386-opc.tbl (mcommit, rdpru): New.
 476         * i386-init.h, i386-tbl.h: Re-generate.
 477
 478 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 479
 480         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 481         "names32" instead.
 482         (OP_Monitor): Drop local variable "op1_names", re-purpose
 483         "names" for it instead, and replace former "names" uses by
 484         "names32" ones.
 485
 486 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 487
 488         PR/gas 25167
 489         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 490         operand-less forms.
 491         * opcodes/i386-tbl.h: Re-generate.
 492
 493 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 494
 495         * i386-dis.c (OP_Mwaitx): Delete.
 496         (prefix_table): Use OP_Mwait for mwaitx entry.
 497         (OP_Mwait): Also handle mwaitx.
 498
 499 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 500
 501         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 502         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 503         (prefix_table): Add respective entries.
 504         (rm_table): Link to those entries.
 505
 506 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 507
 508         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 509         (REG_0F1C_P_0_MOD_0): ... this.
 510         (REG_0F1E_MOD_3): Rename to ...
 511         (REG_0F1E_P_1_MOD_3): ... this.
 512         (RM_0F01_REG_5): Rename to ...
 513         (RM_0F01_REG_5_MOD_3): ... this.
 514         (RM_0F01_REG_7): Rename to ...
 515         (RM_0F01_REG_7_MOD_3): ... this.
 516         (RM_0F1E_MOD_3_REG_7): Rename to ...
 517         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 518         (RM_0FAE_REG_6): Rename to ...
 519         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 520         (RM_0FAE_REG_7): Rename to ...
 521         (RM_0FAE_REG_7_MOD_3): ... this.
 522         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 523         (PREFIX_0F01_REG_5_MOD_0): ... this.
 524         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 525         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 526         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 527         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 528         (PREFIX_0FAE_REG_0): Rename to ...
 529         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 530         (PREFIX_0FAE_REG_1): Rename to ...
 531         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 532         (PREFIX_0FAE_REG_2): Rename to ...
 533         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 534         (PREFIX_0FAE_REG_3): Rename to ...
 535         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 536         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 537         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 538         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 539         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 540         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 541         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 542         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 543         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 544         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 545         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 546         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 547         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 548         (PREFIX_0FAE_REG_7): Rename to ...
 549         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 550         (PREFIX_MOD_0_0FC3): Rename to ...
 551         (PREFIX_0FC3_MOD_0): ... this.
 552         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 553         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 554         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 555         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 556         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 557         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 558         (reg_table, prefix_table, mod_table, rm_table): Adjust
 559         accordingly.
 560
 561 2019-11-04  Nick Clifton  <nickc@redhat.com>
 562
 563         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 564         of a v850 system register.  Move the v850_sreg_names array into
 565         this function.
 566         (get_v850_reg_name): Likewise for ordinary register names.
 567         (get_v850_vreg_name): Likewise for vector register names.
 568         (get_v850_cc_name): Likewise for condition codes.
 569         * get_v850_float_cc_name): Likewise for floating point condition
 570         codes.
 571         (get_v850_cacheop_name): Likewise for cache-ops.
 572         (get_v850_prefop_name): Likewise for pref-ops.
 573         (disassemble): Use the new accessor functions.
 574
 575 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 576
 577         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 578         immediate for the writeback form of ldraa/ldrab if it is 0.
 579         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 580         * aarch64-opc-2.c: Regenerated.
 581
 582 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 583
 584         * i386-gen.c (operand_type_shorthands): Delete.
 585         (operand_type_init): Expand previous shorthands.
 586         (set_bitfield_from_shorthand): Rename back to ...
 587         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 588         of operand_type_init[].
 589         (set_bitfield): Adjust call to the above function.
 590         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 591         RegXMM, RegYMM, RegZMM): Define.
 592         * i386-reg.tbl: Expand prior shorthands.
 593
 594 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 595
 596         * i386-gen.c (output_i386_opcode): Change order of fields
 597         emitted to output.
 598         * i386-opc.h (struct insn_template): Move operands field.
 599         Convert extension_opcode field to unsigned short.
 600         * i386-tbl.h: Re-generate.
 601
 602 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 603
 604         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 605         of W.
 606         * i386-opc.h (W): Extend comment.
 607         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 608         general purpose variants not allowing for byte operands.
 609         * i386-tbl.h: Re-generate.
 610
 611 2019-10-29  Nick Clifton  <nickc@redhat.com>
 612
 613         * tic30-dis.c (print_branch): Correct size of operand array.
 614
 615 2019-10-29  Nick Clifton  <nickc@redhat.com>
 616
 617         * d30v-dis.c (print_insn): Check that operand index is valid
 618         before attempting to access the operands array.
 619
 620 2019-10-29  Nick Clifton  <nickc@redhat.com>
 621
 622         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 623         locating the bit to be tested.
 624
 625 2019-10-29  Nick Clifton  <nickc@redhat.com>
 626
 627         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 628         values.
 629         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 630         (print_insn_s12z):  Check for illegal size values.
 631
 632 2019-10-28  Nick Clifton  <nickc@redhat.com>
 633
 634         * csky-dis.c (csky_chars_to_number): Check for a negative
 635         count. Use an unsigned integer to construct the return value.
 636
 637 2019-10-28  Nick Clifton  <nickc@redhat.com>
 638
 639         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 640         operand buffer.  Set value to 15 not 13.
 641         (get_register_operand): Use OPERAND_BUFFER_LEN.
 642         (get_indirect_operand): Likewise.
 643         (print_two_operand): Likewise.
 644         (print_three_operand): Likewise.
 645         (print_oar_insn): Likewise.
 646
 647 2019-10-28  Nick Clifton  <nickc@redhat.com>
 648
 649         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 650         (bit_extract_simple): Likewise.
 651         (bit_copy): Likewise.
 652         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 653         index_offset array are not accessed.
 654
 655 2019-10-28  Nick Clifton  <nickc@redhat.com>
 656
 657         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 658         operand.
 659
 660 2019-10-25  Nick Clifton  <nickc@redhat.com>
 661
 662         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 663         access to opcodes.op array element.
 664
 665 2019-10-23  Nick Clifton  <nickc@redhat.com>
 666
 667         * rx-dis.c (get_register_name): Fix spelling typo in error
 668         message.
 669         (get_condition_name, get_flag_name, get_double_register_name)
 670         (get_double_register_high_name, get_double_register_low_name)
 671         (get_double_control_register_name, get_double_condition_name)
 672         (get_opsize_name, get_size_name): Likewise.
 673
 674 2019-10-22  Nick Clifton  <nickc@redhat.com>
 675
 676         * rx-dis.c (get_size_name): New function.  Provides safe
 677         access to name array.
 678         (get_opsize_name): Likewise.
 679         (print_insn_rx): Use the accessor functions.
 680
 681 2019-10-16  Nick Clifton  <nickc@redhat.com>
 682
 683         * rx-dis.c (get_register_name): New function.  Provides safe
 684         access to name array.
 685         (get_condition_name, get_flag_name, get_double_register_name)
 686         (get_double_register_high_name, get_double_register_low_name)
 687         (get_double_control_register_name, get_double_condition_name):
 688         Likewise.
 689         (print_insn_rx): Use the accessor functions.
 690
 691 2019-10-09  Nick Clifton  <nickc@redhat.com>
 692
 693         PR 25041
 694         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 695         instructions.
 696
 697 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 698
 699         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 700         (cmpsd): Likewise. Move EsSeg to other operand.
 701         * opcodes/i386-tbl.h: Re-generate.
 702
 703 2019-09-23  Alan Modra  <amodra@gmail.com>
 704
 705         * m68k-dis.c: Include cpu-m68k.h
 706
 707 2019-09-23  Alan Modra  <amodra@gmail.com>
 708
 709         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 710         "elf/mips.h" earlier.
 711
 712 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 713
 714         PR gas/25012
 715         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 716         with SReg operand.
 717         * i386-tbl.h: Re-generate.
 718
 719 2019-09-18  Alan Modra  <amodra@gmail.com>
 720
 721         * arc-ext.c: Update throughout for bfd section macro changes.
 722
 723 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 724
 725         * Makefile.in: Re-generate.
 726         * configure: Re-generate.
 727
 728 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 729
 730         * riscv-opc.c (riscv_opcodes): Change subset field
 731         to insn_class field for all instructions.
 732         (riscv_insn_types): Likewise.
 733
 734 2019-09-16  Phil Blundell  <pb@pbcl.net>
 735
 736         * configure: Regenerated.
 737
 738 2019-09-10  Miod Vallat  <miod@online.fr>
 739
 740         PR 24982
 741         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 742
 743 2019-09-09  Phil Blundell  <pb@pbcl.net>
 744
 745         binutils 2.33 branch created.
 746
 747 2019-09-03  Nick Clifton  <nickc@redhat.com>
 748
 749         PR 24961
 750         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 751         greater than zero before indexing via (bufcnt -1).
 752
 753 2019-09-03  Nick Clifton  <nickc@redhat.com>
 754
 755         PR 24958
 756         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 757         (MAX_SPEC_REG_NAME_LEN): Define.
 758         (struct mmix_dis_info): Use defined constants for array lengths.
 759         (get_reg_name): New function.
 760         (get_sprec_reg_name): New function.
 761         (print_insn_mmix): Use new functions.
 762
 763 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 764
 765         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 766         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 767         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 768
 769 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 770
 771         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 772         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 773         (aarch64_sys_reg_supported_p): Update checks for the above.
 774
 775 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 776
 777         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 778         cases MVE_SQRSHRL and MVE_UQRSHLL.
 779         (print_insn_mve): Add case for specifier 'k' to check
 780         specific bit of the instruction.
 781
 782 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 783
 784         PR 24854
 785         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 786         encountering an unknown machine type.
 787         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 788         cases return -1 rather than calling abort.
 789
 790 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 791
 792         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 793         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 794         IgnoreSize.
 795         * i386-tbl.h: Re-generate.
 796
 797 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 798
 799         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 800         instructions.
 801
 802 2019-07-30  Mel Chen <mel.chen@sifive.com>
 803
 804         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 805         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 806
 807         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 808         fscsr.
 809
 810 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 811
 812         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 813         and MPY class instructions.
 814         (parse_option): Add nps400 option.
 815         (print_arc_disassembler_options): Add nps400 info.
 816
 817 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 818
 819         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 820         (bspop): Likewise.
 821         (modapp): Likewise.
 822         * arc-opc.c (RAD_CHK): Add.
 823         * arc-tbl.h: Regenerate.
 824
 825 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 826
 827         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 828         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 829
 830 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 831
 832         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 833         instructions as UNPREDICTABLE.
 834
 835 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 836
 837         * bpf-desc.c: Regenerated.
 838
 839 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 840
 841         * i386-gen.c (static_assert): Define.
 842         (main): Use it.
 843         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 844         (Opcode_Modifier_Num): ... this.
 845         (Mem): Delete.
 846
 847 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 848
 849         * i386-gen.c (operand_types): Move RegMem ...
 850         (opcode_modifiers): ... here.
 851         * i386-opc.h (RegMem): Move to opcode modifer enum.
 852         (union i386_operand_type): Move regmem field ...
 853         (struct i386_opcode_modifier): ... here.
 854         * i386-opc.tbl (RegMem): Define.
 855         (mov, movq): Move RegMem on segment, control, debug, and test
 856         register flavors.
 857         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 858         to non-SSE2AVX flavor.
 859         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 860         Move RegMem on register only flavors. Drop IgnoreSize from
 861         legacy encoding flavors.
 862         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 863         flavors.
 864         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 865         register only flavors.
 866         (vmovd): Move RegMem and drop IgnoreSize on register only
 867         flavor. Change opcode and operand order to store form.
 868         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 869
 870 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 871
 872         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 873         entries.
 874         * i386-opc.h (SReg2, SReg3): Replace by ...
 875         (SReg): ... this.
 876         (union i386_operand_type): Replace sreg fields.
 877         * i386-opc.tbl (mov, ): Use SReg.
 878         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 879         register flavors.
 880         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 881         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 882
 883 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 884
 885         * bpf-desc.c: Regenerate.
 886         * bpf-opc.c: Likewise.
 887         * bpf-opc.h: Likewise.
 888
 889 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 890
 891         * bpf-desc.c: Regenerate.
 892         * bpf-opc.c: Likewise.
 893
 894 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 895
 896         * arm-dis.c (print_insn_coprocessor): Rename index to
 897         index_operand.
 898
 899 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 900
 901         * riscv-opc.c (riscv_insn_types): Add r4 type.
 902
 903         * riscv-opc.c (riscv_insn_types): Add b and j type.
 904
 905         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 906         format for sb type and correct s type.
 907
 908 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 909
 910         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 911         SVE FMOV alias of FCPY.
 912
 913 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 914
 915         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 916         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 917
 918 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 919
 920         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 921         registers in an instruction prefixed by MOVPRFX.
 922
 923 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 924
 925         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 926         sve_size_13 icode to account for variant behaviour of
 927         pmull{t,b}.
 928         * aarch64-dis-2.c: Regenerate.
 929         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 930         sve_size_13 icode to account for variant behaviour of
 931         pmull{t,b}.
 932         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 933         (OP_SVE_VVV_Q_D): Add new qualifier.
 934         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 935         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 936         AES and those not.
 937
 938 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 939
 940         * opcodes/i386-gen.c (operand_type_init): Remove
 941         OPERAND_TYPE_VEC_IMM4 entry.
 942         (operand_types): Remove Vec_Imm4.
 943         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 944         (union i386_operand_type): Remove vec_imm4.
 945         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 946         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 947
 948 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 949
 950         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 951         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 952         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 953         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 954         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 955         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 956         * i386-tbl.h: Re-generate.
 957
 958 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 959
 960         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 961         register operands.
 962         * i386-tbl.h: Re-generate.
 963
 964 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 965
 966         * i386-opc.tbl (C): New.
 967         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 968         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 969         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 970         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 971         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 972         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 973         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 974         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 975         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 976         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 977         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 978         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 979         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 980         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 981         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 982         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 983         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 984         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 985         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 986         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 987         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 988         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 989         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 990         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 991         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 992         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 993         flavors.
 994         * i386-tbl.h: Re-generate.
 995
 996 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 997
 998         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 999         register operands.
1000         * i386-tbl.h: Re-generate.
1001
1002 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1003
1004         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1005         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1006         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1007         * i386-tbl.h: Re-generate.
1008
1009 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1010
1011         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1012         Disp8MemShift from register only templates.
1013         * i386-tbl.h: Re-generate.
1014
1015 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1016
1017         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1018         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1019         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1020         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1021         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1022         EVEX_W_0F11_P_3_M_1): Delete.
1023         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1024         EVEX_W_0F11_P_3): New.
1025         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1026         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1027         MOD_EVEX_0F11_PREFIX_3 table entries.
1028         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1029         PREFIX_EVEX_0F11 table entries.
1030         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1031         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1032         EVEX_W_0F11_P_3_M_{0,1} table entries.
1033
1034 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1035
1036         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1037         Delete.
1038
1039 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1040
1041         PR binutils/24719
1042         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1043         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1044         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1045         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1046         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1047         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1048         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1049         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1050         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1051         PREFIX_EVEX_0F38C6_REG_6 entries.
1052         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1053         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1054         EVEX_W_0F38C7_R_6_P_2 entries.
1055         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1056         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1057         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1058         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1059         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1060         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1061         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1062
1063 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1064
1065         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1066         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1067         VEX_LEN_0F2D_P_3): Delete.
1068         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1069         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1070         (prefix_table): ... here.
1071
1072 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1073
1074         * i386-dis.c (Iq): Delete.
1075         (Id): New.
1076         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1077         TBM insns.
1078         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1079         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1080         (OP_E_memory): Also honor needindex when deciding whether an
1081         address size prefix needs printing.
1082         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1083
1084 2019-06-26  Jim Wilson  <jimw@sifive.com>
1085
1086         PR binutils/24739
1087         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1088         Set info->display_endian to info->endian_code.
1089
1090 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1091
1092         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1093         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1094         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1095         OPERAND_TYPE_ACC64 entries.
1096         * i386-init.h: Re-generate.
1097
1098 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1099
1100         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1101         Delete.
1102         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1103         of dqa_mode.
1104         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1105         entries here.
1106         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1107         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1108
1109 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1110
1111         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1112         variables.
1113
1114 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1115
1116         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1117         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1118         movnti.
1119         * i386-opc.tbl (movnti): Add IgnoreSize.
1120         * i386-tbl.h: Re-generate.
1121
1122 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1123
1124         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1125         * i386-tbl.h: Re-generate.
1126
1127 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1128
1129         * i386-dis-evex.h: Break into ...
1130         * i386-dis-evex-len.h: New file.
1131         * i386-dis-evex-mod.h: Likewise.
1132         * i386-dis-evex-prefix.h: Likewise.
1133         * i386-dis-evex-reg.h: Likewise.
1134         * i386-dis-evex-w.h: Likewise.
1135         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1136         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1137         i386-dis-evex-mod.h.
1138
1139 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1140
1141         PR binutils/24700
1142         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1143         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1144         EVEX_W_0F385B_P_2.
1145         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1146         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1147         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1148         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1149         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1150         EVEX_LEN_0F385B_P_2_W_1.
1151         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1152         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1153         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1154         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1155         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1156         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1157         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1158         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1159         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1160         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1161
1162 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1163
1164         PR binutils/24691
1165         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1166         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1167         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1168         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1169         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1170         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1171         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1172         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1173         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1174         EVEX_LEN_0F3A43_P_2_W_1.
1175         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1176         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1177         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1178         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1179         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1180         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1181         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1182         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1183         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1184         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1185         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1186         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1187
1188 2019-06-14  Nick Clifton  <nickc@redhat.com>
1189
1190         * po/fr.po; Updated French translation.
1191
1192 2019-06-13  Stafford Horne  <shorne@gmail.com>
1193
1194         * or1k-asm.c: Regenerated.
1195         * or1k-desc.c: Regenerated.
1196         * or1k-desc.h: Regenerated.
1197         * or1k-dis.c: Regenerated.
1198         * or1k-ibld.c: Regenerated.
1199         * or1k-opc.c: Regenerated.
1200         * or1k-opc.h: Regenerated.
1201         * or1k-opinst.c: Regenerated.
1202
1203 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1204
1205         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1206
1207 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1208
1209         PR binutils/24633
1210         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1211         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1212         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1213         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1214         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1215         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1216         EVEX_LEN_0F3A1B_P_2_W_1.
1217         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1218         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1219         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1220         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1221         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1222         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1223         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1224         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1225
1226 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1227
1228         PR binutils/24626
1229         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1230         EVEX.vvvv when disassembling VEX and EVEX instructions.
1231         (OP_VEX): Set vex.register_specifier to 0 after readding
1232         vex.register_specifier.
1233         (OP_Vex_2src_1): Likewise.
1234         (OP_Vex_2src_2): Likewise.
1235         (OP_LWP_E): Likewise.
1236         (OP_EX_Vex): Don't check vex.register_specifier.
1237         (OP_XMM_Vex): Likewise.
1238
1239 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1240             Lili Cui  <lili.cui@intel.com>
1241
1242         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1243         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1244         instructions.
1245         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1246         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1247         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1248         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1249         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1250         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1251         * i386-init.h: Regenerated.
1252         * i386-tbl.h: Likewise.
1253
1254 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1255             Lili Cui  <lili.cui@intel.com>
1256
1257         * doc/c-i386.texi: Document enqcmd.
1258         * testsuite/gas/i386/enqcmd-intel.d: New file.
1259         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1260         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1261         * testsuite/gas/i386/enqcmd.d: Likewise.
1262         * testsuite/gas/i386/enqcmd.s: Likewise.
1263         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1264         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1265         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1266         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1267         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1268         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1269         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1270         and x86-64-enqcmd.
1271
1272 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1273
1274         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1275
1276 2019-06-03  Alan Modra  <amodra@gmail.com>
1277
1278         * ppc-dis.c (prefix_opcd_indices): Correct size.
1279
1280 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1281
1282         PR gas/24625
1283         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1284         Disp8ShiftVL.
1285         * i386-tbl.h: Regenerated.
1286
1287 2019-05-24  Alan Modra  <amodra@gmail.com>
1288
1289         * po/POTFILES.in: Regenerate.
1290
1291 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1292             Alan Modra  <amodra@gmail.com>
1293
1294         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1295         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1296         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1297         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1298         XTOP>): Define and add entries.
1299         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1300         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1301         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1302         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1303
1304 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1305             Alan Modra  <amodra@gmail.com>
1306
1307         * ppc-dis.c (ppc_opts): Add "future" entry.
1308         (PREFIX_OPCD_SEGS): Define.
1309         (prefix_opcd_indices): New array.
1310         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1311         (lookup_prefix): New function.
1312         (print_insn_powerpc): Handle 64-bit prefix instructions.
1313         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1314         (PMRR, POWERXX): Define.
1315         (prefix_opcodes): New instruction table.
1316         (prefix_num_opcodes): New constant.
1317
1318 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1319
1320         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1321         * configure: Regenerated.
1322         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1323         and cpu/bpf.opc.
1324         (HFILES): Add bpf-desc.h and bpf-opc.h.
1325         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1326         bpf-ibld.c and bpf-opc.c.
1327         (BPF_DEPS): Define.
1328         * Makefile.in: Regenerated.
1329         * disassemble.c (ARCH_bpf): Define.
1330         (disassembler): Add case for bfd_arch_bpf.
1331         (disassemble_init_for_target): Likewise.
1332         (enum epbf_isa_attr): Define.
1333         * disassemble.h: extern print_insn_bpf.
1334         * bpf-asm.c: Generated.
1335         * bpf-opc.h: Likewise.
1336         * bpf-opc.c: Likewise.
1337         * bpf-ibld.c: Likewise.
1338         * bpf-dis.c: Likewise.
1339         * bpf-desc.h: Likewise.
1340         * bpf-desc.c: Likewise.
1341
1342 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1343
1344         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1345         and VMSR with the new operands.
1346
1347 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1348
1349         * arm-dis.c (enum mve_instructions): New enum
1350         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1351         and cneg.
1352         (mve_opcodes): New instructions as above.
1353         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1354         csneg and csel.
1355         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1356
1357 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1358
1359         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1360         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1361         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1362         uqshl, urshrl and urshr.
1363         (is_mve_okay_in_it): Add new instructions to TRUE list.
1364         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1365         (print_insn_mve): Updated to accept new %j,
1366         %<bitfield>m and %<bitfield>n patterns.
1367
1368 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1369
1370         * mips-opc.c (mips_builtin_opcodes): Change source register
1371         constraint for DAUI.
1372
1373 2019-05-20  Nick Clifton  <nickc@redhat.com>
1374
1375         * po/fr.po: Updated French translation.
1376
1377 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1378             Michael Collison <michael.collison@arm.com>
1379
1380         * arm-dis.c (thumb32_opcodes): Add new instructions.
1381         (enum mve_instructions): Likewise.
1382         (enum mve_undefined): Add new reasons.
1383         (is_mve_encoding_conflict): Handle new instructions.
1384         (is_mve_undefined): Likewise.
1385         (is_mve_unpredictable): Likewise.
1386         (print_mve_undefined): Likewise.
1387         (print_mve_size): Likewise.
1388
1389 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1390             Michael Collison <michael.collison@arm.com>
1391
1392         * arm-dis.c (thumb32_opcodes): Add new instructions.
1393         (enum mve_instructions): Likewise.
1394         (is_mve_encoding_conflict): Handle new instructions.
1395         (is_mve_undefined): Likewise.
1396         (is_mve_unpredictable): Likewise.
1397         (print_mve_size): Likewise.
1398
1399 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1400             Michael Collison <michael.collison@arm.com>
1401
1402         * arm-dis.c (thumb32_opcodes): Add new instructions.
1403         (enum mve_instructions): Likewise.
1404         (is_mve_encoding_conflict): Likewise.
1405         (is_mve_unpredictable): Likewise.
1406         (print_mve_size): Likewise.
1407
1408 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1409             Michael Collison <michael.collison@arm.com>
1410
1411         * arm-dis.c (thumb32_opcodes): Add new instructions.
1412         (enum mve_instructions): Likewise.
1413         (is_mve_encoding_conflict): Handle new instructions.
1414         (is_mve_undefined): Likewise.
1415         (is_mve_unpredictable): Likewise.
1416         (print_mve_size): Likewise.
1417
1418 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1419             Michael Collison <michael.collison@arm.com>
1420
1421         * arm-dis.c (thumb32_opcodes): Add new instructions.
1422         (enum mve_instructions): Likewise.
1423         (is_mve_encoding_conflict): Handle new instructions.
1424         (is_mve_undefined): Likewise.
1425         (is_mve_unpredictable): Likewise.
1426         (print_mve_size): Likewise.
1427         (print_insn_mve): Likewise.
1428
1429 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1430             Michael Collison <michael.collison@arm.com>
1431
1432         * arm-dis.c (thumb32_opcodes): Add new instructions.
1433         (print_insn_thumb32): Handle new instructions.
1434
1435 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1436             Michael Collison <michael.collison@arm.com>
1437
1438         * arm-dis.c (enum mve_instructions): Add new instructions.
1439         (enum mve_undefined): Add new reasons.
1440         (is_mve_encoding_conflict): Handle new instructions.
1441         (is_mve_undefined): Likewise.
1442         (is_mve_unpredictable): Likewise.
1443         (print_mve_undefined): Likewise.
1444         (print_mve_size): Likewise.
1445         (print_mve_shift_n): Likewise.
1446         (print_insn_mve): Likewise.
1447
1448 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1449             Michael Collison <michael.collison@arm.com>
1450
1451         * arm-dis.c (enum mve_instructions): Add new instructions.
1452         (is_mve_encoding_conflict): Handle new instructions.
1453         (is_mve_unpredictable): Likewise.
1454         (print_mve_rotate): Likewise.
1455         (print_mve_size): Likewise.
1456         (print_insn_mve): Likewise.
1457
1458 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1459             Michael Collison <michael.collison@arm.com>
1460
1461         * arm-dis.c (enum mve_instructions): Add new instructions.
1462         (is_mve_encoding_conflict): Handle new instructions.
1463         (is_mve_unpredictable): Likewise.
1464         (print_mve_size): Likewise.
1465         (print_insn_mve): Likewise.
1466
1467 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1468             Michael Collison <michael.collison@arm.com>
1469
1470         * arm-dis.c (enum mve_instructions): Add new instructions.
1471         (enum mve_undefined): Add new reasons.
1472         (is_mve_encoding_conflict): Handle new instructions.
1473         (is_mve_undefined): Likewise.
1474         (is_mve_unpredictable): Likewise.
1475         (print_mve_undefined): Likewise.
1476         (print_mve_size): Likewise.
1477         (print_insn_mve): Likewise.
1478
1479 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1480             Michael Collison <michael.collison@arm.com>
1481
1482         * arm-dis.c (enum mve_instructions): Add new instructions.
1483         (is_mve_encoding_conflict): Handle new instructions.
1484         (is_mve_undefined): Likewise.
1485         (is_mve_unpredictable): Likewise.
1486         (print_mve_size): Likewise.
1487         (print_insn_mve): Likewise.
1488
1489 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1490             Michael Collison <michael.collison@arm.com>
1491
1492         * arm-dis.c (enum mve_instructions): Add new instructions.
1493         (enum mve_unpredictable): Add new reasons.
1494         (enum mve_undefined): Likewise.
1495         (is_mve_okay_in_it): Handle new isntructions.
1496         (is_mve_encoding_conflict): Likewise.
1497         (is_mve_undefined): Likewise.
1498         (is_mve_unpredictable): Likewise.
1499         (print_mve_vmov_index): Likewise.
1500         (print_simd_imm8): Likewise.
1501         (print_mve_undefined): Likewise.
1502         (print_mve_unpredictable): Likewise.
1503         (print_mve_size): Likewise.
1504         (print_insn_mve): Likewise.
1505
1506 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1507             Michael Collison <michael.collison@arm.com>
1508
1509         * arm-dis.c (enum mve_instructions): Add new instructions.
1510         (enum mve_unpredictable): Add new reasons.
1511         (enum mve_undefined): Likewise.
1512         (is_mve_encoding_conflict): Handle new instructions.
1513         (is_mve_undefined): Likewise.
1514         (is_mve_unpredictable): Likewise.
1515         (print_mve_undefined): Likewise.
1516         (print_mve_unpredictable): Likewise.
1517         (print_mve_rounding_mode): Likewise.
1518         (print_mve_vcvt_size): Likewise.
1519         (print_mve_size): Likewise.
1520         (print_insn_mve): Likewise.
1521
1522 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1523             Michael Collison <michael.collison@arm.com>
1524
1525         * arm-dis.c (enum mve_instructions): Add new instructions.
1526         (enum mve_unpredictable): Add new reasons.
1527         (enum mve_undefined): Likewise.
1528         (is_mve_undefined): Handle new instructions.
1529         (is_mve_unpredictable): Likewise.
1530         (print_mve_undefined): Likewise.
1531         (print_mve_unpredictable): Likewise.
1532         (print_mve_size): Likewise.
1533         (print_insn_mve): Likewise.
1534
1535 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1536             Michael Collison <michael.collison@arm.com>
1537
1538         * arm-dis.c (enum mve_instructions): Add new instructions.
1539         (enum mve_undefined): Add new reasons.
1540         (insns): Add new instructions.
1541         (is_mve_encoding_conflict):
1542         (print_mve_vld_str_addr): New print function.
1543         (is_mve_undefined): Handle new instructions.
1544         (is_mve_unpredictable): Likewise.
1545         (print_mve_undefined): Likewise.
1546         (print_mve_size): Likewise.
1547         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1548         (print_insn_mve):  Handle new operands.
1549
1550 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1551             Michael Collison <michael.collison@arm.com>
1552
1553         * arm-dis.c (enum mve_instructions): Add new instructions.
1554         (enum mve_unpredictable): Add new reasons.
1555         (is_mve_encoding_conflict): Handle new instructions.
1556         (is_mve_unpredictable): Likewise.
1557         (mve_opcodes): Add new instructions.
1558         (print_mve_unpredictable): Handle new reasons.
1559         (print_mve_register_blocks): New print function.
1560         (print_mve_size): Handle new instructions.
1561         (print_insn_mve): Likewise.
1562
1563 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1564             Michael Collison <michael.collison@arm.com>
1565
1566         * arm-dis.c (enum mve_instructions): Add new instructions.
1567         (enum mve_unpredictable): Add new reasons.
1568         (enum mve_undefined): Likewise.
1569         (is_mve_encoding_conflict): Handle new instructions.
1570         (is_mve_undefined): Likewise.
1571         (is_mve_unpredictable): Likewise.
1572         (coprocessor_opcodes): Move NEON VDUP from here...
1573         (neon_opcodes): ... to here.
1574         (mve_opcodes): Add new instructions.
1575         (print_mve_undefined):  Handle new reasons.
1576         (print_mve_unpredictable): Likewise.
1577         (print_mve_size): Handle new instructions.
1578         (print_insn_neon): Handle vdup.
1579         (print_insn_mve): Handle new operands.
1580
1581 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1582             Michael Collison <michael.collison@arm.com>
1583
1584         * arm-dis.c (enum mve_instructions): Add new instructions.
1585         (enum mve_unpredictable): Add new values.
1586         (mve_opcodes): Add new instructions.
1587         (vec_condnames): New array with vector conditions.
1588         (mve_predicatenames): New array with predicate suffixes.
1589         (mve_vec_sizename): New array with vector sizes.
1590         (enum vpt_pred_state): New enum with vector predication states.
1591         (struct vpt_block): New struct type for vpt blocks.
1592         (vpt_block_state): Global struct to keep track of state.
1593         (mve_extract_pred_mask): New helper function.
1594         (num_instructions_vpt_block): Likewise.
1595         (mark_outside_vpt_block): Likewise.
1596         (mark_inside_vpt_block): Likewise.
1597         (invert_next_predicate_state): Likewise.
1598         (update_next_predicate_state): Likewise.
1599         (update_vpt_block_state): Likewise.
1600         (is_vpt_instruction): Likewise.
1601         (is_mve_encoding_conflict): Add entries for new instructions.
1602         (is_mve_unpredictable): Likewise.
1603         (print_mve_unpredictable): Handle new cases.
1604         (print_instruction_predicate): Likewise.
1605         (print_mve_size): New function.
1606         (print_vec_condition): New function.
1607         (print_insn_mve): Handle vpt blocks and new print operands.
1608
1609 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1610
1611         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1612         8, 14 and 15 for Armv8.1-M Mainline.
1613
1614 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1615             Michael Collison <michael.collison@arm.com>
1616
1617         * arm-dis.c (enum mve_instructions): New enum.
1618         (enum mve_unpredictable): Likewise.
1619         (enum mve_undefined): Likewise.
1620         (struct mopcode32): New struct.
1621         (is_mve_okay_in_it): New function.
1622         (is_mve_architecture): Likewise.
1623         (arm_decode_field): Likewise.
1624         (arm_decode_field_multiple): Likewise.
1625         (is_mve_encoding_conflict): Likewise.
1626         (is_mve_undefined): Likewise.
1627         (is_mve_unpredictable): Likewise.
1628         (print_mve_undefined): Likewise.
1629         (print_mve_unpredictable): Likewise.
1630         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1631         (print_insn_mve): New function.
1632         (print_insn_thumb32): Handle MVE architecture.
1633         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1634
1635 2019-05-10  Nick Clifton  <nickc@redhat.com>
1636
1637         PR 24538
1638         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1639         end of the table prematurely.
1640
1641 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1642
1643         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1644         macros for R6.
1645
1646 2019-05-11  Alan Modra  <amodra@gmail.com>
1647
1648         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1649         when -Mraw is in effect.
1650
1651 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1652
1653         * aarch64-dis-2.c: Regenerate.
1654         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1655         (OP_SVE_BBB): New variant set.
1656         (OP_SVE_DDDD): New variant set.
1657         (OP_SVE_HHH): New variant set.
1658         (OP_SVE_HHHU): New variant set.
1659         (OP_SVE_SSS): New variant set.
1660         (OP_SVE_SSSU): New variant set.
1661         (OP_SVE_SHH): New variant set.
1662         (OP_SVE_SBBU): New variant set.
1663         (OP_SVE_DSS): New variant set.
1664         (OP_SVE_DHHU): New variant set.
1665         (OP_SVE_VMV_HSD_BHS): New variant set.
1666         (OP_SVE_VVU_HSD_BHS): New variant set.
1667         (OP_SVE_VVVU_SD_BH): New variant set.
1668         (OP_SVE_VVVU_BHSD): New variant set.
1669         (OP_SVE_VVV_QHD_DBS): New variant set.
1670         (OP_SVE_VVV_HSD_BHS): New variant set.
1671         (OP_SVE_VVV_HSD_BHS2): New variant set.
1672         (OP_SVE_VVV_BHS_HSD): New variant set.
1673         (OP_SVE_VV_BHS_HSD): New variant set.
1674         (OP_SVE_VVV_SD): New variant set.
1675         (OP_SVE_VVU_BHS_HSD): New variant set.
1676         (OP_SVE_VZVV_SD): New variant set.
1677         (OP_SVE_VZVV_BH): New variant set.
1678         (OP_SVE_VZV_SD): New variant set.
1679         (aarch64_opcode_table): Add sve2 instructions.
1680
1681 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1682
1683         * aarch64-asm-2.c: Regenerated.
1684         * aarch64-dis-2.c: Regenerated.
1685         * aarch64-opc-2.c: Regenerated.
1686         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1687         for SVE_SHLIMM_UNPRED_22.
1688         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1689         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1690         operand.
1691
1692 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1693
1694         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1695         sve_size_tsz_bhs iclass encode.
1696         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1697         sve_size_tsz_bhs iclass decode.
1698
1699 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1700
1701         * aarch64-asm-2.c: Regenerated.
1702         * aarch64-dis-2.c: Regenerated.
1703         * aarch64-opc-2.c: Regenerated.
1704         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1705         for SVE_Zm4_11_INDEX.
1706         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1707         (fields): Handle SVE_i2h field.
1708         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1709         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1710
1711 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1712
1713         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1714         sve_shift_tsz_bhsd iclass encode.
1715         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1716         sve_shift_tsz_bhsd iclass decode.
1717
1718 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1719
1720         * aarch64-asm-2.c: Regenerated.
1721         * aarch64-dis-2.c: Regenerated.
1722         * aarch64-opc-2.c: Regenerated.
1723         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1724         (aarch64_encode_variant_using_iclass): Handle
1725         sve_shift_tsz_hsd iclass encode.
1726         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1727         sve_shift_tsz_hsd iclass decode.
1728         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1729         for SVE_SHRIMM_UNPRED_22.
1730         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1731         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1732         operand.
1733
1734 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1735
1736         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1737         sve_size_013 iclass encode.
1738         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1739         sve_size_013 iclass decode.
1740
1741 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1742
1743         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1744         sve_size_bh iclass encode.
1745         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1746         sve_size_bh iclass decode.
1747
1748 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1749
1750         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1751         sve_size_sd2 iclass encode.
1752         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1753         sve_size_sd2 iclass decode.
1754         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1755         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1756
1757 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1758
1759         * aarch64-asm-2.c: Regenerated.
1760         * aarch64-dis-2.c: Regenerated.
1761         * aarch64-opc-2.c: Regenerated.
1762         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1763         for SVE_ADDR_ZX.
1764         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1765         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1766
1767 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1768
1769         * aarch64-asm-2.c: Regenerated.
1770         * aarch64-dis-2.c: Regenerated.
1771         * aarch64-opc-2.c: Regenerated.
1772         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1773         for SVE_Zm3_11_INDEX.
1774         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1775         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1776         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1777         fields.
1778         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1779
1780 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1781
1782         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1783         sve_size_hsd2 iclass encode.
1784         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1785         sve_size_hsd2 iclass decode.
1786         * aarch64-opc.c (fields): Handle SVE_size field.
1787         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1788
1789 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1790
1791         * aarch64-asm-2.c: Regenerated.
1792         * aarch64-dis-2.c: Regenerated.
1793         * aarch64-opc-2.c: Regenerated.
1794         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1795         for SVE_IMM_ROT3.
1796         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1797         (fields): Handle SVE_rot3 field.
1798         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1799         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1800
1801 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1802
1803         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1804         instructions.
1805
1806 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1807
1808         * aarch64-tbl.h
1809         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1810         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1811         aarch64_feature_sve2bitperm): New feature sets.
1812         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1813         for feature set addresses.
1814         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1815         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1816
1817 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1818             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1819
1820         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1821         argument and set ASE_EVA_R6 appropriately.
1822         (set_default_mips_dis_options): Pass ISA to above.
1823         (parse_mips_dis_option): Likewise.
1824         * mips-opc.c (EVAR6): New macro.
1825         (mips_builtin_opcodes): Add llwpe, scwpe.
1826
1827 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1828
1829         * aarch64-asm-2.c: Regenerated.
1830         * aarch64-dis-2.c: Regenerated.
1831         * aarch64-opc-2.c: Regenerated.
1832         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1833         AARCH64_OPND_TME_UIMM16.
1834         (aarch64_print_operand): Likewise.
1835         * aarch64-tbl.h (QL_IMM_NIL): New.
1836         (TME): New.
1837         (_TME_INSN): New.
1838         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1839
1840 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1841
1842         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1843
1844 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1845             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1846
1847         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1848
1849 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1850
1851         * s12z-opc.h: Add extern "C" bracketing to help
1852         users who wish to use this interface in c++ code.
1853
1854 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1855
1856         * s12z-opc.c (bm_decode): Handle bit map operations with the
1857         "reserved0" mode.
1858
1859 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1860
1861         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1862         specifier.  Add entries for VLDR and VSTR of system registers.
1863         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1864         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1865         of %J and %K format specifier.
1866
1867 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1868
1869         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1870         Add new entries for VSCCLRM instruction.
1871         (print_insn_coprocessor): Handle new %C format control code.
1872
1873 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1874
1875         * arm-dis.c (enum isa): New enum.
1876         (struct sopcode32): New structure.
1877         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1878         set isa field of all current entries to ANY.
1879         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1880         Only match an entry if its isa field allows the current mode.
1881
1882 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1883
1884         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1885         CLRM.
1886         (print_insn_thumb32): Add logic to print %n CLRM register list.
1887
1888 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1889
1890         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1891         and %Q patterns.
1892
1893 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1894
1895         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1896         (print_insn_thumb32): Edit the switch case for %Z.
1897
1898 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1899
1900         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1901
1902 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1903
1904         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1905
1906 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1907
1908         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1909
1910 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1911
1912         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1913         Arm register with r13 and r15 unpredictable.
1914         (thumb32_opcodes): New instructions for bfx and bflx.
1915
1916 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1917
1918         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1919
1920 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1921
1922         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1923
1924 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1925
1926         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1927
1928 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1929
1930         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1931
1932 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1933
1934         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1935         "optr". ("operator" is a reserved word in c++).
1936
1937 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1938
1939         * aarch64-opc.c (aarch64_print_operand): Add case for
1940         AARCH64_OPND_Rt_SP.
1941         (verify_constraints): Likewise.
1942         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1943         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1944         to accept Rt|SP as first operand.
1945         (AARCH64_OPERANDS): Add new Rt_SP.
1946         * aarch64-asm-2.c: Regenerated.
1947         * aarch64-dis-2.c: Regenerated.
1948         * aarch64-opc-2.c: Regenerated.
1949
1950 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1951
1952         * aarch64-asm-2.c: Regenerated.
1953         * aarch64-dis-2.c: Likewise.
1954         * aarch64-opc-2.c: Likewise.
1955         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1956
1957 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1958
1959         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1960
1961 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1962
1963         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1964         * i386-init.h: Regenerated.
1965
1966 2019-04-07  Alan Modra  <amodra@gmail.com>
1967
1968         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1969         op_separator to control printing of spaces, comma and parens
1970         rather than need_comma, need_paren and spaces vars.
1971
1972 2019-04-07  Alan Modra  <amodra@gmail.com>
1973
1974         PR 24421
1975         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1976         (print_insn_neon, print_insn_arm): Likewise.
1977
1978 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1979
1980         * i386-dis-evex.h (evex_table): Updated to support BF16
1981         instructions.
1982         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1983         and EVEX_W_0F3872_P_3.
1984         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1985         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1986         * i386-opc.h (enum): Add CpuAVX512_BF16.
1987         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1988         * i386-opc.tbl: Add AVX512 BF16 instructions.
1989         * i386-init.h: Regenerated.
1990         * i386-tbl.h: Likewise.
1991
1992 2019-04-05  Alan Modra  <amodra@gmail.com>
1993
1994         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1995         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1996         to favour printing of "-" branch hint when using the "y" bit.
1997         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1998
1999 2019-04-05  Alan Modra  <amodra@gmail.com>
2000
2001         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2002         opcode until first operand is output.
2003
2004 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2005
2006         PR gas/24349
2007         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2008         (valid_bo_post_v2): Add support for 'at' branch hints.
2009         (insert_bo): Only error on branch on ctr.
2010         (get_bo_hint_mask): New function.
2011         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2012         for inserting 'at' branch hints.
2013         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2014         for extracting 'at' branch hints.
2015         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2016         (BOE): Delete operand.
2017         (BOM, BOP): New operands.
2018         (RM): Update value.
2019         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2020         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2021         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2022         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2023         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2024         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2025         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2026         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2027         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2028         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2029         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2030         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2031         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2032         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2033         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2034         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2035         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2036         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2037         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2038         bttarl+>: New extended mnemonics.
2039
2040 2019-03-28  Alan Modra  <amodra@gmail.com>
2041
2042         PR 24390
2043         * ppc-opc.c (BTF): Define.
2044         (powerpc_opcodes): Use for mtfsb*.
2045         * ppc-dis.c (print_insn_powerpc): Print fields with both
2046         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2047
2048 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2049
2050         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2051         (mapping_symbol_for_insn): Implement new algorithm.
2052         (print_insn): Remove duplicate code.
2053
2054 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2055
2056         * aarch64-dis.c (print_insn_aarch64):
2057         Implement override.
2058
2059 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2060
2061         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2062         order.
2063
2064 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2065
2066         * aarch64-dis.c (last_stop_offset): New.
2067         (print_insn_aarch64): Use stop_offset.
2068
2069 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2070
2071         PR gas/24359
2072         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2073         CPU_ANY_AVX2_FLAGS.
2074         * i386-init.h: Regenerated.
2075
2076 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2077
2078         PR gas/24348
2079         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2080         vmovdqu16, vmovdqu32 and vmovdqu64.
2081         * i386-tbl.h: Regenerated.
2082
2083 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2084
2085         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2086         from vstrszb, vstrszh, and vstrszf.
2087
2088 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2089
2090         * s390-opc.txt: Add instruction descriptions.
2091
2092 2019-02-08  Jim Wilson  <jimw@sifive.com>
2093
2094         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2095         <bne>: Likewise.
2096
2097 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2098
2099         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2100
2101 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2102
2103         PR binutils/23212
2104         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2105         * aarch64-opc.c (verify_elem_sd): New.
2106         (fields): Add FLD_sz entr.
2107         * aarch64-tbl.h (_SIMD_INSN): New.
2108         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2109         fmulx scalar and vector by element isns.
2110
2111 2019-02-07  Nick Clifton  <nickc@redhat.com>
2112
2113         * po/sv.po: Updated Swedish translation.
2114
2115 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2116
2117         * s390-mkopc.c (main): Accept arch13 as cpu string.
2118         * s390-opc.c: Add new instruction formats and instruction opcode
2119         masks.
2120         * s390-opc.txt: Add new arch13 instructions.
2121
2122 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2123
2124         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2125         (aarch64_opcode): Change encoding for stg, stzg
2126         st2g and st2zg.
2127         * aarch64-asm-2.c: Regenerated.
2128         * aarch64-dis-2.c: Regenerated.
2129         * aarch64-opc-2.c: Regenerated.
2130
2131 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2132
2133         * aarch64-asm-2.c: Regenerated.
2134         * aarch64-dis-2.c: Likewise.
2135         * aarch64-opc-2.c: Likewise.
2136         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2137
2138 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2139             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2140
2141         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2142         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2143         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2144         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2145         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2146         case for ldstgv_indexed.
2147         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2148         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2149         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2150         * aarch64-asm-2.c: Regenerated.
2151         * aarch64-dis-2.c: Regenerated.
2152         * aarch64-opc-2.c: Regenerated.
2153
2154 2019-01-23  Nick Clifton  <nickc@redhat.com>
2155
2156         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2157
2158 2019-01-21  Nick Clifton  <nickc@redhat.com>
2159
2160         * po/de.po: Updated German translation.
2161         * po/uk.po: Updated Ukranian translation.
2162
2163 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2164         * mips-dis.c (mips_arch_choices): Fix typo in
2165         gs464, gs464e and gs264e descriptors.
2166
2167 2019-01-19  Nick Clifton  <nickc@redhat.com>
2168
2169         * configure: Regenerate.
2170         * po/opcodes.pot: Regenerate.
2171
2172 2018-06-24  Nick Clifton  <nickc@redhat.com>
2173
2174         2.32 branch created.
2175
2176 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2177
2178         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2179         if it is null.
2180         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2181         zero.
2182
2183 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2184
2185         * configure: Regenerate.
2186
2187 2019-01-07  Alan Modra  <amodra@gmail.com>
2188
2189         * configure: Regenerate.
2190         * po/POTFILES.in: Regenerate.
2191
2192 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2193
2194         * s12z-opc.c: New file.
2195         * s12z-opc.h: New file.
2196         * s12z-dis.c: Removed all code not directly related to display
2197         of instructions.  Used the interface provided by the new files
2198         instead.
2199         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2200         * Makefile.in: Regenerate.
2201         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2202         * configure: Regenerate.
2203
2204 2019-01-01  Alan Modra  <amodra@gmail.com>
2205
2206         Update year range in copyright notice of all files.
2207
2208 For older changes see ChangeLog-2018
2209 \f
2210 Copyright (C) 2019 Free Software Foundation, Inc.
2211
2212 Copying and distribution of this file, with or without modification,
2213 are permitted in any medium without royalty provided the copyright
2214 notice and this notice are preserved.
2215
2216 Local Variables:
2217 mode: change-log
2218 left-margin: 8
2219 fill-column: 74
2220 version-control: never
2221 End: