opcodes/ChangeLog

   1 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * arm-dis.c (enum mve_instructions): New enum
   4         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
   5         and cneg.
   6         (mve_opcodes): New instructions as above.
   7         (is_mve_encoding_conflict): Add cases for csinc, csinv,
   8         csneg and csel.
   9         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
  10
  11 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  12
  13         * arm-dis.c (emun mve_instructions): Updated for new instructions.
  14         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
  15         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
  16         uqshl, urshrl and urshr.
  17         (is_mve_okay_in_it): Add new instructions to TRUE list.
  18         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
  19         (print_insn_mve): Updated to accept new %j,
  20         %<bitfield>m and %<bitfield>n patterns.
  21
  22 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
  23
  24         * mips-opc.c (mips_builtin_opcodes): Change source register
  25         constraint for DAUI.
  26
  27 2019-05-20  Nick Clifton  <nickc@redhat.com>
  28
  29         * po/fr.po: Updated French translation.
  30
  31 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  32             Michael Collison <michael.collison@arm.com>
  33
  34         * arm-dis.c (thumb32_opcodes): Add new instructions.
  35         (enum mve_instructions): Likewise.
  36         (enum mve_undefined): Add new reasons.
  37         (is_mve_encoding_conflict): Handle new instructions.
  38         (is_mve_undefined): Likewise.
  39         (is_mve_unpredictable): Likewise.
  40         (print_mve_undefined): Likewise.
  41         (print_mve_size): Likewise.
  42
  43 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  44             Michael Collison <michael.collison@arm.com>
  45
  46         * arm-dis.c (thumb32_opcodes): Add new instructions.
  47         (enum mve_instructions): Likewise.
  48         (is_mve_encoding_conflict): Handle new instructions.
  49         (is_mve_undefined): Likewise.
  50         (is_mve_unpredictable): Likewise.
  51         (print_mve_size): Likewise.
  52
  53 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  54             Michael Collison <michael.collison@arm.com>
  55
  56         * arm-dis.c (thumb32_opcodes): Add new instructions.
  57         (enum mve_instructions): Likewise.
  58         (is_mve_encoding_conflict): Likewise.
  59         (is_mve_unpredictable): Likewise.
  60         (print_mve_size): Likewise.
  61
  62 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  63             Michael Collison <michael.collison@arm.com>
  64
  65         * arm-dis.c (thumb32_opcodes): Add new instructions.
  66         (enum mve_instructions): Likewise.
  67         (is_mve_encoding_conflict): Handle new instructions.
  68         (is_mve_undefined): Likewise.
  69         (is_mve_unpredictable): Likewise.
  70         (print_mve_size): Likewise.
  71
  72 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  73             Michael Collison <michael.collison@arm.com>
  74
  75         * arm-dis.c (thumb32_opcodes): Add new instructions.
  76         (enum mve_instructions): Likewise.
  77         (is_mve_encoding_conflict): Handle new instructions.
  78         (is_mve_undefined): Likewise.
  79         (is_mve_unpredictable): Likewise.
  80         (print_mve_size): Likewise.
  81         (print_insn_mve): Likewise.
  82
  83 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  84             Michael Collison <michael.collison@arm.com>
  85
  86         * arm-dis.c (thumb32_opcodes): Add new instructions.
  87         (print_insn_thumb32): Handle new instructions.
  88
  89 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  90             Michael Collison <michael.collison@arm.com>
  91
  92         * arm-dis.c (enum mve_instructions): Add new instructions.
  93         (enum mve_undefined): Add new reasons.
  94         (is_mve_encoding_conflict): Handle new instructions.
  95         (is_mve_undefined): Likewise.
  96         (is_mve_unpredictable): Likewise.
  97         (print_mve_undefined): Likewise.
  98         (print_mve_size): Likewise.
  99         (print_mve_shift_n): Likewise.
 100         (print_insn_mve): Likewise.
 101
 102 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 103             Michael Collison <michael.collison@arm.com>
 104
 105         * arm-dis.c (enum mve_instructions): Add new instructions.
 106         (is_mve_encoding_conflict): Handle new instructions.
 107         (is_mve_unpredictable): Likewise.
 108         (print_mve_rotate): Likewise.
 109         (print_mve_size): Likewise.
 110         (print_insn_mve): Likewise.
 111
 112 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 113             Michael Collison <michael.collison@arm.com>
 114
 115         * arm-dis.c (enum mve_instructions): Add new instructions.
 116         (is_mve_encoding_conflict): Handle new instructions.
 117         (is_mve_unpredictable): Likewise.
 118         (print_mve_size): Likewise.
 119         (print_insn_mve): Likewise.
 120
 121 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 122             Michael Collison <michael.collison@arm.com>
 123
 124         * arm-dis.c (enum mve_instructions): Add new instructions.
 125         (enum mve_undefined): Add new reasons.
 126         (is_mve_encoding_conflict): Handle new instructions.
 127         (is_mve_undefined): Likewise.
 128         (is_mve_unpredictable): Likewise.
 129         (print_mve_undefined): Likewise.
 130         (print_mve_size): Likewise.
 131         (print_insn_mve): Likewise.
 132
 133 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 134             Michael Collison <michael.collison@arm.com>
 135
 136         * arm-dis.c (enum mve_instructions): Add new instructions.
 137         (is_mve_encoding_conflict): Handle new instructions.
 138         (is_mve_undefined): Likewise.
 139         (is_mve_unpredictable): Likewise.
 140         (print_mve_size): Likewise.
 141         (print_insn_mve): Likewise.
 142
 143 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 144             Michael Collison <michael.collison@arm.com>
 145
 146         * arm-dis.c (enum mve_instructions): Add new instructions.
 147         (enum mve_unpredictable): Add new reasons.
 148         (enum mve_undefined): Likewise.
 149         (is_mve_okay_in_it): Handle new isntructions.
 150         (is_mve_encoding_conflict): Likewise.
 151         (is_mve_undefined): Likewise.
 152         (is_mve_unpredictable): Likewise.
 153         (print_mve_vmov_index): Likewise.
 154         (print_simd_imm8): Likewise.
 155         (print_mve_undefined): Likewise.
 156         (print_mve_unpredictable): Likewise.
 157         (print_mve_size): Likewise.
 158         (print_insn_mve): Likewise.
 159
 160 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 161             Michael Collison <michael.collison@arm.com>
 162
 163         * arm-dis.c (enum mve_instructions): Add new instructions.
 164         (enum mve_unpredictable): Add new reasons.
 165         (enum mve_undefined): Likewise.
 166         (is_mve_encoding_conflict): Handle new instructions.
 167         (is_mve_undefined): Likewise.
 168         (is_mve_unpredictable): Likewise.
 169         (print_mve_undefined): Likewise.
 170         (print_mve_unpredictable): Likewise.
 171         (print_mve_rounding_mode): Likewise.
 172         (print_mve_vcvt_size): Likewise.
 173         (print_mve_size): Likewise.
 174         (print_insn_mve): Likewise.
 175
 176 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 177             Michael Collison <michael.collison@arm.com>
 178
 179         * arm-dis.c (enum mve_instructions): Add new instructions.
 180         (enum mve_unpredictable): Add new reasons.
 181         (enum mve_undefined): Likewise.
 182         (is_mve_undefined): Handle new instructions.
 183         (is_mve_unpredictable): Likewise.
 184         (print_mve_undefined): Likewise.
 185         (print_mve_unpredictable): Likewise.
 186         (print_mve_size): Likewise.
 187         (print_insn_mve): Likewise.
 188
 189 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 190             Michael Collison <michael.collison@arm.com>
 191
 192         * arm-dis.c (enum mve_instructions): Add new instructions.
 193         (enum mve_undefined): Add new reasons.
 194         (insns): Add new instructions.
 195         (is_mve_encoding_conflict):
 196         (print_mve_vld_str_addr): New print function.
 197         (is_mve_undefined): Handle new instructions.
 198         (is_mve_unpredictable): Likewise.
 199         (print_mve_undefined): Likewise.
 200         (print_mve_size): Likewise.
 201         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 202         (print_insn_mve):  Handle new operands.
 203
 204 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 205             Michael Collison <michael.collison@arm.com>
 206
 207         * arm-dis.c (enum mve_instructions): Add new instructions.
 208         (enum mve_unpredictable): Add new reasons.
 209         (is_mve_encoding_conflict): Handle new instructions.
 210         (is_mve_unpredictable): Likewise.
 211         (mve_opcodes): Add new instructions.
 212         (print_mve_unpredictable): Handle new reasons.
 213         (print_mve_register_blocks): New print function.
 214         (print_mve_size): Handle new instructions.
 215         (print_insn_mve): Likewise.
 216
 217 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 218             Michael Collison <michael.collison@arm.com>
 219
 220         * arm-dis.c (enum mve_instructions): Add new instructions.
 221         (enum mve_unpredictable): Add new reasons.
 222         (enum mve_undefined): Likewise.
 223         (is_mve_encoding_conflict): Handle new instructions.
 224         (is_mve_undefined): Likewise.
 225         (is_mve_unpredictable): Likewise.
 226         (coprocessor_opcodes): Move NEON VDUP from here...
 227         (neon_opcodes): ... to here.
 228         (mve_opcodes): Add new instructions.
 229         (print_mve_undefined):  Handle new reasons.
 230         (print_mve_unpredictable): Likewise.
 231         (print_mve_size): Handle new instructions.
 232         (print_insn_neon): Handle vdup.
 233         (print_insn_mve): Handle new operands.
 234
 235 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 236             Michael Collison <michael.collison@arm.com>
 237
 238         * arm-dis.c (enum mve_instructions): Add new instructions.
 239         (enum mve_unpredictable): Add new values.
 240         (mve_opcodes): Add new instructions.
 241         (vec_condnames): New array with vector conditions.
 242         (mve_predicatenames): New array with predicate suffixes.
 243         (mve_vec_sizename): New array with vector sizes.
 244         (enum vpt_pred_state): New enum with vector predication states.
 245         (struct vpt_block): New struct type for vpt blocks.
 246         (vpt_block_state): Global struct to keep track of state.
 247         (mve_extract_pred_mask): New helper function.
 248         (num_instructions_vpt_block): Likewise.
 249         (mark_outside_vpt_block): Likewise.
 250         (mark_inside_vpt_block): Likewise.
 251         (invert_next_predicate_state): Likewise.
 252         (update_next_predicate_state): Likewise.
 253         (update_vpt_block_state): Likewise.
 254         (is_vpt_instruction): Likewise.
 255         (is_mve_encoding_conflict): Add entries for new instructions.
 256         (is_mve_unpredictable): Likewise.
 257         (print_mve_unpredictable): Handle new cases.
 258         (print_instruction_predicate): Likewise.
 259         (print_mve_size): New function.
 260         (print_vec_condition): New function.
 261         (print_insn_mve): Handle vpt blocks and new print operands.
 262
 263 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 264
 265         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 266         8, 14 and 15 for Armv8.1-M Mainline.
 267
 268 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 269             Michael Collison <michael.collison@arm.com>
 270
 271         * arm-dis.c (enum mve_instructions): New enum.
 272         (enum mve_unpredictable): Likewise.
 273         (enum mve_undefined): Likewise.
 274         (struct mopcode32): New struct.
 275         (is_mve_okay_in_it): New function.
 276         (is_mve_architecture): Likewise.
 277         (arm_decode_field): Likewise.
 278         (arm_decode_field_multiple): Likewise.
 279         (is_mve_encoding_conflict): Likewise.
 280         (is_mve_undefined): Likewise.
 281         (is_mve_unpredictable): Likewise.
 282         (print_mve_undefined): Likewise.
 283         (print_mve_unpredictable): Likewise.
 284         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 285         (print_insn_mve): New function.
 286         (print_insn_thumb32): Handle MVE architecture.
 287         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 288
 289 2019-05-10  Nick Clifton  <nickc@redhat.com>
 290
 291         PR 24538
 292         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 293         end of the table prematurely.
 294
 295 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 296
 297         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 298         macros for R6.
 299
 300 2019-05-11  Alan Modra  <amodra@gmail.com>
 301
 302         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 303         when -Mraw is in effect.
 304
 305 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 306
 307         * aarch64-dis-2.c: Regenerate.
 308         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 309         (OP_SVE_BBB): New variant set.
 310         (OP_SVE_DDDD): New variant set.
 311         (OP_SVE_HHH): New variant set.
 312         (OP_SVE_HHHU): New variant set.
 313         (OP_SVE_SSS): New variant set.
 314         (OP_SVE_SSSU): New variant set.
 315         (OP_SVE_SHH): New variant set.
 316         (OP_SVE_SBBU): New variant set.
 317         (OP_SVE_DSS): New variant set.
 318         (OP_SVE_DHHU): New variant set.
 319         (OP_SVE_VMV_HSD_BHS): New variant set.
 320         (OP_SVE_VVU_HSD_BHS): New variant set.
 321         (OP_SVE_VVVU_SD_BH): New variant set.
 322         (OP_SVE_VVVU_BHSD): New variant set.
 323         (OP_SVE_VVV_QHD_DBS): New variant set.
 324         (OP_SVE_VVV_HSD_BHS): New variant set.
 325         (OP_SVE_VVV_HSD_BHS2): New variant set.
 326         (OP_SVE_VVV_BHS_HSD): New variant set.
 327         (OP_SVE_VV_BHS_HSD): New variant set.
 328         (OP_SVE_VVV_SD): New variant set.
 329         (OP_SVE_VVU_BHS_HSD): New variant set.
 330         (OP_SVE_VZVV_SD): New variant set.
 331         (OP_SVE_VZVV_BH): New variant set.
 332         (OP_SVE_VZV_SD): New variant set.
 333         (aarch64_opcode_table): Add sve2 instructions.
 334
 335 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 336
 337         * aarch64-asm-2.c: Regenerated.
 338         * aarch64-dis-2.c: Regenerated.
 339         * aarch64-opc-2.c: Regenerated.
 340         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 341         for SVE_SHLIMM_UNPRED_22.
 342         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 343         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 344         operand.
 345
 346 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 347
 348         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 349         sve_size_tsz_bhs iclass encode.
 350         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 351         sve_size_tsz_bhs iclass decode.
 352
 353 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 354
 355         * aarch64-asm-2.c: Regenerated.
 356         * aarch64-dis-2.c: Regenerated.
 357         * aarch64-opc-2.c: Regenerated.
 358         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 359         for SVE_Zm4_11_INDEX.
 360         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 361         (fields): Handle SVE_i2h field.
 362         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 363         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 364
 365 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 366
 367         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 368         sve_shift_tsz_bhsd iclass encode.
 369         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 370         sve_shift_tsz_bhsd iclass decode.
 371
 372 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 373
 374         * aarch64-asm-2.c: Regenerated.
 375         * aarch64-dis-2.c: Regenerated.
 376         * aarch64-opc-2.c: Regenerated.
 377         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 378         (aarch64_encode_variant_using_iclass): Handle
 379         sve_shift_tsz_hsd iclass encode.
 380         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 381         sve_shift_tsz_hsd iclass decode.
 382         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 383         for SVE_SHRIMM_UNPRED_22.
 384         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 385         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 386         operand.
 387
 388 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 389
 390         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 391         sve_size_013 iclass encode.
 392         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 393         sve_size_013 iclass decode.
 394
 395 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 396
 397         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 398         sve_size_bh iclass encode.
 399         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 400         sve_size_bh iclass decode.
 401
 402 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 403
 404         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 405         sve_size_sd2 iclass encode.
 406         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 407         sve_size_sd2 iclass decode.
 408         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 409         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 410
 411 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 412
 413         * aarch64-asm-2.c: Regenerated.
 414         * aarch64-dis-2.c: Regenerated.
 415         * aarch64-opc-2.c: Regenerated.
 416         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 417         for SVE_ADDR_ZX.
 418         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 419         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 420
 421 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 422
 423         * aarch64-asm-2.c: Regenerated.
 424         * aarch64-dis-2.c: Regenerated.
 425         * aarch64-opc-2.c: Regenerated.
 426         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 427         for SVE_Zm3_11_INDEX.
 428         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 429         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 430         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 431         fields.
 432         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 433
 434 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 435
 436         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 437         sve_size_hsd2 iclass encode.
 438         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 439         sve_size_hsd2 iclass decode.
 440         * aarch64-opc.c (fields): Handle SVE_size field.
 441         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 442
 443 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 444
 445         * aarch64-asm-2.c: Regenerated.
 446         * aarch64-dis-2.c: Regenerated.
 447         * aarch64-opc-2.c: Regenerated.
 448         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 449         for SVE_IMM_ROT3.
 450         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 451         (fields): Handle SVE_rot3 field.
 452         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 453         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 454
 455 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 456
 457         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 458         instructions.
 459
 460 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 461
 462         * aarch64-tbl.h
 463         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 464         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 465         aarch64_feature_sve2bitperm): New feature sets.
 466         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 467         for feature set addresses.
 468         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 469         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 470
 471 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 472             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 473
 474         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 475         argument and set ASE_EVA_R6 appropriately.
 476         (set_default_mips_dis_options): Pass ISA to above.
 477         (parse_mips_dis_option): Likewise.
 478         * mips-opc.c (EVAR6): New macro.
 479         (mips_builtin_opcodes): Add llwpe, scwpe.
 480
 481 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 482
 483         * aarch64-asm-2.c: Regenerated.
 484         * aarch64-dis-2.c: Regenerated.
 485         * aarch64-opc-2.c: Regenerated.
 486         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 487         AARCH64_OPND_TME_UIMM16.
 488         (aarch64_print_operand): Likewise.
 489         * aarch64-tbl.h (QL_IMM_NIL): New.
 490         (TME): New.
 491         (_TME_INSN): New.
 492         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 493
 494 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 495
 496         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 497
 498 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 499             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 500
 501         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 502
 503 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 504
 505         * s12z-opc.h: Add extern "C" bracketing to help
 506         users who wish to use this interface in c++ code.
 507
 508 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 509
 510         * s12z-opc.c (bm_decode): Handle bit map operations with the
 511         "reserved0" mode.
 512
 513 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 514
 515         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 516         specifier.  Add entries for VLDR and VSTR of system registers.
 517         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 518         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 519         of %J and %K format specifier.
 520
 521 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 522
 523         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 524         Add new entries for VSCCLRM instruction.
 525         (print_insn_coprocessor): Handle new %C format control code.
 526
 527 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 528
 529         * arm-dis.c (enum isa): New enum.
 530         (struct sopcode32): New structure.
 531         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 532         set isa field of all current entries to ANY.
 533         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 534         Only match an entry if its isa field allows the current mode.
 535
 536 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 537
 538         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 539         CLRM.
 540         (print_insn_thumb32): Add logic to print %n CLRM register list.
 541
 542 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 543
 544         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 545         and %Q patterns.
 546
 547 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 548
 549         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 550         (print_insn_thumb32): Edit the switch case for %Z.
 551
 552 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 553
 554         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 555
 556 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 557
 558         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 559
 560 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 561
 562         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 563
 564 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 565
 566         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 567         Arm register with r13 and r15 unpredictable.
 568         (thumb32_opcodes): New instructions for bfx and bflx.
 569
 570 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 571
 572         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 573
 574 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 575
 576         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 577
 578 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 579
 580         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 581
 582 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 583
 584         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 585
 586 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 587
 588         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 589         "optr". ("operator" is a reserved word in c++).
 590
 591 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 592
 593         * aarch64-opc.c (aarch64_print_operand): Add case for
 594         AARCH64_OPND_Rt_SP.
 595         (verify_constraints): Likewise.
 596         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 597         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 598         to accept Rt|SP as first operand.
 599         (AARCH64_OPERANDS): Add new Rt_SP.
 600         * aarch64-asm-2.c: Regenerated.
 601         * aarch64-dis-2.c: Regenerated.
 602         * aarch64-opc-2.c: Regenerated.
 603
 604 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 605
 606         * aarch64-asm-2.c: Regenerated.
 607         * aarch64-dis-2.c: Likewise.
 608         * aarch64-opc-2.c: Likewise.
 609         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 610
 611 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 612
 613         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 614
 615 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 616
 617         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 618         * i386-init.h: Regenerated.
 619
 620 2019-04-07  Alan Modra  <amodra@gmail.com>
 621
 622         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 623         op_separator to control printing of spaces, comma and parens
 624         rather than need_comma, need_paren and spaces vars.
 625
 626 2019-04-07  Alan Modra  <amodra@gmail.com>
 627
 628         PR 24421
 629         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 630         (print_insn_neon, print_insn_arm): Likewise.
 631
 632 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 633
 634         * i386-dis-evex.h (evex_table): Updated to support BF16
 635         instructions.
 636         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 637         and EVEX_W_0F3872_P_3.
 638         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 639         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 640         * i386-opc.h (enum): Add CpuAVX512_BF16.
 641         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 642         * i386-opc.tbl: Add AVX512 BF16 instructions.
 643         * i386-init.h: Regenerated.
 644         * i386-tbl.h: Likewise.
 645
 646 2019-04-05  Alan Modra  <amodra@gmail.com>
 647
 648         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 649         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 650         to favour printing of "-" branch hint when using the "y" bit.
 651         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 652
 653 2019-04-05  Alan Modra  <amodra@gmail.com>
 654
 655         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 656         opcode until first operand is output.
 657
 658 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 659
 660         PR gas/24349
 661         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 662         (valid_bo_post_v2): Add support for 'at' branch hints.
 663         (insert_bo): Only error on branch on ctr.
 664         (get_bo_hint_mask): New function.
 665         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 666         for inserting 'at' branch hints.
 667         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 668         for extracting 'at' branch hints.
 669         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 670         (BOE): Delete operand.
 671         (BOM, BOP): New operands.
 672         (RM): Update value.
 673         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 674         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 675         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 676         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 677         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 678         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 679         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 680         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 681         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 682         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 683         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 684         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 685         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 686         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 687         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 688         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 689         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 690         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 691         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 692         bttarl+>: New extended mnemonics.
 693
 694 2019-03-28  Alan Modra  <amodra@gmail.com>
 695
 696         PR 24390
 697         * ppc-opc.c (BTF): Define.
 698         (powerpc_opcodes): Use for mtfsb*.
 699         * ppc-dis.c (print_insn_powerpc): Print fields with both
 700         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 701
 702 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 703
 704         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 705         (mapping_symbol_for_insn): Implement new algorithm.
 706         (print_insn): Remove duplicate code.
 707
 708 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 709
 710         * aarch64-dis.c (print_insn_aarch64):
 711         Implement override.
 712
 713 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 714
 715         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 716         order.
 717
 718 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 719
 720         * aarch64-dis.c (last_stop_offset): New.
 721         (print_insn_aarch64): Use stop_offset.
 722
 723 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 724
 725         PR gas/24359
 726         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 727         CPU_ANY_AVX2_FLAGS.
 728         * i386-init.h: Regenerated.
 729
 730 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 731
 732         PR gas/24348
 733         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 734         vmovdqu16, vmovdqu32 and vmovdqu64.
 735         * i386-tbl.h: Regenerated.
 736
 737 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 738
 739         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 740         from vstrszb, vstrszh, and vstrszf.
 741
 742 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 743
 744         * s390-opc.txt: Add instruction descriptions.
 745
 746 2019-02-08  Jim Wilson  <jimw@sifive.com>
 747
 748         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 749         <bne>: Likewise.
 750
 751 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 752
 753         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 754
 755 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 756
 757         PR binutils/23212
 758         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 759         * aarch64-opc.c (verify_elem_sd): New.
 760         (fields): Add FLD_sz entr.
 761         * aarch64-tbl.h (_SIMD_INSN): New.
 762         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 763         fmulx scalar and vector by element isns.
 764
 765 2019-02-07  Nick Clifton  <nickc@redhat.com>
 766
 767         * po/sv.po: Updated Swedish translation.
 768
 769 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 770
 771         * s390-mkopc.c (main): Accept arch13 as cpu string.
 772         * s390-opc.c: Add new instruction formats and instruction opcode
 773         masks.
 774         * s390-opc.txt: Add new arch13 instructions.
 775
 776 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 777
 778         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 779         (aarch64_opcode): Change encoding for stg, stzg
 780         st2g and st2zg.
 781         * aarch64-asm-2.c: Regenerated.
 782         * aarch64-dis-2.c: Regenerated.
 783         * aarch64-opc-2.c: Regenerated.
 784
 785 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 786
 787         * aarch64-asm-2.c: Regenerated.
 788         * aarch64-dis-2.c: Likewise.
 789         * aarch64-opc-2.c: Likewise.
 790         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 791
 792 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 793             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 794
 795         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 796         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 797         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 798         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 799         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 800         case for ldstgv_indexed.
 801         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 802         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 803         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 804         * aarch64-asm-2.c: Regenerated.
 805         * aarch64-dis-2.c: Regenerated.
 806         * aarch64-opc-2.c: Regenerated.
 807
 808 2019-01-23  Nick Clifton  <nickc@redhat.com>
 809
 810         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 811
 812 2019-01-21  Nick Clifton  <nickc@redhat.com>
 813
 814         * po/de.po: Updated German translation.
 815         * po/uk.po: Updated Ukranian translation.
 816
 817 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 818         * mips-dis.c (mips_arch_choices): Fix typo in
 819         gs464, gs464e and gs264e descriptors.
 820
 821 2019-01-19  Nick Clifton  <nickc@redhat.com>
 822
 823         * configure: Regenerate.
 824         * po/opcodes.pot: Regenerate.
 825
 826 2018-06-24  Nick Clifton  <nickc@redhat.com>
 827
 828         2.32 branch created.
 829
 830 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 831
 832         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 833         if it is null.
 834         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 835         zero.
 836
 837 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 838
 839         * configure: Regenerate.
 840
 841 2019-01-07  Alan Modra  <amodra@gmail.com>
 842
 843         * configure: Regenerate.
 844         * po/POTFILES.in: Regenerate.
 845
 846 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 847
 848         * s12z-opc.c: New file.
 849         * s12z-opc.h: New file.
 850         * s12z-dis.c: Removed all code not directly related to display
 851         of instructions.  Used the interface provided by the new files
 852         instead.
 853         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 854         * Makefile.in: Regenerate.
 855         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 856         * configure: Regenerate.
 857
 858 2019-01-01  Alan Modra  <amodra@gmail.com>
 859
 860         Update year range in copyright notice of all files.
 861
 862 For older changes see ChangeLog-2018
 863 \f
 864 Copyright (C) 2019 Free Software Foundation, Inc.
 865
 866 Copying and distribution of this file, with or without modification,
 867 are permitted in any medium without royalty provided the copyright
 868 notice and this notice are preserved.
 869
 870 Local Variables:
 871 mode: change-log
 872 left-margin: 8
 873 fill-column: 74
 874 version-control: never
 875 End: