opcodes/ChangeLog

   1 2017-10-25  Alan Modra  <amodra@gmail.com>
   2
   3         PR 22348
   4         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
   5         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
   6         (imm4flag, size_changed): Likewise.
   7         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
   8         (words, allWords, processing_argument_number): Likewise.
   9         (cst4flag, size_changed): Likewise.
  10         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
  11         (crx_cst4_maps): Rename from cst4_maps.
  12         (crx_no_op_insn): Rename from no_op_insn.
  13
  14 2017-10-24  Andrew Waterman  <andrew@sifive.com>
  15
  16         * riscv-opc.c (match_c_addi16sp) : New function.
  17         (match_c_addi4spn): New function.
  18         (match_c_lui): Don't allow 0-immediate encodings.
  19         (riscv_opcodes) <addi>: Use the above functions.
  20         <add>: Likewise.
  21         <c.addi4spn>: Likewise.
  22         <c.addi16sp>: Likewise.
  23
  24 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  25
  26         * i386-init.h: Regenerate
  27         * i386-tbl.h: Likewise
  28
  29 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  30
  31         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
  32         (enum): Add EVEX_W_0F3854_P_2.
  33         * i386-dis-evex.h (evex_table): Updated.
  34         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
  35         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
  36         (cpu_flags): Add CpuAVX512_BITALG.
  37         * i386-opc.h (enum): Add CpuAVX512_BITALG.
  38         (i386_cpu_flags): Add cpuavx512_bitalg..
  39         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
  40         * i386-init.h: Regenerate.
  41         * i386-tbl.h: Likewise.
  42
  43 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  44
  45         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
  46         * i386-dis-evex.h (evex_table): Updated.
  47         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
  48         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
  49         (cpu_flags): Add CpuAVX512_VNNI.
  50         * i386-opc.h (enum): Add CpuAVX512_VNNI.
  51         (i386_cpu_flags): Add cpuavx512_vnni.
  52         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
  53         * i386-init.h: Regenerate.
  54         * i386-tbl.h: Likewise.
  55
  56 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  57
  58         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
  59         (enum): Remove VEX_LEN_0F3A44_P_2.
  60         (vex_len_table): Ditto.
  61         (enum): Remove VEX_W_0F3A44_P_2.
  62         (vew_w_table): Ditto.
  63         (prefix_table): Adjust instructions (see prefixes above).
  64         * i386-dis-evex.h (evex_table):
  65         Add new instructions (see prefixes above).
  66         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
  67         (bitfield_cpu_flags): Ditto.
  68         * i386-opc.h (enum): Ditto.
  69         (i386_cpu_flags): Ditto.
  70         (CpuUnused): Comment out to avoid zero-width field problem.
  71         * i386-opc.tbl (vpclmulqdq): New instruction.
  72         * i386-init.h: Regenerate.
  73         * i386-tbl.h: Ditto.
  74
  75 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  76
  77         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
  78         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
  79         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
  80         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
  81         (vex_len_table): Ditto.
  82         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
  83         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
  84         (vew_w_table): Ditto.
  85         (prefix_table): Adjust instructions (see prefixes above).
  86         * i386-dis-evex.h (evex_table):
  87         Add new instructions (see prefixes above).
  88         * i386-gen.c (cpu_flag_init): Add VAES.
  89         (bitfield_cpu_flags): Ditto.
  90         * i386-opc.h (enum): Ditto.
  91         (i386_cpu_flags): Ditto.
  92         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
  93         * i386-init.h: Regenerate.
  94         * i386-tbl.h: Ditto.
  95
  96 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  97
  98         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
  99         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 100         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 101         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 102         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 103         (prefix_table): Updated (see prefixes above).
 104         (three_byte_table): Likewise.
 105         (vex_w_table): Likewise.
 106         * i386-dis-evex.h: Likewise.
 107         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 108         (cpu_flags): Add CpuGFNI.
 109         * i386-opc.h (enum): Add CpuGFNI.
 110         (i386_cpu_flags): Add cpugfni.
 111         * i386-opc.tbl: Add Intel GFNI instructions.
 112         * i386-init.h: Regenerate.
 113         * i386-tbl.h: Likewise.
 114
 115 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 116
 117         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 118         Define EXbScalar and EXwScalar for OP_EX.
 119         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 120         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 121         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 122         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 123         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 124         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 125         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 126         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 127         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 128         (OP_E_memory): Likewise.
 129         * i386-dis-evex.h: Updated.
 130         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 131         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 132         (cpu_flags): Add CpuAVX512_VBMI2.
 133         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 134         (i386_cpu_flags): Add cpuavx512_vbmi2.
 135         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 136         * i386-init.h: Regenerate.
 137         * i386-tbl.h: Likewise.
 138
 139 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 140
 141         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 142
 143 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 144
 145         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 146         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 147         K15. Add jmpix pattern.
 148
 149 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 150
 151         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 152
 153 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 154
 155         * s390-opc.c (INSTR_SI_RD): New macro.
 156         (INSTR_S_RD): Adjust example instruction.
 157         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 158         SI_RD.
 159
 160 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 161
 162         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 163         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 164         VLE multimple load/store instructions. Old e_ldm* variants are
 165         kept as aliases.
 166         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 167
 168 2017-09-27  Nick Clifton  <nickc@redhat.com>
 169
 170         PR 22179
 171         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 172         names for the fmv.x.s and fmv.s.x instructions respectively.
 173
 174 2017-09-26  do  <do@nerilex.org>
 175
 176         PR 22123
 177         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 178         be used on CPUs that have emacs support.
 179
 180 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 181
 182         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 183
 184 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 185
 186         * nds32-asm.c: Rename __BIT() to N32_BIT().
 187         * nds32-asm.h: Likewise.
 188         * nds32-dis.c: Likewise.
 189
 190 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 191
 192         * i386-dis.c (last_active_prefix): Removed.
 193         (ckprefix): Don't set last_active_prefix.
 194         (NOTRACK_Fixup): Don't check last_active_prefix.
 195
 196 2017-08-31  Nick Clifton  <nickc@redhat.com>
 197
 198         * po/fr.po: Updated French translation.
 199
 200 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 201
 202         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 203         fields.
 204
 205 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 206             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 207
 208         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 209         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 210         New entries efs2 and spe2.
 211         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 212         (SPE2_OPCD_SEGS): New macro.
 213         (spe2_opcd_indices): New.
 214         (disassemble_init_powerpc): Handle SPE2 opcodes.
 215         (lookup_spe2): New function.
 216         (print_insn_powerpc): call lookup_spe2.
 217         * ppc-opc.c (insert_evuimm1_ex0): New function.
 218         (extract_evuimm1_ex0): Likewise.
 219         (insert_evuimm_lt8): Likewise.
 220         (extract_evuimm_lt8): Likewise.
 221         (insert_off_spe2): Likewise.
 222         (extract_off_spe2): Likewise.
 223         (insert_Ddd): Likewise.
 224         (extract_Ddd): Likewise.
 225         (DD): New operand.
 226         (EVUIMM_LT8): Likewise.
 227         (EVUIMM_LT16): Adjust.
 228         (MMMM): New operand.
 229         (EVUIMM_1): Likewise.
 230         (EVUIMM_1_EX0): Likewise.
 231         (EVUIMM_2): Adjust.
 232         (NNN): New operand.
 233         (VX_OFF_SPE2): Likewise.
 234         (BBB): Likewise.
 235         (DDD): Likewise.
 236         (VX_MASK_DDD): New mask.
 237         (HH): New operand.
 238         (VX_RA_CONST): New macro.
 239         (VX_RA_CONST_MASK): Likewise.
 240         (VX_RB_CONST): Likewise.
 241         (VX_RB_CONST_MASK): Likewise.
 242         (VX_OFF_SPE2_MASK): Likewise.
 243         (VX_SPE_CRFD): Likewise.
 244         (VX_SPE_CRFD_MASK VX): Likewise.
 245         (VX_SPE2_CLR): Likewise.
 246         (VX_SPE2_CLR_MASK): Likewise.
 247         (VX_SPE2_SPLATB): Likewise.
 248         (VX_SPE2_SPLATB_MASK): Likewise.
 249         (VX_SPE2_OCTET): Likewise.
 250         (VX_SPE2_OCTET_MASK): Likewise.
 251         (VX_SPE2_DDHH): Likewise.
 252         (VX_SPE2_DDHH_MASK): Likewise.
 253         (VX_SPE2_HH): Likewise.
 254         (VX_SPE2_HH_MASK): Likewise.
 255         (VX_SPE2_EVMAR): Likewise.
 256         (VX_SPE2_EVMAR_MASK): Likewise.
 257         (PPCSPE2): Likewise.
 258         (PPCEFS2): Likewise.
 259         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 260         (powerpc_macros): Map old SPE instructions have new names
 261         with the same opcodes. Add SPE2 instructions which just are
 262         mapped to SPE2.
 263         (spe2_opcodes): Add SPE2 opcodes.
 264
 265 2017-08-23  Alan Modra  <amodra@gmail.com>
 266
 267         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 268         extract functions earlier, deleting forward declarations.
 269         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 270         RA_MASK.
 271
 272 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 273
 274         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 275
 276 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 277             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 278
 279         * ppc-opc.c (insert_evuimm2_ex0): New function.
 280         (extract_evuimm2_ex0): Likewise.
 281         (insert_evuimm4_ex0): Likewise.
 282         (extract_evuimm4_ex0): Likewise.
 283         (insert_evuimm8_ex0): Likewise.
 284         (extract_evuimm8_ex0): Likewise.
 285         (insert_evuimm_lt16): Likewise.
 286         (extract_evuimm_lt16): Likewise.
 287         (insert_rD_rS_even): Likewise.
 288         (extract_rD_rS_even): Likewise.
 289         (insert_off_lsp): Likewise.
 290         (extract_off_lsp): Likewise.
 291         (RD_EVEN): New operand.
 292         (RS_EVEN): Likewise.
 293         (RSQ): Adjust.
 294         (EVUIMM_LT16): New operand.
 295         (HTM_SI): Adjust.
 296         (EVUIMM_2_EX0): New operand.
 297         (EVUIMM_4): Adjust.
 298         (EVUIMM_4_EX0): New operand.
 299         (EVUIMM_8): Adjust.
 300         (EVUIMM_8_EX0): New operand.
 301         (WS): Adjust.
 302         (VX_OFF): New operand.
 303         (VX_LSP): New macro.
 304         (VX_LSP_MASK): Likewise.
 305         (VX_LSP_OFF_MASK): Likewise.
 306         (PPC_OPCODE_LSP): Likewise.
 307         (vle_opcodes): Add LSP opcodes.
 308         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 309
 310 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 311
 312         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 313         register operands in CRC instructions.
 314         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 315         comments.
 316
 317 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 318
 319         * disassemble.c (disassembler): Mark big and mach with
 320         ATTRIBUTE_UNUSED.
 321
 322 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 323
 324         * disassemble.c (disassembler): Remove arch/mach/endian
 325         assertions.
 326
 327 2017-07-25  Nick Clifton  <nickc@redhat.com>
 328
 329         PR 21739
 330         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 331         message.
 332         (insert_r0): Likewise.
 333         (insert_r1): Likewise.
 334         (insert_r2): Likewise.
 335         (insert_r3): Likewise.
 336         (insert_sp): Likewise.
 337         (insert_gp): Likewise.
 338         (insert_pcl): Likewise.
 339         (insert_blink): Likewise.
 340         (insert_ilink1): Likewise.
 341         (insert_ilink2): Likewise.
 342         (insert_ras): Likewise.
 343         (insert_rbs): Likewise.
 344         (insert_rcs): Likewise.
 345         (insert_simm3s): Likewise.
 346         (insert_rrange): Likewise.
 347         (insert_r13el): Likewise.
 348         (insert_fpel): Likewise.
 349         (insert_blinkel): Likewise.
 350         (insert_pclel): Likewise.
 351         (insert_nps_bitop_size_2b): Likewise.
 352         (insert_nps_imm_offset): Likewise.
 353         (insert_nps_imm_entry): Likewise.
 354         (insert_nps_size_16bit): Likewise.
 355         (insert_nps_##NAME##_pos): Likewise.
 356         (insert_nps_##NAME): Likewise.
 357         (insert_nps_bitop_ins_ext): Likewise.
 358         (insert_nps_##NAME): Likewise.
 359         (insert_nps_min_hofs): Likewise.
 360         (insert_nps_##NAME): Likewise.
 361         (insert_nps_rbdouble_64): Likewise.
 362         (insert_nps_misc_imm_offset): Likewise.
 363         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 364         option description.
 365
 366 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 367             Jiong Wang  <jiong.wang@arm.com>
 368
 369         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 370         correct the print.
 371         * aarch64-dis-2.c: Regenerated.
 372
 373 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 374
 375         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 376         table.
 377
 378 2017-07-20  Nick Clifton  <nickc@redhat.com>
 379
 380         * po/de.po: Updated German translation.
 381
 382 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 383
 384         * arc-regs.h (sec_stat): New aux register.
 385         (aux_kernel_sp): Likewise.
 386         (aux_sec_u_sp): Likewise.
 387         (aux_sec_k_sp): Likewise.
 388         (sec_vecbase_build): Likewise.
 389         (nsc_table_top): Likewise.
 390         (nsc_table_base): Likewise.
 391         (ersec_stat): Likewise.
 392         (aux_sec_except): Likewise.
 393
 394 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 395
 396         * arc-opc.c (extract_uimm12_20): New function.
 397         (UIMM12_20): New operand.
 398         (SIMM3_5_S): Adjust.
 399         * arc-tbl.h (sjli): Add new instruction.
 400
 401 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 402             John Eric Martin  <John.Martin@emmicro-us.com>
 403
 404         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 405         (UIMM3_23): Adjust accordingly.
 406         * arc-regs.h: Add/correct jli_base register.
 407         * arc-tbl.h (jli_s): Likewise.
 408
 409 2017-07-18  Nick Clifton  <nickc@redhat.com>
 410
 411         PR 21775
 412         * aarch64-opc.c: Fix spelling typos.
 413         * i386-dis.c: Likewise.
 414
 415 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 416
 417         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 418         max_addr_offset and octets variables to size_t.
 419
 420 2017-07-12  Alan Modra  <amodra@gmail.com>
 421
 422         * po/da.po: Update from translationproject.org/latest/opcodes/.
 423         * po/de.po: Likewise.
 424         * po/es.po: Likewise.
 425         * po/fi.po: Likewise.
 426         * po/fr.po: Likewise.
 427         * po/id.po: Likewise.
 428         * po/it.po: Likewise.
 429         * po/nl.po: Likewise.
 430         * po/pt_BR.po: Likewise.
 431         * po/ro.po: Likewise.
 432         * po/sv.po: Likewise.
 433         * po/tr.po: Likewise.
 434         * po/uk.po: Likewise.
 435         * po/vi.po: Likewise.
 436         * po/zh_CN.po: Likewise.
 437
 438 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 439             Alan Modra  <amodra@gmail.com>
 440
 441         * cgen.sh: Mark generated files read-only.
 442         * epiphany-asm.c: Regenerate.
 443         * epiphany-desc.c: Regenerate.
 444         * epiphany-desc.h: Regenerate.
 445         * epiphany-dis.c: Regenerate.
 446         * epiphany-ibld.c: Regenerate.
 447         * epiphany-opc.c: Regenerate.
 448         * epiphany-opc.h: Regenerate.
 449         * fr30-asm.c: Regenerate.
 450         * fr30-desc.c: Regenerate.
 451         * fr30-desc.h: Regenerate.
 452         * fr30-dis.c: Regenerate.
 453         * fr30-ibld.c: Regenerate.
 454         * fr30-opc.c: Regenerate.
 455         * fr30-opc.h: Regenerate.
 456         * frv-asm.c: Regenerate.
 457         * frv-desc.c: Regenerate.
 458         * frv-desc.h: Regenerate.
 459         * frv-dis.c: Regenerate.
 460         * frv-ibld.c: Regenerate.
 461         * frv-opc.c: Regenerate.
 462         * frv-opc.h: Regenerate.
 463         * ip2k-asm.c: Regenerate.
 464         * ip2k-desc.c: Regenerate.
 465         * ip2k-desc.h: Regenerate.
 466         * ip2k-dis.c: Regenerate.
 467         * ip2k-ibld.c: Regenerate.
 468         * ip2k-opc.c: Regenerate.
 469         * ip2k-opc.h: Regenerate.
 470         * iq2000-asm.c: Regenerate.
 471         * iq2000-desc.c: Regenerate.
 472         * iq2000-desc.h: Regenerate.
 473         * iq2000-dis.c: Regenerate.
 474         * iq2000-ibld.c: Regenerate.
 475         * iq2000-opc.c: Regenerate.
 476         * iq2000-opc.h: Regenerate.
 477         * lm32-asm.c: Regenerate.
 478         * lm32-desc.c: Regenerate.
 479         * lm32-desc.h: Regenerate.
 480         * lm32-dis.c: Regenerate.
 481         * lm32-ibld.c: Regenerate.
 482         * lm32-opc.c: Regenerate.
 483         * lm32-opc.h: Regenerate.
 484         * lm32-opinst.c: Regenerate.
 485         * m32c-asm.c: Regenerate.
 486         * m32c-desc.c: Regenerate.
 487         * m32c-desc.h: Regenerate.
 488         * m32c-dis.c: Regenerate.
 489         * m32c-ibld.c: Regenerate.
 490         * m32c-opc.c: Regenerate.
 491         * m32c-opc.h: Regenerate.
 492         * m32r-asm.c: Regenerate.
 493         * m32r-desc.c: Regenerate.
 494         * m32r-desc.h: Regenerate.
 495         * m32r-dis.c: Regenerate.
 496         * m32r-ibld.c: Regenerate.
 497         * m32r-opc.c: Regenerate.
 498         * m32r-opc.h: Regenerate.
 499         * m32r-opinst.c: Regenerate.
 500         * mep-asm.c: Regenerate.
 501         * mep-desc.c: Regenerate.
 502         * mep-desc.h: Regenerate.
 503         * mep-dis.c: Regenerate.
 504         * mep-ibld.c: Regenerate.
 505         * mep-opc.c: Regenerate.
 506         * mep-opc.h: Regenerate.
 507         * mt-asm.c: Regenerate.
 508         * mt-desc.c: Regenerate.
 509         * mt-desc.h: Regenerate.
 510         * mt-dis.c: Regenerate.
 511         * mt-ibld.c: Regenerate.
 512         * mt-opc.c: Regenerate.
 513         * mt-opc.h: Regenerate.
 514         * or1k-asm.c: Regenerate.
 515         * or1k-desc.c: Regenerate.
 516         * or1k-desc.h: Regenerate.
 517         * or1k-dis.c: Regenerate.
 518         * or1k-ibld.c: Regenerate.
 519         * or1k-opc.c: Regenerate.
 520         * or1k-opc.h: Regenerate.
 521         * or1k-opinst.c: Regenerate.
 522         * xc16x-asm.c: Regenerate.
 523         * xc16x-desc.c: Regenerate.
 524         * xc16x-desc.h: Regenerate.
 525         * xc16x-dis.c: Regenerate.
 526         * xc16x-ibld.c: Regenerate.
 527         * xc16x-opc.c: Regenerate.
 528         * xc16x-opc.h: Regenerate.
 529         * xstormy16-asm.c: Regenerate.
 530         * xstormy16-desc.c: Regenerate.
 531         * xstormy16-desc.h: Regenerate.
 532         * xstormy16-dis.c: Regenerate.
 533         * xstormy16-ibld.c: Regenerate.
 534         * xstormy16-opc.c: Regenerate.
 535         * xstormy16-opc.h: Regenerate.
 536
 537 2017-07-07  Alan Modra  <amodra@gmail.com>
 538
 539         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 540         * m32c-dis.c: Regenerate.
 541         * mep-dis.c: Regenerate.
 542
 543 2017-07-05  Borislav Petkov  <bp@suse.de>
 544
 545         * i386-dis.c: Enable ModRM.reg /6 aliases.
 546
 547 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 548
 549         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 550         with vmrs and vmsr.
 551
 552 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 553
 554         * configure: Regenerate.
 555
 556 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 557
 558         * po/opcodes.pot: Regenerate.
 559
 560 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 561
 562         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 563         entries to the MSA ASE instruction block.
 564
 565 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 566             Maciej W. Rozycki  <macro@imgtec.com>
 567
 568         * micromips-opc.c (XPA, XPAVZ): New macros.
 569         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 570         "mthgc0".
 571
 572 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 573             Maciej W. Rozycki  <macro@imgtec.com>
 574
 575         * micromips-opc.c (I36): New macro.
 576         (micromips_opcodes): Add "eretnc".
 577
 578 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 579             Andrew Bennett  <andrew.bennett@imgtec.com>
 580
 581         * mips-dis.c (mips_calculate_combination_ases): Handle the
 582         ASE_XPA_VIRT flag.
 583         (parse_mips_ase_option): New function.
 584         (parse_mips_dis_option): Factor out ASE option handling to the
 585         new function.  Call `mips_calculate_combination_ases'.
 586         * mips-opc.c (XPAVZ): New macro.
 587         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 588         "mfhgc0", "mthc0" and "mthgc0".
 589
 590 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 591
 592         * mips-dis.c (mips_calculate_combination_ases): New function.
 593         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 594         calculation to the new function.
 595         (set_default_mips_dis_options): Call the new function.
 596
 597 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 598
 599         * arc-dis.c (parse_disassembler_options): Use
 600         FOR_EACH_DISASSEMBLER_OPTION.
 601
 602 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 603
 604         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 605         disassembler option strings.
 606         (parse_cpu_option): Likewise.
 607
 608 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 609
 610         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 611         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 612         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 613         (aarch64_feature_dotprod, DOT_INSN): New.
 614         (udot, sdot): New.
 615         * aarch64-dis-2.c: Regenerated.
 616
 617 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 618
 619         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 620
 621 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 622             Matthew Fortune  <matthew.fortune@imgtec.com>
 623             Andrew Bennett  <andrew.bennett@imgtec.com>
 624
 625         * mips-formats.h (INT_BIAS): New macro.
 626         (INT_ADJ): Redefine in INT_BIAS terms.
 627         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 628         (mips_print_save_restore): New function.
 629         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 630         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 631         call.
 632         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 633         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 634         OP_SAVE_RESTORE_LIST handling, factored out from here.
 635         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 636         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 637         (mips_builtin_opcodes): Add "restore" and "save" entries.
 638         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 639         (IAMR2): New macro.
 640         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 641
 642 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 643
 644         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 645         alias; do not mark SLTI instruction as an alias.
 646
 647 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 648
 649         * i386-dis.c (RM_0FAE_REG_5): Removed.
 650         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 651         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 652         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 653         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 654         PREFIX_MOD_3_0F01_REG_5_RM_0.
 655         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 656         PREFIX_MOD_3_0FAE_REG_5.
 657         (mod_table): Update MOD_0FAE_REG_5.
 658         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 659         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 660         * i386-tbl.h: Regenerated.
 661
 662 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 663
 664         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 665         * i386-opc.tbl: Likewise.
 666         * i386-tbl.h: Regenerated.
 667
 668 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 669
 670         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 671         and "jmp{&|}".
 672         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 673         prefix.
 674
 675 2017-06-19  Nick Clifton  <nickc@redhat.com>
 676
 677         PR binutils/21614
 678         * score-dis.c (score_opcodes): Add sentinel.
 679
 680 2017-06-16  Alan Modra  <amodra@gmail.com>
 681
 682         * rx-decode.c: Regenerate.
 683
 684 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 685
 686         PR binutils/21594
 687         * i386-dis.c (OP_E_register): Check valid bnd register.
 688         (OP_G): Likewise.
 689
 690 2017-06-15  Nick Clifton  <nickc@redhat.com>
 691
 692         PR binutils/21595
 693         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 694         range value.
 695
 696 2017-06-15  Nick Clifton  <nickc@redhat.com>
 697
 698         PR binutils/21588
 699         * rl78-decode.opc (OP_BUF_LEN): Define.
 700         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 701         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 702         array.
 703         * rl78-decode.c: Regenerate.
 704
 705 2017-06-15  Nick Clifton  <nickc@redhat.com>
 706
 707         PR binutils/21586
 708         * bfin-dis.c (gregs): Clip index to prevent overflow.
 709         (regs): Likewise.
 710         (regs_lo): Likewise.
 711         (regs_hi): Likewise.
 712
 713 2017-06-14  Nick Clifton  <nickc@redhat.com>
 714
 715         PR binutils/21576
 716         * score7-dis.c (score_opcodes): Add sentinel.
 717
 718 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 719
 720         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 721         * arm-dis.c: Likewise.
 722         * ia64-dis.c: Likewise.
 723         * mips-dis.c: Likewise.
 724         * spu-dis.c: Likewise.
 725         * disassemble.h (print_insn_aarch64): New declaration, moved from
 726         include/dis-asm.h.
 727         (print_insn_big_arm, print_insn_big_mips): Likewise.
 728         (print_insn_i386, print_insn_ia64): Likewise.
 729         (print_insn_little_arm, print_insn_little_mips): Likewise.
 730
 731 2017-06-14  Nick Clifton  <nickc@redhat.com>
 732
 733         PR binutils/21587
 734         * rx-decode.opc: Include libiberty.h
 735         (GET_SCALE): New macro - validates access to SCALE array.
 736         (GET_PSCALE): New macro - validates access to PSCALE array.
 737         (DIs, SIs, S2Is, rx_disp): Use new macros.
 738         * rx-decode.c: Regenerate.
 739
 740 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 741
 742         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 743
 744 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 745
 746         * arc-dis.c (enforced_isa_mask): Declare.
 747         (cpu_types): Likewise.
 748         (parse_cpu_option): New function.
 749         (parse_disassembler_options): Use it.
 750         (print_insn_arc): Use enforced_isa_mask.
 751         (print_arc_disassembler_options): Document new options.
 752
 753 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 754
 755         * alpha-dis.c: Include disassemble.h, don't include
 756         dis-asm.h.
 757         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 758         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 759         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 760         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 761         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 762         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 763         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 764         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 765         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 766         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 767         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 768         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 769         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 770         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 771         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 772         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 773         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 774         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 775         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 776         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 777         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 778         * z80-dis.c, z8k-dis.c: Likewise.
 779         * disassemble.h: New file.
 780
 781 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 782
 783         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 784         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 785
 786 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 787
 788         * disassemble.c (disassembler): Add arguments a, big and mach.
 789         Use them.
 790
 791 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 792
 793         * i386-dis.c (NOTRACK_Fixup): New.
 794         (NOTRACK): Likewise.
 795         (NOTRACK_PREFIX): Likewise.
 796         (last_active_prefix): Likewise.
 797         (reg_table): Use NOTRACK on indirect call and jmp.
 798         (ckprefix): Set last_active_prefix.
 799         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 800         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 801         * i386-opc.h (NoTrackPrefixOk): New.
 802         (i386_opcode_modifier): Add notrackprefixok.
 803         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 804         Add notrack.
 805         * i386-tbl.h: Regenerated.
 806
 807 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 808
 809         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 810         (X_IMM2): Define.
 811         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 812         bfd_mach_sparc_v9m8.
 813         (print_insn_sparc): Handle new operand types.
 814         * sparc-opc.c (MASK_M8): Define.
 815         (v6): Add MASK_M8.
 816         (v6notlet): Likewise.
 817         (v7): Likewise.
 818         (v8): Likewise.
 819         (v9): Likewise.
 820         (v9a): Likewise.
 821         (v9b): Likewise.
 822         (v9c): Likewise.
 823         (v9d): Likewise.
 824         (v9e): Likewise.
 825         (v9v): Likewise.
 826         (v9m): Likewise.
 827         (v9andleon): Likewise.
 828         (m8): Define.
 829         (HWS_VM8): Define.
 830         (HWS2_VM8): Likewise.
 831         (sparc_opcode_archs): Add entry for "m8".
 832         (sparc_opcodes): Add OSA2017 and M8 instructions
 833         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 834         fpx{ll,ra,rl}64x,
 835         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 836         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 837         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 838         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 839         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 840         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 841         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 842         ASI_CORE_SELECT_COMMIT_NHT.
 843
 844 2017-05-18  Alan Modra  <amodra@gmail.com>
 845
 846         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 847         * aarch64-dis.c: Likewise.
 848         * aarch64-gen.c: Likewise.
 849         * aarch64-opc.c: Likewise.
 850
 851 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 852             Matthew Fortune  <matthew.fortune@imgtec.com>
 853
 854         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 855         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 856         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 857         (print_insn_arg) <OP_REG28>: Add handler.
 858         (validate_insn_args) <OP_REG28>: Handle.
 859         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 860         32-bit encoding and 9-bit immediates.
 861         (print_insn_mips16): Handle MIPS16 instructions that require
 862         32-bit encoding and MFC0/MTC0 operand decoding.
 863         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 864         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 865         (RD_C0, WR_C0, E2, E2MT): New macros.
 866         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 867         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 868         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 869         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 870         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 871         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 872         instructions, "swl", "swr", "sync" and its "sync_acquire",
 873         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 874         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 875         regular/extended entries for original MIPS16 ISA revision
 876         instructions whose extended forms are subdecoded in the MIPS16e2
 877         ISA revision: "li", "sll" and "srl".
 878
 879 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 880
 881         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 882         reference in CP0 move operand decoding.
 883
 884 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 885
 886         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 887         type to hexadecimal.
 888         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 889
 890 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 891
 892         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 893         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 894         "sync_rmb" and "sync_wmb" as aliases.
 895         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 896         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 897
 898 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 899
 900         * arc-dis.c (parse_option): Update quarkse_em option..
 901         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 902         QUARKSE1.
 903         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 904
 905 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 906
 907         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 908
 909 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 910
 911         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 912         register.
 913
 914 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 915
 916         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 917         and branches and not synthetic data instructions.
 918
 919 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 920
 921         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 922
 923 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 924
 925         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 926         * arc-opc.c (insert_r13el): New function.
 927         (R13_EL): Define.
 928         * arc-tbl.h: Add new enter/leave variants.
 929
 930 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 931
 932         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 933
 934 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 935
 936         * mips-dis.c (print_mips_disassembler_options): Add
 937         `no-aliases'.
 938
 939 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 940
 941         * mips16-opc.c (AL): New macro.
 942         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 943         of "ld" and "lw" as aliases.
 944
 945 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 946
 947         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 948         arguments.
 949
 950 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 951             Alan Modra  <amodra@gmail.com>
 952
 953         * ppc-opc.c (ELEV): Define.
 954         (vle_opcodes): Add se_rfgi and e_sc.
 955         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 956         for E200Z4.
 957
 958 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 959
 960         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 961
 962 2017-04-21  Nick Clifton  <nickc@redhat.com>
 963
 964         PR binutils/21380
 965         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 966         LD3R and LD4R.
 967
 968 2017-04-13  Alan Modra  <amodra@gmail.com>
 969
 970         * epiphany-desc.c: Regenerate.
 971         * fr30-desc.c: Regenerate.
 972         * frv-desc.c: Regenerate.
 973         * ip2k-desc.c: Regenerate.
 974         * iq2000-desc.c: Regenerate.
 975         * lm32-desc.c: Regenerate.
 976         * m32c-desc.c: Regenerate.
 977         * m32r-desc.c: Regenerate.
 978         * mep-desc.c: Regenerate.
 979         * mt-desc.c: Regenerate.
 980         * or1k-desc.c: Regenerate.
 981         * xc16x-desc.c: Regenerate.
 982         * xstormy16-desc.c: Regenerate.
 983
 984 2017-04-11  Alan Modra  <amodra@gmail.com>
 985
 986         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 987         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 988         PPC_OPCODE_TMR for e6500.
 989         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 990         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 991         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 992         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 993         (PPCHTM): Define as PPC_OPCODE_POWER8.
 994         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 995
 996 2017-04-10  Alan Modra  <amodra@gmail.com>
 997
 998         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 999         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1000         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1001         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1002
1003 2017-04-09  Pip Cet  <pipcet@gmail.com>
1004
1005         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1006         appropriate floating-point precision directly.
1007
1008 2017-04-07  Alan Modra  <amodra@gmail.com>
1009
1010         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1011         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1012         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1013         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1014         vector instructions with E6500 not PPCVEC2.
1015
1016 2017-04-06  Pip Cet  <pipcet@gmail.com>
1017
1018         * Makefile.am: Add wasm32-dis.c.
1019         * configure.ac: Add wasm32-dis.c to wasm32 target.
1020         * disassemble.c: Add wasm32 disassembler code.
1021         * wasm32-dis.c: New file.
1022         * Makefile.in: Regenerate.
1023         * configure: Regenerate.
1024         * po/POTFILES.in: Regenerate.
1025         * po/opcodes.pot: Regenerate.
1026
1027 2017-04-05  Pedro Alves  <palves@redhat.com>
1028
1029         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1030         * arm-dis.c (parse_arm_disassembler_options): Constify.
1031         * ppc-dis.c (powerpc_init_dialect): Constify local.
1032         * vax-dis.c (parse_disassembler_options): Constify.
1033
1034 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1035
1036         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1037         RISCV_GP_SYMBOL.
1038
1039 2017-03-30  Pip Cet  <pipcet@gmail.com>
1040
1041         * configure.ac: Add (empty) bfd_wasm32_arch target.
1042         * configure: Regenerate
1043         * po/opcodes.pot: Regenerate.
1044
1045 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1046
1047         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1048         OSA2015.
1049         * opcodes/sparc-opc.c (asi_table): New ASIs.
1050
1051 2017-03-29  Alan Modra  <amodra@gmail.com>
1052
1053         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1054         "raw" option.
1055         (lookup_powerpc): Don't special case -1 dialect.  Handle
1056         PPC_OPCODE_RAW.
1057         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1058         lookup_powerpc call, pass it on second.
1059
1060 2017-03-27  Alan Modra  <amodra@gmail.com>
1061
1062         PR 21303
1063         * ppc-dis.c (struct ppc_mopt): Comment.
1064         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1065
1066 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1067
1068         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1069         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1070         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1071         (insert_nps_misc_imm_offset): New function.
1072         (extract_nps_misc imm_offset): New function.
1073         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1074         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1075
1076 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1077
1078         * s390-mkopc.c (main): Remove vx2 check.
1079         * s390-opc.txt: Remove vx2 instruction flags.
1080
1081 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1082
1083         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1084         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1085         (insert_nps_imm_offset): New function.
1086         (extract_nps_imm_offset): New function.
1087         (insert_nps_imm_entry): New function.
1088         (extract_nps_imm_entry): New function.
1089
1090 2017-03-17  Alan Modra  <amodra@gmail.com>
1091
1092         PR 21248
1093         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1094         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1095         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1096
1097 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1098
1099         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1100         <c.andi>: Likewise.
1101         <c.addiw> Likewise.
1102
1103 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1104
1105         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1106
1107 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1108
1109         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1110         <srl> Likewise.
1111         <srai> Likewise.
1112         <sra> Likewise.
1113
1114 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1115
1116         * i386-gen.c (opcode_modifiers): Replace S with Load.
1117         * i386-opc.h (S): Removed.
1118         (Load): New.
1119         (i386_opcode_modifier): Replace s with load.
1120         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1121         and {evex}.  Replace S with Load.
1122         * i386-tbl.h: Regenerated.
1123
1124 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1125
1126         * i386-opc.tbl: Use CpuCET on rdsspq.
1127         * i386-tbl.h: Regenerated.
1128
1129 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1130
1131         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1132         <vsx>: Do not use PPC_OPCODE_VSX3;
1133
1134 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1135
1136         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1137
1138 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1139
1140         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1141         (MOD_0F1E_PREFIX_1): Likewise.
1142         (MOD_0F38F5_PREFIX_2): Likewise.
1143         (MOD_0F38F6_PREFIX_0): Likewise.
1144         (RM_0F1E_MOD_3_REG_7): Likewise.
1145         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1146         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1147         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1148         (PREFIX_0F1E): Likewise.
1149         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1150         (PREFIX_0F38F5): Likewise.
1151         (dis386_twobyte): Use PREFIX_0F1E.
1152         (reg_table): Add REG_0F1E_MOD_3.
1153         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1154         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1155         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1156         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1157         (three_byte_table): Use PREFIX_0F38F5.
1158         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1159         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1160         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1161         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1162         PREFIX_MOD_3_0F01_REG_5_RM_2.
1163         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1164         (cpu_flags): Add CpuCET.
1165         * i386-opc.h (CpuCET): New enum.
1166         (CpuUnused): Commented out.
1167         (i386_cpu_flags): Add cpucet.
1168         * i386-opc.tbl: Add Intel CET instructions.
1169         * i386-init.h: Regenerated.
1170         * i386-tbl.h: Likewise.
1171
1172 2017-03-06  Alan Modra  <amodra@gmail.com>
1173
1174         PR 21124
1175         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1176         (extract_raq, extract_ras, extract_rbx): New functions.
1177         (powerpc_operands): Use opposite corresponding insert function.
1178         (Q_MASK): Define.
1179         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1180         register restriction.
1181
1182 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1183
1184         * disassemble.c Include "safe-ctype.h".
1185         (disassemble_init_for_target): Handle s390 init.
1186         (remove_whitespace_and_extra_commas): New function.
1187         (disassembler_options_cmp): Likewise.
1188         * arm-dis.c: Include "libiberty.h".
1189         (NUM_ELEM): Delete.
1190         (regnames): Use long disassembler style names.
1191         Add force-thumb and no-force-thumb options.
1192         (NUM_ARM_REGNAMES): Rename from this...
1193         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1194         (get_arm_regname_num_options): Delete.
1195         (set_arm_regname_option): Likewise.
1196         (get_arm_regnames): Likewise.
1197         (parse_disassembler_options): Likewise.
1198         (parse_arm_disassembler_option): Rename from this...
1199         (parse_arm_disassembler_options): ...to this.  Make static.
1200         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1201         (print_insn): Use parse_arm_disassembler_options.
1202         (disassembler_options_arm): New function.
1203         (print_arm_disassembler_options): Handle updated regnames.
1204         * ppc-dis.c: Include "libiberty.h".
1205         (ppc_opts): Add "32" and "64" entries.
1206         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1207         (powerpc_init_dialect): Add break to switch statement.
1208         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1209         (disassembler_options_powerpc): New function.
1210         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1211         Remove printing of "32" and "64".
1212         * s390-dis.c: Include "libiberty.h".
1213         (init_flag): Remove unneeded variable.
1214         (struct s390_options_t): New structure type.
1215         (options): New structure.
1216         (init_disasm): Rename from this...
1217         (disassemble_init_s390): ...to this.  Add initializations for
1218         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1219         (print_insn_s390): Delete call to init_disasm.
1220         (disassembler_options_s390): New function.
1221         (print_s390_disassembler_options): Print using information from
1222         struct 'options'.
1223         * po/opcodes.pot: Regenerate.
1224
1225 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1226
1227         * i386-dis.c (PCMPESTR_Fixup): New.
1228         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1229         (prefix_table): Use PCMPESTR_Fixup.
1230         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1231         PCMPESTR_Fixup.
1232         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1233         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1234         Split 64-bit and non-64-bit variants.
1235         * opcodes/i386-tbl.h: Re-generate.
1236
1237 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1238
1239         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1240         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1241         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1242         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1243         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1244         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1245         (OP_SVE_V_HSD): New macros.
1246         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1247         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1248         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1249         (aarch64_opcode_table): Add new SVE instructions.
1250         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1251         for rotation operands.  Add new SVE operands.
1252         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1253         (ins_sve_quad_index): Likewise.
1254         (ins_imm_rotate): Split into...
1255         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1256         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1257         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1258         functions.
1259         (aarch64_ins_sve_addr_ri_s4): New function.
1260         (aarch64_ins_sve_quad_index): Likewise.
1261         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1262         * aarch64-asm-2.c: Regenerate.
1263         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1264         (ext_sve_quad_index): Likewise.
1265         (ext_imm_rotate): Split into...
1266         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1267         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1268         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1269         functions.
1270         (aarch64_ext_sve_addr_ri_s4): New function.
1271         (aarch64_ext_sve_quad_index): Likewise.
1272         (aarch64_ext_sve_index): Allow quad indices.
1273         (do_misc_decoding): Likewise.
1274         * aarch64-dis-2.c: Regenerate.
1275         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1276         aarch64_field_kinds.
1277         (OPD_F_OD_MASK): Widen by one bit.
1278         (OPD_F_NO_ZR): Bump accordingly.
1279         (get_operand_field_width): New function.
1280         * aarch64-opc.c (fields): Add new SVE fields.
1281         (operand_general_constraint_met_p): Handle new SVE operands.
1282         (aarch64_print_operand): Likewise.
1283         * aarch64-opc-2.c: Regenerate.
1284
1285 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1286
1287         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1288         (aarch64_feature_compnum): ...this.
1289         (SIMD_V8_3): Replace with...
1290         (COMPNUM): ...this.
1291         (CNUM_INSN): New macro.
1292         (aarch64_opcode_table): Use it for the complex number instructions.
1293
1294 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1295
1296         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1297
1298 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1299
1300         Add support for associating SPARC ASIs with an architecture level.
1301         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1302         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1303         decoding of SPARC ASIs.
1304
1305 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1306
1307         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1308         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1309
1310 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1311
1312         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1313         1 (instead of to itself). Correct typo.
1314
1315 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1316
1317         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1318         pseudoinstructions.
1319
1320 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1321
1322         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1323         (aarch64_sys_reg_supported_p): Handle them.
1324
1325 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1326
1327         * arc-opc.c (UIMM6_20R): Define.
1328         (SIMM12_20): Use above.
1329         (SIMM12_20R): Define.
1330         (SIMM3_5_S): Use above.
1331         (UIMM7_A32_11R_S): Define.
1332         (UIMM7_9_S): Use above.
1333         (UIMM3_13R_S): Define.
1334         (SIMM11_A32_7_S): Use above.
1335         (SIMM9_8R): Define.
1336         (UIMM10_A32_8_S): Use above.
1337         (UIMM8_8R_S): Define.
1338         (W6): Use above.
1339         (arc_relax_opcodes): Use all above defines.
1340
1341 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1342
1343         * arc-regs.h: Distinguish some of the registers different on
1344         ARC700 and HS38 cpus.
1345
1346 2017-02-14  Alan Modra  <amodra@gmail.com>
1347
1348         PR 21118
1349         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1350         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1351
1352 2017-02-11  Stafford Horne  <shorne@gmail.com>
1353             Alan Modra  <amodra@gmail.com>
1354
1355         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1356         Use insn_bytes_value and insn_int_value directly instead.  Don't
1357         free allocated memory until function exit.
1358
1359 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1360
1361         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1362
1363 2017-02-03  Nick Clifton  <nickc@redhat.com>
1364
1365         PR 21096
1366         * aarch64-opc.c (print_register_list): Ensure that the register
1367         list index will fir into the tb buffer.
1368         (print_register_offset_address): Likewise.
1369         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1370
1371 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1372
1373         PR 21056
1374         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1375         instructions when the previous fetch packet ends with a 32-bit
1376         instruction.
1377
1378 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1379
1380         * pru-opc.c: Remove vague reference to a future GDB port.
1381
1382 2017-01-20  Nick Clifton  <nickc@redhat.com>
1383
1384         * po/ga.po: Updated Irish translation.
1385
1386 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1387
1388         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1389
1390 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1391
1392         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1393         if FETCH_DATA returns 0.
1394         (m68k_scan_mask): Likewise.
1395         (print_insn_m68k): Update code to handle -1 return value.
1396
1397 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1398
1399         * m68k-dis.c (enum print_insn_arg_error): New.
1400         (NEXTBYTE): Replace -3 with
1401         PRINT_INSN_ARG_MEMORY_ERROR.
1402         (NEXTULONG): Likewise.
1403         (NEXTSINGLE): Likewise.
1404         (NEXTDOUBLE): Likewise.
1405         (NEXTDOUBLE): Likewise.
1406         (NEXTPACKED): Likewise.
1407         (FETCH_ARG): Likewise.
1408         (FETCH_DATA): Update comments.
1409         (print_insn_arg): Update comments. Replace magic numbers with
1410         enum.
1411         (match_insn_m68k): Likewise.
1412
1413 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1414
1415         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1416         * i386-dis-evex.h (evex_table): Updated.
1417         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1418         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1419         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1420         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1421         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1422         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1423         * i386-init.h: Regenerate.
1424         * i386-tbl.h: Ditto.
1425
1426 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1427
1428         * msp430-dis.c (msp430_singleoperand): Return -1 if
1429         msp430dis_opcode_signed returns false.
1430         (msp430_doubleoperand): Likewise.
1431         (msp430_branchinstr): Return -1 if
1432         msp430dis_opcode_unsigned returns false.
1433         (msp430x_calla_instr): Likewise.
1434         (print_insn_msp430): Likewise.
1435
1436 2017-01-05  Nick Clifton  <nickc@redhat.com>
1437
1438         PR 20946
1439         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1440         could not be matched.
1441         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1442         NULL.
1443
1444 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1445
1446         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1447         (aarch64_opcode_table): Use RCPC_INSN.
1448
1449 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1450
1451         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1452         extension.
1453         * riscv-opcodes/all-opcodes: Likewise.
1454
1455 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1456
1457         * riscv-dis.c (print_insn_args): Add fall through comment.
1458
1459 2017-01-03  Nick Clifton  <nickc@redhat.com>
1460
1461         * po/sr.po: New Serbian translation.
1462         * configure.ac (ALL_LINGUAS): Add sr.
1463         * configure: Regenerate.
1464
1465 2017-01-02  Alan Modra  <amodra@gmail.com>
1466
1467         * epiphany-desc.h: Regenerate.
1468         * epiphany-opc.h: Regenerate.
1469         * fr30-desc.h: Regenerate.
1470         * fr30-opc.h: Regenerate.
1471         * frv-desc.h: Regenerate.
1472         * frv-opc.h: Regenerate.
1473         * ip2k-desc.h: Regenerate.
1474         * ip2k-opc.h: Regenerate.
1475         * iq2000-desc.h: Regenerate.
1476         * iq2000-opc.h: Regenerate.
1477         * lm32-desc.h: Regenerate.
1478         * lm32-opc.h: Regenerate.
1479         * m32c-desc.h: Regenerate.
1480         * m32c-opc.h: Regenerate.
1481         * m32r-desc.h: Regenerate.
1482         * m32r-opc.h: Regenerate.
1483         * mep-desc.h: Regenerate.
1484         * mep-opc.h: Regenerate.
1485         * mt-desc.h: Regenerate.
1486         * mt-opc.h: Regenerate.
1487         * or1k-desc.h: Regenerate.
1488         * or1k-opc.h: Regenerate.
1489         * xc16x-desc.h: Regenerate.
1490         * xc16x-opc.h: Regenerate.
1491         * xstormy16-desc.h: Regenerate.
1492         * xstormy16-opc.h: Regenerate.
1493
1494 2017-01-02  Alan Modra  <amodra@gmail.com>
1495
1496         Update year range in copyright notice of all files.
1497
1498 For older changes see ChangeLog-2016
1499 \f
1500 Copyright (C) 2017 Free Software Foundation, Inc.
1501
1502 Copying and distribution of this file, with or without modification,
1503 are permitted in any medium without royalty provided the copyright
1504 notice and this notice are preserved.
1505
1506 Local Variables:
1507 mode: change-log
1508 left-margin: 8
1509 fill-column: 74
1510 version-control: never
1511 End: